[AArch64] Make Read Write System Registers Read Only

[LukeGeeson]

Summary

This patch makes the following System Registers Read Only:

• CurrentEL
• ICH_MISR_EL2
• PMBIDR_EL1
• PMSIDR_EL1

as found in:
https://developer.arm.com/docs/ddi0595/e/aarch64-system-registers

Relative line numbers were also added to the tests so we get more
informative error messages on failure.

[simon_tatham]

Mostly LGTM, except for test nitpicks.

llvm/test/MC/AArch64/arm64-system-encoding.s

169–170

I think it would be much more readable to move this check and the line that invoked it into their own separate section of the test file, so that the checks are right next to the input instruction.

The way you've done it in armv8.2a-statistical-profiling.s for PMBIDR_EL1 and PMSIDR_EL1 looks fine to me.

llvm/test/MC/AArch64/basic-a64-instructions.s

4059–4060

Same comment here.

llvm/test/MC/AArch64/gicv3-regs.s

203–204

And here.

[ostannard]

llvm/test/MC/AArch64/arm64-system-encoding.s

169–170

The NOECV check prefix isn't used by any FileCheck commands.

llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s

1–10

The stderr from this llvm-mc execution is redirected to a temp file, but not checked.

7

Why are you just checking msr, and not mrs or psb?

llvm/test/MC/AArch64/basic-a64-instructions.s

4059–4060

This should be moved to basic-a64-diagnostics.s, there's a block of tests like this around line 3600.

llvm/test/MC/AArch64/gicv3-regs.s

203–204

Move to gicv3-regs-diagnostics.s.

[LukeGeeson]

Moved erroneous changes into diagnostic files, fixed FileCheck output to handle errors, added instructions to NO_SPE_OUT

[LukeGeeson]

llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s

1–10

added FileCheck command

7

good spot, fixed

[ostannard]

llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s

7

This is now checking that the string msr, mrs, psb doesn't appear in the output, which isn't what we want to test. It also doesn't need the regex. Something like this would work (not actually tested):

// NO_SPE_OUT-NOT: msr
// NO_SPE_OUT-NOT: mrs
// NO_SPE_OUT-NOT: psb

[LukeGeeson]

Corrected Filecheck checks

[ostannard]

LGTM, thanks.

[LukeGeeson]

Pushed as commit https://github.com/llvm/llvm-project/commit/a67db83681f3dfe2950ad8d2b2addb5d6f175ad3

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : RWSysReg<"ELR_EL2",            0b11, 0b100, 0b0100, 0b0000, 0b001>;
 def : RWSysReg<"ELR_EL3",            0b11, 0b110, 0b0100, 0b0000, 0b001>;
 def : RWSysReg<"SP_EL0",             0b11, 0b000, 0b0100, 0b0001, 0b000>;
 def : RWSysReg<"SP_EL1",             0b11, 0b100, 0b0100, 0b0001, 0b000>;
 def : RWSysReg<"SP_EL2",             0b11, 0b110, 0b0100, 0b0001, 0b000>;
 def : RWSysReg<"SPSel",              0b11, 0b000, 0b0100, 0b0010, 0b000>;
 def : RWSysReg<"NZCV",               0b11, 0b011, 0b0100, 0b0010, 0b000>;
 def : RWSysReg<"DAIF",               0b11, 0b011, 0b0100, 0b0010, 0b001>;
-def : RWSysReg<"CurrentEL",          0b11, 0b000, 0b0100, 0b0010, 0b010>;
+def : ROSysReg<"CurrentEL",          0b11, 0b000, 0b0100, 0b0010, 0b010>;
 def : RWSysReg<"SPSR_irq",           0b11, 0b100, 0b0100, 0b0011, 0b000>;
 def : RWSysReg<"SPSR_abt",           0b11, 0b100, 0b0100, 0b0011, 0b001>;
 def : RWSysReg<"SPSR_und",           0b11, 0b100, 0b0100, 0b0011, 0b010>;
 def : RWSysReg<"SPSR_fiq",           0b11, 0b100, 0b0100, 0b0011, 0b011>;
 def : RWSysReg<"FPCR",               0b11, 0b011, 0b0100, 0b0100, 0b000>;
 def : RWSysReg<"FPSR",               0b11, 0b011, 0b0100, 0b0100, 0b001>;
 def : RWSysReg<"DSPSR_EL0",          0b11, 0b011, 0b0100, 0b0101, 0b000>;
 def : RWSysReg<"DLR_EL0",            0b11, 0b011, 0b0100, 0b0101, 0b001>;

 def : RWSysReg<"ICH_AP0R1_EL2",      0b11, 0b100, 0b1100, 0b1000, 0b001>;
 def : RWSysReg<"ICH_AP0R2_EL2",      0b11, 0b100, 0b1100, 0b1000, 0b010>;
 def : RWSysReg<"ICH_AP0R3_EL2",      0b11, 0b100, 0b1100, 0b1000, 0b011>;
 def : RWSysReg<"ICH_AP1R0_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b000>;
 def : RWSysReg<"ICH_AP1R1_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b001>;
 def : RWSysReg<"ICH_AP1R2_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b010>;
 def : RWSysReg<"ICH_AP1R3_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b011>;
 def : RWSysReg<"ICH_HCR_EL2",        0b11, 0b100, 0b1100, 0b1011, 0b000>;
-def : RWSysReg<"ICH_MISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b010>;
+def : ROSysReg<"ICH_MISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b010>;
 def : RWSysReg<"ICH_VMCR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b111>;
 def : RWSysReg<"ICH_VSEIR_EL2",      0b11, 0b100, 0b1100, 0b1001, 0b100>;
 def : RWSysReg<"ICH_LR0_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b000>;
 def : RWSysReg<"ICH_LR1_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b001>;
 def : RWSysReg<"ICH_LR2_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b010>;
 def : RWSysReg<"ICH_LR3_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b011>;
 def : RWSysReg<"ICH_LR4_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b100>;
 def : RWSysReg<"ICH_LR5_EL2",        0b11, 0b100, 0b1100, 0b1100, 0b101>;

 def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;
 
 // v8.2a "Statistical Profiling extension" registers
 //                            Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::FeatureSPE} }] in {
 def : RWSysReg<"PMBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b000>;
 def : RWSysReg<"PMBPTR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b001>;
 def : RWSysReg<"PMBSR_EL1",     0b11, 0b000, 0b1001, 0b1010, 0b011>;
-def : RWSysReg<"PMBIDR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b111>;
+def : ROSysReg<"PMBIDR_EL1",    0b11, 0b000, 0b1001, 0b1010, 0b111>;
 def : RWSysReg<"PMSCR_EL2",     0b11, 0b100, 0b1001, 0b1001, 0b000>;
 def : RWSysReg<"PMSCR_EL12",    0b11, 0b101, 0b1001, 0b1001, 0b000>;
 def : RWSysReg<"PMSCR_EL1",     0b11, 0b000, 0b1001, 0b1001, 0b000>;
 def : RWSysReg<"PMSICR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b010>;
 def : RWSysReg<"PMSIRR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b011>;
 def : RWSysReg<"PMSFCR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b100>;
 def : RWSysReg<"PMSEVFR_EL1",   0b11, 0b000, 0b1001, 0b1001, 0b101>;
 def : RWSysReg<"PMSLATFR_EL1",  0b11, 0b000, 0b1001, 0b1001, 0b110>;
-def : RWSysReg<"PMSIDR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b111>;
+def : ROSysReg<"PMSIDR_EL1",    0b11, 0b000, 0b1001, 0b1001, 0b111>;
 }
 
 // v8.2a "RAS extension" registers
 //                         Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::FeatureRAS} }] in {
 def : RWSysReg<"ERRSELR_EL1",   0b11, 0b000, 0b0101, 0b0011, 0b001>;
 def : RWSysReg<"ERXCTLR_EL1",   0b11, 0b000, 0b0101, 0b0100, 0b001>;
 def : RWSysReg<"ERXSTATUS_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b010>;

llvm/test/MC/AArch64/arm64-system-encoding.s

;-----------------------------------------------------------------------------
   msr CNTV_CTL_EL0, x3
   msr CNTV_CVAL_EL0, x3
   msr CNTV_TVAL_EL0, x3
   msr CONTEXTIDR_EL1, x3
   msr CPACR_EL1, x3
   msr CPTR_EL2, x3
   msr CPTR_EL3, x3
   msr CSSELR_EL1, x3
-  msr CURRENTEL, x3
   msr DACR32_EL2, x3
   msr ESR_EL1, x3
   msr ESR_EL2, x3
   msr ESR_EL3, x3
   msr FAR_EL1, x3
   msr FAR_EL2, x3
   msr FAR_EL3, x3
   msr FPEXC32_EL2, x3

 ; CHECK: msr CNTVOFF_EL2, x3            ; encoding: [0x63,0xe0,0x1c,0xd5]
 ; CHECK: msr CNTV_CTL_EL0, x3           ; encoding: [0x23,0xe3,0x1b,0xd5]
 ; CHECK: msr CNTV_CVAL_EL0, x3          ; encoding: [0x43,0xe3,0x1b,0xd5]
 ; CHECK: msr CNTV_TVAL_EL0, x3          ; encoding: [0x03,0xe3,0x1b,0xd5]
 ; CHECK: msr CONTEXTIDR_EL1, x3         ; encoding: [0x23,0xd0,0x18,0xd5]
 ; CHECK: msr CPACR_EL1, x3              ; encoding: [0x43,0x10,0x18,0xd5]
 ; CHECK: msr CPTR_EL2, x3               ; encoding: [0x43,0x11,0x1c,0xd5]
 ; CHECK: msr CPTR_EL3, x3               ; encoding: [0x43,0x11,0x1e,0xd5]
 ; CHECK: msr CSSELR_EL1, x3             ; encoding: [0x03,0x00,0x1a,0xd5]
-; CHECK: msr CurrentEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]
 ; CHECK: msr DACR32_EL2, x3             ; encoding: [0x03,0x30,0x1c,0xd5]
 ; CHECK: msr ESR_EL1, x3                ; encoding: [0x03,0x52,0x18,0xd5]
 ; CHECK: msr ESR_EL2, x3                ; encoding: [0x03,0x52,0x1c,0xd5]
 ; CHECK: msr ESR_EL3, x3                ; encoding: [0x03,0x52,0x1e,0xd5]
 ; CHECK: msr FAR_EL1, x3                ; encoding: [0x03,0x60,0x18,0xd5]
 ; CHECK: msr FAR_EL2, x3                ; encoding: [0x03,0x60,0x1c,0xd5]
 ; CHECK: msr FAR_EL3, x3                ; encoding: [0x03,0x60,0x1e,0xd5]
 ; CHECK: msr FPEXC32_EL2, x3            ; encoding: [0x03,0x53,0x1c,0xd5]
 ; CHECK: msr HACR_EL2, x3               ; encoding: [0xe3,0x11,0x1c,0xd5]

 ; CHECK: msr VPIDR_EL2, x3              ; encoding: [0x03,0x00,0x1c,0xd5]
 ; CHECK: msr VTCR_EL2, x3               ; encoding: [0x43,0x21,0x1c,0xd5]
 ; CHECK: msr VTTBR_EL2, x3              ; encoding: [0x03,0x21,0x1c,0xd5]
 ; CHECK: msr  SPSel, x3                 ; encoding: [0x03,0x42,0x18,0xd5]
 ; CHECK: msr  S3_2_C11_C6_4, x1         ; encoding: [0x81,0xb6,0x1a,0xd5]
 ; CHECK: msr  S0_0_C0_C0_0, x0          ; encoding: [0x00,0x00,0x00,0xd5]
 ; CHECK: msr  S1_2_C3_C4_5, x2          ; encoding: [0xa2,0x34,0x0a,0xd5]
 
+// Readonly system registers: writing to them gives an error
+  msr CURRENTEL, x3
+; CHECK-ERRORS: :[[@LINE-1]]:7: error: expected writable system register or pstate
+
   mrs x3, ACTLR_EL1
   mrs x3, ACTLR_EL2
   mrs x3, ACTLR_EL3
   mrs x3, AFSR0_EL1
   mrs x3, AFSR0_EL2
   mrs x3, AFSR0_EL3
   mrs x3, AIDR_EL1
   mrs x3, AFSR1_EL1

llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe < %s | FileCheck %s
-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=NO_SPE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+spe       < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=ERROR %s < %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding                   < %s 2> %t | FileCheck --check-prefix=NO_SPE_OUT %s
+// RUN: FileCheck --check-prefix=NO_SPE %s < %t
+
+// NO_SPE_OUT-NOT: msr
+// NO_SPE_OUT-NOT: mrs
+// NO_SPE_OUT-NOT: psb
 
   psb csync
 // CHECK: psb csync              // encoding: [0x3f,0x22,0x03,0xd5]
 // NO_SPE:  instruction requires: spe
 
   msr pmblimitr_el1, x0
   msr pmbptr_el1, x0
   msr pmbsr_el1, x0
-  msr pmbidr_el1, x0
   msr pmscr_el2, x0
   msr pmscr_el12, x0
   msr pmscr_el1, x0
   msr pmsicr_el1, x0
   msr pmsirr_el1, x0
   msr pmsfcr_el1, x0
   msr pmsevfr_el1, x0
   msr pmslatfr_el1, x0
-  msr pmsidr_el1, x0
 // CHECK:     msr PMBLIMITR_EL1, x0       // encoding: [0x00,0x9a,0x18,0xd5]
 // CHECK:     msr PMBPTR_EL1, x0          // encoding: [0x20,0x9a,0x18,0xd5]
 // CHECK:     msr PMBSR_EL1, x0           // encoding: [0x60,0x9a,0x18,0xd5]
-// CHECK:     msr PMBIDR_EL1, x0          // encoding: [0xe0,0x9a,0x18,0xd5]
 // CHECK:     msr PMSCR_EL2, x0           // encoding: [0x00,0x99,0x1c,0xd5]
 // CHECK:     msr PMSCR_EL12, x0          // encoding: [0x00,0x99,0x1d,0xd5]
 // CHECK:     msr PMSCR_EL1, x0           // encoding: [0x00,0x99,0x18,0xd5]
 // CHECK:     msr PMSICR_EL1, x0          // encoding: [0x40,0x99,0x18,0xd5]
 // CHECK:     msr PMSIRR_EL1, x0          // encoding: [0x60,0x99,0x18,0xd5]
 // CHECK:     msr PMSFCR_EL1, x0          // encoding: [0x80,0x99,0x18,0xd5]
 // CHECK:     msr PMSEVFR_EL1, x0         // encoding: [0xa0,0x99,0x18,0xd5]
 // CHECK:     msr PMSLATFR_EL1, x0        // encoding: [0xc0,0x99,0x18,0xd5]
-// CHECK:     msr PMSIDR_EL1, x0          // encoding: [0xe0,0x99,0x18,0xd5]
-// NO_SPE: error: expected writable system register or pstate
-// NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 // NO_SPE: error: expected writable system register or pstate
 
+
+// Readonly system registers: writing to them gives an error
+  msr pmbidr_el1, x0
+  msr pmsidr_el1, x0
+// ERROR: :[[@LINE-2]]:7: error: expected writable system register or pstate
+// ERROR: :[[@LINE-2]]:7: error: expected writable system register or pstate
+// NO_SPE: :[[@LINE-4]]:7: error: expected writable system register or pstate
+// NO_SPE: :[[@LINE-4]]:7: error: expected writable system register or pstate
+
 mrs x0, pmblimitr_el1
   mrs x0, pmbptr_el1
   mrs x0, pmbsr_el1
   mrs x0, pmbidr_el1
   mrs x0, pmscr_el2
   mrs x0, pmscr_el12
   mrs x0, pmscr_el1
   mrs x0, pmsicr_el1

llvm/test/MC/AArch64/basic-a64-diagnostics.s

 // CHECK-ERROR-NEXT: error: 'sy' or #imm operand expected
 // CHECK-ERROR-NEXT:        isb foo
 // CHECK-ERROR-NEXT:            ^
 
         msr daifset, x4
         msr spsel, #-1
         msr spsel #-1
         msr daifclr, #16
-// CHECK-ERROR: [[@LINE-4]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
-// CHECK-ERROR: [[@LINE-4]]:20: error: {{expected|immediate must be an}} integer in range [0, 15]
-// CHECK-ERROR: [[@LINE-4]]:{{9|19}}: error: {{too few operands for instruction|expected comma before next operand|unexpected token in argument list}}
-// CHECK-ERROR: [[@LINE-4]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
+        msr CurrentEL, x12
+// CHECK-ERROR: [[@LINE-5]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
+// CHECK-ERROR: [[@LINE-5]]:20: error: {{expected|immediate must be an}} integer in range [0, 15]
+// CHECK-ERROR: [[@LINE-5]]:{{9|19}}: error: {{too few operands for instruction|expected comma before next operand|unexpected token in argument list}}
+// CHECK-ERROR: [[@LINE-5]]:22: error: {{expected|immediate must be an}} integer in range [0, 15]
+// CHECK-ERROR: [[@LINE-5]]:13: error: expected writable system register or pstate
 
         sys #8, c1, c2, #7, x9
         sys #3, c16, c2, #3, x10
         sys #2, c11, c16, #5
         sys #4, c9, c8, #8, xzr
         sysl x11, #8, c1, c2, #7
         sysl x13, #3, c16, c2, #3
         sysl x9, #2, c11, c16, #5

llvm/test/MC/AArch64/basic-a64-instructions.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 %s | FileCheck %s
   .globl _func
 
 // Check that the assembler can handle the documented syntax from the ARM ARM.
 // For complex constructs like shifter operands, check more thoroughly for them
 // once then spot check that following instructions accept the form generally.
 // This gives us good coverage while keeping the overall size of the test
 // more reasonable.
 
// CHECK: tlbi    vaale1, x25             // encoding: [0xf9,0x87,0x08,0xd5]
   msr ELR_EL2, x12
   msr ELR_EL3, x12
   msr SP_EL0, x12
   msr SP_EL1, x12
   msr SP_EL2, x12
   msr SPSel, x12
   msr NZCV, x12
   msr DAIF, x12
-  msr CurrentEL, x12
   msr SPSR_irq, x12
   msr SPSR_abt, x12
   msr SPSR_und, x12
   msr SPSR_fiq, x12
   msr FPCR, x12
   msr FPSR, x12
   msr DSPSR_EL0, x12
   msr DLR_EL0, x12

 // CHECK: msr      {{elr_el1|ELR_EL1}}, x12               // encoding: [0x2c,0x40,0x18,0xd5]
 // CHECK: msr      {{elr_el2|ELR_EL2}}, x12               // encoding: [0x2c,0x40,0x1c,0xd5]
 // CHECK: msr      {{elr_el3|ELR_EL3}}, x12               // encoding: [0x2c,0x40,0x1e,0xd5]
 // CHECK: msr      {{sp_el0|SP_EL0}}, x12                // encoding: [0x0c,0x41,0x18,0xd5]
 // CHECK: msr      {{sp_el1|SP_EL1}}, x12                // encoding: [0x0c,0x41,0x1c,0xd5]
 // CHECK: msr      {{sp_el2|SP_EL2}}, x12                // encoding: [0x0c,0x41,0x1e,0xd5]
 // CHECK: msr      {{SPSel|SPSEL}}, x12                 // encoding: [0x0c,0x42,0x18,0xd5]
 // CHECK: msr      {{nzcv|NZCV}}, x12                  // encoding: [0x0c,0x42,0x1b,0xd5]
 // CHECK: msr      {{daif|DAIF}}, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]
-// CHECK: msr      {{CurrentEL|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]
 // CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
 // CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12              // encoding: [0x2c,0x43,0x1c,0xd5]
 // CHECK: msr      {{SPSR_und|SPSR_UND}}, x12              // encoding: [0x4c,0x43,0x1c,0xd5]
 // CHECK: msr      {{SPSR_fiq|SPSR_FIQ}}, x12              // encoding: [0x6c,0x43,0x1c,0xd5]
 // CHECK: msr      {{fpcr|FPCR}}, x12                  // encoding: [0x0c,0x44,0x1b,0xd5]
 // CHECK: msr      {{fpsr|FPSR}}, x12                  // encoding: [0x2c,0x44,0x1b,0xd5]
 // CHECK: msr      {{dspsr_el0|DSPSR_EL0}}, x12             // encoding: [0x0c,0x45,0x1b,0xd5]
 // CHECK: msr      {{dlr_el0|DLR_EL0}}, x12               // encoding: [0x2c,0x45,0x1b,0xd5]
 // CHECK: msr      {{ifsr32_el2|IFSR32_EL2}}, x12            // encoding: [0x2c,0x50,0x1c,0xd5]

llvm/test/MC/AArch64/gicv3-regs-diagnostics.s

// CHECK-NEXT:                  ^
         msr icc_iar1_el1, x16
         msr icc_iar0_el1, x19
         msr icc_hppir1_el1, x29
         msr icc_hppir0_el1, x14
         msr icc_rpr_el1, x6
         msr ich_vtr_el2, x8
         msr ich_eisr_el2, x22
         msr ich_elsr_el2, x8
+        msr ich_misr_el2, x10
 // CHECK: error: expected writable system register or pstate
 // CHECK-NEXT:         msr icc_iar1_el1, x16
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr icc_iar0_el1, x19
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr icc_hppir1_el1, x29
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr icc_hppir0_el1, x14
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr icc_rpr_el1, x6
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr ich_vtr_el2, x8
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr ich_eisr_el2, x22
 // CHECK-NEXT:             ^
 // CHECK-NEXT: error: expected writable system register or pstate
 // CHECK-NEXT:         msr ich_elsr_el2, x8
 // CHECK-NEXT:             ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT:         msr ich_misr_el2, x10
+// CHECK-NEXT:             ^

llvm/test/MC/AArch64/gicv3-regs.s

- // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding %s | FileCheck %s
 
         mrs x8, icc_iar1_el1
         mrs x26, icc_iar0_el1
         mrs x2, icc_hppir1_el1
         mrs x17, icc_hppir0_el1
         mrs x29, icc_rpr_el1
         mrs x4, ich_vtr_el2
         mrs x24, ich_eisr_el2
// CHECK: mrs      x8, {{ich_lr15_el2|ICH_LR15_EL2}}           // encoding: [0xe8,0xcd,0x3c,0xd5]
         msr ich_ap0r1_el2, x27
         msr ich_ap0r2_el2, x7
         msr ich_ap0r3_el2, x1
         msr ich_ap1r0_el2, x7
         msr ich_ap1r1_el2, x12
         msr ich_ap1r2_el2, x14
         msr ich_ap1r3_el2, x13
         msr ich_hcr_el2, x1
-        msr ich_misr_el2, x10
         msr ich_vmcr_el2, x24
         msr ich_vseir_el2, x29
         msr ich_lr0_el2, x26
         msr ich_lr1_el2, x9
         msr ich_lr2_el2, x18
         msr ich_lr3_el2, x26
         msr ich_lr4_el2, x22
         msr ich_lr5_el2, x26

 // CHECK: msr      {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2          // encoding: [0x02,0xc8,0x1c,0xd5]
 // CHECK: msr      {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27         // encoding: [0x3b,0xc8,0x1c,0xd5]
 // CHECK: msr      {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7          // encoding: [0x47,0xc8,0x1c,0xd5]
 // CHECK: msr      {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1          // encoding: [0x61,0xc8,0x1c,0xd5]
 // CHECK: msr      {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7          // encoding: [0x07,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12         // encoding: [0x2c,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14         // encoding: [0x4e,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13         // encoding: [0x6d,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1            // encoding: [0x01,0xcb,0x1c,0xd5]
-// CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10          // encoding: [0x4a,0xcb,0x1c,0xd5]
 // CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24          // encoding: [0xf8,0xcb,0x1c,0xd5]
 // CHECK: msr      {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29         // encoding: [0x9d,0xc9,0x1c,0xd5]
 // CHECK: msr      {{ich_lr0_el2|ICH_LR0_EL2}}, x26           // encoding: [0x1a,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr1_el2|ICH_LR1_EL2}}, x9            // encoding: [0x29,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr2_el2|ICH_LR2_EL2}}, x18           // encoding: [0x52,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr3_el2|ICH_LR3_EL2}}, x26           // encoding: [0x7a,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr4_el2|ICH_LR4_EL2}}, x22           // encoding: [0x96,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr5_el2|ICH_LR5_EL2}}, x26           // encoding: [0xba,0xcc,0x1c,0xd5]
 // CHECK: msr      {{ich_lr6_el2|ICH_LR6_EL2}}, x27           // encoding: [0xdb,0xcc,0x1c,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.2a-statistical-profiling.txt

 [0xc0,0x99,0x18,0xd5]
 [0xe0,0x99,0x18,0xd5]
 # CHECK: msr PMBLIMITR_EL1, x0
 # NO_SPE: msr S3_0_C9_C10_0, x0
 # CHECK: msr PMBPTR_EL1, x0
 # NO_SPE: msr S3_0_C9_C10_1, x0
 # CHECK: msr PMBSR_EL1, x0
 # NO_SPE: msr S3_0_C9_C10_3, x0
-# CHECK: msr PMBIDR_EL1, x0
+# CHECK: msr S3_0_C9_C10_7, x0
 # NO_SPE: msr S3_0_C9_C10_7, x0
 # CHECK: msr PMSCR_EL2, x0
 # NO_SPE: msr S3_4_C9_C9_0, x0
 # CHECK: msr PMSCR_EL12, x0
 # NO_SPE: msr S3_5_C9_C9_0, x0
 # CHECK: msr PMSCR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_0, x0
 # CHECK: msr PMSICR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_2, x0
 # CHECK: msr PMSIRR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_3, x0
 # CHECK: msr PMSFCR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_4, x0
 # CHECK: msr PMSEVFR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_5, x0
 # CHECK: msr PMSLATFR_EL1, x0
 # NO_SPE: msr S3_0_C9_C9_6, x0
-# CHECK: msr PMSIDR_EL1, x0
+# CHECK: msr S3_0_C9_C9_7, x0
 # NO_SPE: msr S3_0_C9_C9_7, x0
 
 [0x00,0x9a,0x38,0xd5]
 [0x20,0x9a,0x38,0xd5]
 [0x60,0x9a,0x38,0xd5]
 [0xe0,0x9a,0x38,0xd5]
 [0x00,0x99,0x3c,0xd5]
 [0x00,0x99,0x3d,0xd5]

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # CHECK: msr      {{elr_el2|ELR_EL2}}, x12
 # CHECK: msr      {{elr_el3|ELR_EL3}}, x12
 # CHECK: msr      {{sp_el0|SP_EL0}}, x12
 # CHECK: msr      {{sp_el1|SP_EL1}}, x12
 # CHECK: msr      {{sp_el2|SP_EL2}}, x12
 # CHECK: msr      {{SPSel|SPSEL}}, x12
 # CHECK: msr      {{nzcv|NZCV}}, x12
 # CHECK: msr      {{daif|DAIF}}, x12
-# CHECK: msr      {{CurrentEL|CURRENTEL}}, x12
+# CHECK: msr      S3_0_C4_C2_2, x12
 # CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12
 # CHECK: msr      {{SPSR_abt|SPSR_ABT}}, x12
 # CHECK: msr      {{SPSR_und|SPSR_UND}}, x12
 # CHECK: msr      {{SPSR_fiq|SPSR_FIQ}}, x12
 # CHECK: msr      {{fpcr|FPCR}}, x12
 # CHECK: msr      {{fpsr|FPSR}}, x12
 # CHECK: msr      {{dspsr_el0|DSPSR_EL0}}, x12
 # CHECK: msr      {{dlr_el0|DLR_EL0}}, x12

llvm/test/MC/Disassembler/AArch64/gicv3-regs.txt

 # CHECK: msr      {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12
 0x4e 0xc9 0x1c 0xd5
 # CHECK: msr      {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14
 0x6d 0xc9 0x1c 0xd5
 # CHECK: msr      {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13
 0x1 0xcb 0x1c 0xd5
 # CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1
 0x4a 0xcb 0x1c 0xd5
-# CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10
+# CHECK: msr      S3_4_C12_C11_2, x10
 0xf8 0xcb 0x1c 0xd5
 # CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
 0x9d 0xc9 0x1c 0xd5
 # CHECK: msr      {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29
 0x1a 0xcc 0x1c 0xd5
 # CHECK: msr      {{ich_lr0_el2|ICH_LR0_EL2}}, x26
 0x29 0xcc 0x1c 0xd5
 # CHECK: msr      {{ich_lr1_el2|ICH_LR1_EL2}}, x9