[WebAssembly] Enable recently implemented SIMD operations

[tlively]

Summary

Moves a batch of instructions from unimplemented-simd128 to simd128
because they have recently become available in V8.

[merge_guards_bot]

Unit tests: pass. 62428 tests passed, 0 failed and 845 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64_f32, "LLif", "nc", "nontrapping-fptoint")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i64_f64, "LLid", "nc", "nontrapping-fptoint")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64_f64, "LLid", "nc", "nontrapping-fptoint")
 
 // SIMD builtins
 TARGET_BUILTIN(__builtin_wasm_swizzle_v8x16, "V16cV16cV16c", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i8x16, "iV16cIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i8x16, "iV16cIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i8x16, "iV16cIi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i16x8, "iV8sIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i16x8, "iV8sIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i16x8, "iV8sIi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extract_lane_i32x4, "iV4iIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_i64x2, "LLiV2LLiIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_i64x2, "LLiV2LLiIi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extract_lane_f32x4, "fV4fIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_f64x2, "dV2dIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_f64x2, "dV2dIi", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i8x16, "V16cV16cIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i16x8, "V8sV8sIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i32x4, "V4iV4iIii", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2LLiV2LLiIiLLi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2LLiV2LLiIiLLi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_f32x4, "V4fV4fIif", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_replace_lane_f64x2, "V2dV2dIid", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_replace_lane_f64x2, "V2dV2dIid", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i8x16, "V16cV16cV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i8x16, "V16cV16cV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i16x8, "V8sV8sV8s", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i8x16, "V16cV16cV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i8x16, "V16cV16cV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i16x8, "V8sV8sV8s", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, "V16cV16cV16c", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, "V8sV8sV8s", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, "V16cV16cV16c", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, "V8sV8sV8s", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, "iV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_any_true_i16x8, "iV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_any_true_i32x4, "iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_any_true_i64x2, "iV2LLi", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i8x16, "iV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i16x8, "iV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i32x4, "iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_all_true_i64x2, "iV2LLi", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_abs_f32x4, "V4fV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_abs_f64x2, "V2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_abs_f64x2, "V2dV2d", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_min_f32x4, "V4fV4fV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_f32x4, "V4fV4fV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_min_f64x2, "V2dV2dV2d", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_max_f64x2, "V2dV2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_min_f64x2, "V2dV2dV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_max_f64x2, "V2dV2dV2d", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_dot_s_i32x4_i16x8, "V4iV8sV8s", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_sqrt_f32x4, "V4fV4f", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_sqrt_f64x2, "V2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_sqrt_f32x4, "V4fV4f", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_sqrt_f64x2, "V2dV2d", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfma_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i64x2_f64x2, "V2LLiV2d", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i64x2_f64x2, "V2LLiV2d", "nc", "unimplemented-simd128")
 

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
   addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
   addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
   if (Subtarget->hasSIMD128()) {
     addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
-  }
-  if (Subtarget->hasUnimplementedSIMD128()) {
     addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
   }
   // Compute derived properties from the register classes.
   computeRegisterProperties(Subtarget->getRegisterInfo());
 
   setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
   setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   // Expand unavailable integer operations.
   for (auto Op :
        {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
         ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
         ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
     for (auto T : {MVT::i32, MVT::i64})
       setOperationAction(Op, T, Expand);
     if (Subtarget->hasSIMD128())
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
         setOperationAction(Op, T, Expand);
-    if (Subtarget->hasUnimplementedSIMD128())
-      setOperationAction(Op, MVT::v2i64, Expand);
   }
 
   // SIMD-specific configuration
   if (Subtarget->hasSIMD128()) {
     // Support saturating add for i8x16 and i16x8
     for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
       for (auto T : {MVT::v16i8, MVT::v8i16})
         setOperationAction(Op, T, Legal);
 
     // Custom lower BUILD_VECTORs to minimize number of replace_lanes
-    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
-      setOperationAction(ISD::BUILD_VECTOR, T, Custom);
-    if (Subtarget->hasUnimplementedSIMD128())
-      for (auto T : {MVT::v2i64, MVT::v2f64})
-        setOperationAction(ISD::BUILD_VECTOR, T, Custom);
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                   MVT::v2f64})
 
     // We have custom shuffle lowering to expose the shuffle mask
-    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
-      setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
-    if (Subtarget->hasUnimplementedSIMD128())
-      for (auto T: {MVT::v2i64, MVT::v2f64})
-        setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                   MVT::v2f64})
 
     // Custom lowering since wasm shifts must have a scalar shift amount
-    for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+    for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
         setOperationAction(Op, T, Custom);
-      if (Subtarget->hasUnimplementedSIMD128())
-        setOperationAction(Op, MVT::v2i64, Custom);
-    }
 
     // Custom lower lane accesses to expand out variable indices
-    for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
-        setOperationAction(Op, T, Custom);
-      if (Subtarget->hasUnimplementedSIMD128())
-        for (auto T : {MVT::v2i64, MVT::v2f64})
-          setOperationAction(Op, T, Custom);
-    }
+    for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                     MVT::v2f64})
 
     // There is no i64x2.mul instruction
+    // TODO: Actually, there is now. Implement it.
     setOperationAction(ISD::MUL, MVT::v2i64, Expand);
 
     // There are no vector select instructions
-    for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
-        setOperationAction(Op, T, Expand);
-      if (Subtarget->hasUnimplementedSIMD128())
-        for (auto T : {MVT::v2i64, MVT::v2f64})
-          setOperationAction(Op, T, Expand);
-    }
+    for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                     MVT::v2f64})
 
     // Expand integer operations supported for scalars but not SIMD
     for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
-                    ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+                    ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
         setOperationAction(Op, T, Expand);
-      if (Subtarget->hasUnimplementedSIMD128())
-        setOperationAction(Op, MVT::v2i64, Expand);
-    }
 
     // But we do have integer min and max operations
-    if (Subtarget->hasUnimplementedSIMD128()) {
-      for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
-        for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
-          setOperationAction(Op, T, Legal);
-    }
 
     // Expand float operations supported for scalars but not SIMD
     for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
                     ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
-                    ISD::FEXP, ISD::FEXP2, ISD::FRINT}) {
-      setOperationAction(Op, MVT::v4f32, Expand);
-      if (Subtarget->hasUnimplementedSIMD128())
-        setOperationAction(Op, MVT::v2f64, Expand);
-    }
+                    ISD::FEXP, ISD::FEXP2, ISD::FRINT})
+      for (auto T : {MVT::v4f32, MVT::v2f64})
+        setOperationAction(Op, T, Expand);
 
     // Expand operations not supported for i64x2 vectors
-    if (Subtarget->hasUnimplementedSIMD128())
-      for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)
-        setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);
 
-    // Expand additional SIMD ops that V8 hasn't implemented yet
-    if (!Subtarget->hasUnimplementedSIMD128()) {
-      setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
-      setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
-    }
+    // 64x2 conversions are not in the spec
+    if (!Subtarget->hasUnimplementedSIMD128())
+      for (auto Op :
+           {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT})
+        for (auto T : {MVT::v2i64, MVT::v2f64})
+          setOperationAction(Op, T, Expand);
   }
 
   // As a special case, these operators use the type to mean the type to
   // sign-extend from.
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   if (!Subtarget->hasSignExt()) {
     // Sign extends are legal only when extending a vector extract
     auto Action = Subtarget->hasSIMD128() ? Custom : Expand;

 SDValue WebAssemblyTargetLowering::LowerSETCC(SDValue Op,
                                               SelectionDAG &DAG) const {
   SDLoc DL(Op);
   // The legalizer does not know how to expand the comparison modes of i64x2
   // vectors because no comparison modes are supported. We could solve this by
   // expanding all i64x2 SETCC nodes, but that seems to expand f64x2 SETCC nodes
   // (which return i64x2 results) as well. So instead we manually unroll i64x2
   // comparisons here.
-  assert(Subtarget->hasUnimplementedSIMD128());
   assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);
   SmallVector<SDValue, 2> LHS, RHS;
   DAG.ExtractVectorElements(Op->getOperand(0), LHS);
   DAG.ExtractVectorElements(Op->getOperand(1), RHS);
   const SDValue &CC = Op->getOperand(2);
   auto MakeLane = [&](unsigned I) {
     return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I],
                        DAG.getConstant(uint64_t(-1), DL, MVT::i64),

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

 multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
   defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
                         !cast<PatFrag>("extract_i8x16"#sign)>;
   defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 4), sign,
                         !cast<PatFrag>("extract_i16x8"#sign)>;
 }
 
 defm "" : ExtractLaneExtended<"_s", 5>;
-let Predicates = [HasUnimplementedSIMD128] in
 defm "" : ExtractLaneExtended<"_u", 6>;
 defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
 defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
 defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
 defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>;
 
 // It would be more conventional to use unsigned extracts, but v8
 // doesn't implement them yet

 let isCommutable = 1 in {
 defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 94>;
 defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 95>;
 defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 96>;
 defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 97>;
 } // isCommutable = 1
 
 // Integer unsigned rounding average: avgr_u
-let isCommutable = 1, Predicates = [HasUnimplementedSIMD128] in {
+let isCommutable = 1 in {
 defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 217>;
 defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 218>;
 }
 
 def add_nuw : PatFrag<(ops node:$lhs, node:$rhs),
                       (add node:$lhs, node:$rhs),
                       "return N->getFlags().hasNoUnsignedWrap();">;
 

 
 // Absolute value: abs
 defm ABS : SIMDUnaryFP<fabs, "abs", 149>;
 
 // Negation: neg
 defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
 
 // Square root: sqrt
-let Predicates = [HasUnimplementedSIMD128] in
 defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point binary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
   defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
 }
 
 // Addition: add
 let isCommutable = 1 in
 defm ADD : SIMDBinaryFP<fadd, "add", 154>;
 
 // Subtraction: sub
 defm SUB : SIMDBinaryFP<fsub, "sub", 155>;
 
 // Multiplication: mul
 let isCommutable = 1 in
 defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
 
 // Division: div
-let Predicates = [HasUnimplementedSIMD128] in
 defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
 
 // NaN-propagating minimum: min
 defm MIN : SIMDBinaryFP<fminimum, "min", 158>;
 
 // NaN-propagating maximum: max
 defm MAX : SIMDBinaryFP<fmaximum, "max", 159>;
 
 //===----------------------------------------------------------------------===//
 // Conversions
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
                        string name, bits<32> simdop> {
   defm op#_#vec_t#_#arg_t :
     SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
            [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
            name#"\t$dst, $vec", name, simdop>;
 }
 
 // Integer to floating point: convert
 defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
 defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
+
+let Predicates = [HasUnimplementedSIMD128] in {
 defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
 defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
+}
 
 // Floating point to integer with saturation: trunc_sat
 defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
 defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
+
+let Predicates = [HasUnimplementedSIMD128] in {
 defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
 defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
+}
 
 // Widening operations
 multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
                      bits<32> baseInst> {
   defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed,
                         vec#".widen_low_"#arg#"_s", baseInst>;
   defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed,
                         vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>;

llvm/test/CodeGen/WebAssembly/simd-arith.ll

define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) {
   ret <4 x i32> %a
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: add_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = add <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: sub_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = sub <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; v2i64.mul is not in spec
 ; CHECK-LABEL: mul_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NOT: i64x2.mul
 ; SIMD128: i64x2.extract_lane
 ; SIMD128: i64.mul
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 

 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shr_u_vec_v2i64(<2 x i64> %v, <2 x i64> %x) {
   %a = lshr <2 x i64> %v, %x
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: and_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = and <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: or_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @or_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = or <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: xor_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = xor <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: not_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @not_v2i64(<2 x i64> %x) {
   %a = xor <2 x i64> %x, <i64 -1, i64 -1>
   ret <2 x i64> %a
 }
 

 define <2 x i64> @andnot_v2i64(<2 x i64> %x, <2 x i64> %y) {
  %inv_y = xor <2 x i64> %y, <i64 -1, i64 -1>
  %a = and <2 x i64> %x, %inv_y
  ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: bitselect_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
 ; SIMD128-FAST-NEXT: v128.not
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.and
 ; SIMD128-FAST-NEXT: v128.or
 ; SIMD128-FAST-NEXT: return

 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fsub <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: div_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-VM-NOT: f32x4.div
 ; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fdiv <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: mul_v4f32:
 ; NO-SIMD128-NOT: f32x4
 ; SIMD128-NEXT: .functype mul_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
   %a = fmul <4 x float> %x, %y
   ret <4 x float> %a
 }
 
 ; CHECK-LABEL: sqrt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-VM-NOT: f32x4.sqrt
 ; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
 define <4 x float> @sqrt_v4f32(<4 x float> %x) {
   %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
   ret <4 x float> %a
 }
%a = call <2 x double> @llvm.maximum.v2f64(
     <2 x double> <double 42., double 42.>,
     <2 x double> <double 5., double 5.>
   )
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: add_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fadd <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: sub_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fsub <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: div_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fdiv <2 x double> %x, %y
   ret <2 x double> %a
 }
 
 ; CHECK-LABEL: mul_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
   %a = fmul <2 x double> %x, %y
   ret <2 x double> %a
 }
 

llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll

-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that bitcasts between vector types are lowered to zero instructions
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: v16i8_to_v16i8:

 ; SIMD128: return $0
 define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
   %res = bitcast <16 x i8> %v to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: v16i8_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
   %res = bitcast <16 x i8> %v to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: v16i8_to_v4f32:
 ; NO-SIMD128-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
   %res = bitcast <16 x i8> %v to <4 x float>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: v16i8_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
   %res = bitcast <16 x i8> %v to <2 x double>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: v8i16_to_v16i8:
 ; NO-SIMD128-NOT: return $0

 ; SIMD128: return $0
 define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
   %res = bitcast <8 x i16> %v to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: v8i16_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
   %res = bitcast <8 x i16> %v to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: v8i16_to_v4f32:
 ; NO-SIMD128-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
   %res = bitcast <8 x i16> %v to <4 x float>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: v8i16_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
   %res = bitcast <8 x i16> %v to <2 x double>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: v4i32_to_v16i8:
 ; NO-SIMD128-NOT: return $0

 ; SIMD128: return $0
 define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
   %res = bitcast <4 x i32> %v to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: v4i32_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
   %res = bitcast <4 x i32> %v to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: v4i32_to_v4f32:
 ; NO-SIMD128-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
   %res = bitcast <4 x i32> %v to <4 x float>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: v4i32_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
   %res = bitcast <4 x i32> %v to <2 x double>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: v2i64_to_v16i8:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: v2i64_to_v8i16:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: v2i64_to_v4i32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: v2i64_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: v2i64_to_v4f32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <4 x float>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: v2i64_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <2 x double>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: v4f32_to_v16i8:
 ; NO-SIMD128-NOT: return $0

 ; SIMD128: return $0
 define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
   %res = bitcast <4 x float> %v to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: v4f32_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
   %res = bitcast <4 x float> %v to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: v4f32_to_v4f32:
 ; NO-SIMD128-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
   %res = bitcast <4 x float> %v to <4 x float>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: v4f32_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
   %res = bitcast <4 x float> %v to <2 x double>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: v2f64_to_v16i8:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <16 x i8>
   ret <16 x i8> %res
 }
 
 ; CHECK-LABEL: v2f64_to_v8i16:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <8 x i16>
   ret <8 x i16> %res
 }
 
 ; CHECK-LABEL: v2f64_to_v4i32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: v2f64_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: v2f64_to_v4f32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <4 x float>
   ret <4 x float> %res
 }
 
 ; CHECK-LABEL: v2f64_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <2 x double>
   ret <2 x double> %res
 }

llvm/test/CodeGen/WebAssembly/simd-build-pair.ll

 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=simd128 | FileCheck %s --check-prefixes CHECK
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; Test that BUILD_PAIR dag nodes are correctly lowered.
 ; This code produces a selection DAG like the following:
 
 ;    t0: ch = EntryToken
 ;  t3: v4i32,ch = load<(load 16 from `<4 x i32>* undef`)> t0, undef:i32, undef:i32
 ;        t30: i32 = extract_vector_elt t3, Constant:i32<2>
 ;        t28: i32 = extract_vector_elt t3, Constant:i32<3>
 ;      t24: i64 = build_pair t30, t28
 ;    t8: ch = store<(store 8 into `i64* undef`, align 1)> t3:1, t24, undef:i32, undef:i32
 ;  t9: ch = WebAssemblyISD::RETURN t8
 
-; CHECK:      i32x4.extract_lane
-; CHECK-NEXT: i64.extend_i32_u
-; CHECK-NEXT: i32x4.extract_lane
-; CHECK-NEXT: i64.extend_i32_u
-; CHECK-NEXT: i64.const {{.*}} 32
-; CHECK-NEXT: i64.shl
-; CHECK-NEXT: i64.or
+; CHECK:      i64x2.extract_lane
 ; CHECK-NEXT: i64.store
 define void @build_pair_i32s() {
 entry:
   %0 = load <4 x i32>, <4 x i32>* undef, align 16
   %shuffle.i184 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
   %bc357 = bitcast <4 x i32> %shuffle.i184 to <2 x i64>
   %1 = extractelement <2 x i64> %bc357, i32 0
   store i64 %1, i64* undef, align 1
   ret void
 }

llvm/test/CodeGen/WebAssembly/simd-comparisons.ll

 define <4 x i32> @compare_sext_uno_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
   %cmp = fcmp nnan uno <4 x float> %x, %y
   %res = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %res
 }
 
 ; CHECK-LABEL: compare_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oeq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_oeq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp oeq <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_oeq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oeq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_oeq_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan oeq <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oeq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_oeq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp oeq <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_oeq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oeq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_oeq_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan oeq <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ogt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ogt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ogt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ogt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ogt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ogt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ogt_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ogt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ogt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ogt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ogt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ogt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ogt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ogt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ogt_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ogt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_oge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_oge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp oge <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_oge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_oge_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan oge <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_oge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_oge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp oge <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_oge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_oge_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan oge <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_olt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_olt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_olt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp olt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_olt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_olt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_olt_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan olt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_olt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_olt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_olt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp olt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_olt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_olt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_olt_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan olt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ole_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ole_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ole_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ole <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ole_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ole_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ole_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ole <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ole_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ole_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ole_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ole <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ole_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ole_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ole_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ole <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_one_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_one_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_one_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp one <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_one_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_one_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_one_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan one <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_one_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_one_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_one_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp one <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_one_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_one_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_one_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan one <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i1> @compare_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ord <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ord_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ord_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i1> @compare_ord_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ord <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ord_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ord <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ord_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ord_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return   $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ord_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ord <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ueq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ueq <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ueq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ueq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ueq_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ueq <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ueq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ueq <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ueq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ueq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ueq_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ueq <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ugt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ugt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ugt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ugt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ugt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ugt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ugt_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ugt <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ugt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ugt_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ugt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ugt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ugt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ugt_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ugt <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_uge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_uge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp uge <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_uge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_uge_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan uge <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uge_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp uge <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_uge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uge_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan uge <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ult_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ult_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ult_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ult <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ult_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ult_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ult_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ult <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ult_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ult_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ult <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ult_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ult_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ult_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ult <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_ule_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ule_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ule_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp ule <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_ule_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ule_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_ule_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan ule <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ule_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ule_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp ule <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_ule_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ule_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_ule_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan ule <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_une_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_une_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_une_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp une <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_une_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_une_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_une_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan une <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_une_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_une_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_une_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp une <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_une_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_une_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_une_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan une <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp uno <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_uno_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uno_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i1> @compare_uno_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %res = fcmp nnan uno <2 x double> %x, %y
   ret <2 x i1> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uno_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp uno <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: compare_sext_uno_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uno_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @compare_sext_uno_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
   %cmp = fcmp nnan uno <2 x double> %x, %y
   %res = sext <2 x i1> %cmp to <2 x i64>
   ret <2 x i64> %res
 }

llvm/test/CodeGen/WebAssembly/simd-extended-extract.ll

 ; handle mismatched types like this, so we insert a bitcast before the
 ; extract. This was previously an ISel failure. This test case is
 ; reduced from a private user bug report, and the vector extracts are
 ; optimized out via subsequent DAG combines.
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-define void @foo(<4 x i8>* %p) {
 ; CHECK-LABEL: foo:
 ; CHECK:         .functype foo (i32) -> ()
-; CHECK-NEXT:    i32.load8_u 0
-; CHECK-NEXT:    i32x4.splat
-; CHECK-NEXT:    local.tee
-; CHECK-NEXT:    i8x16.extract_lane_s 0
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.splat
-; CHECK-NEXT:    i32.load8_u 1
-; CHECK-NEXT:    i32x4.replace_lane 1
-; CHECK-NEXT:    local.tee
-; CHECK-NEXT:    i8x16.extract_lane_s 4
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.replace_lane 1
-; CHECK-NEXT:    i32.const 2
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i32.load8_u 0
-; CHECK-NEXT:    i32x4.replace_lane 2
-; CHECK-NEXT:    local.tee
-; CHECK-NEXT:    i8x16.extract_lane_s 8
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.replace_lane 2
-; CHECK-NEXT:    i32.const 3
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i32.load8_u 0
-; CHECK-NEXT:    i32x4.replace_lane 3
-; CHECK-NEXT:    i8x16.extract_lane_s 12
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.replace_lane 3
-; CHECK-NEXT:    v128.store 0
-; CHECK-NEXT:    return
+; Implementation omitted...
+; CHECK:         return
+define void @foo(<4 x i8>* %p) {
   %1 = load <4 x i8>, <4 x i8>* %p
   %2 = sitofp <4 x i8> %1 to <4 x double>
   %3 = fmul <4 x double> zeroinitializer, %2
   %4 = fadd <4 x double> %3, zeroinitializer
   %5 = fptrunc <4 x double> %4 to <4 x float>
   store <4 x float> %5, <4 x float>* undef
   ret void
 }

llvm/test/CodeGen/WebAssembly/simd-offset.ll

define void @store_v4i32_to_global_address(<4 x i32> %v) {
   ret void
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: load_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64(<2 x i64>* %p) {
   %v = load <2 x i64>, <2 x i64>* %p
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64(i64* %p) {
   %e = load i64, i64* %p
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64(<2 x i32>* %p) {
   %v = load <2 x i32>, <2 x i32>* %p
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64(<2 x i32>* %p) {
   %v = load <2 x i32>, <2 x i32>* %p
   %v2 = zext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_ext_v2i64:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: load32x2
 ; SIMD128-NEXT: .functype load_ext_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i32> @load_ext_v2i64(<2 x i32>* %p) {
   %v = load <2 x i32>, <2 x i32>* %p
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_folded_offset(<2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_with_folded_offset(i64* %p) {
   %q = ptrtoint i64* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to i64*
   %e = load i64, i64* %s
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64_with_folded_offset(<2 x i32>* %p) {
   %q = ptrtoint <2 x i32>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_with_folded_offset(<2 x i32>* %p) {
   %q = ptrtoint <2 x i32>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
define <2 x i32> @load_ext_v2i64_with_folded_offset(<2 x i32>* %p) {
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_folded_gep_offset(<2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_with_folded_gep_offset(i64* %p) {
   %s = getelementptr inbounds i64, i64* %p, i32 1
   %e = load i64, i64* %s
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64_with_folded_gep_offset(<2 x i32>* %p) {
   %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 1
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_with_folded_gep_offset(<2 x i32>* %p) {
   %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 1
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = zext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_ext_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: load32x2
 ; SIMD128-NEXT: .functype load_ext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i32> @load_ext_v2i64_with_folded_gep_offset(<2 x i32>* %p) {
   %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 1
   %v = load <2 x i32>, <2 x i32>* %s
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_gep_negative_offset(<2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_with_unfolded_gep_negative_offset(i64* %p) {
   %s = getelementptr inbounds i64, i64* %p, i32 -1
   %e = load i64, i64* %s
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64_with_unfolded_gep_negative_offset(<2 x i32>* %p) {
   %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 -1
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_with_unfolded_gep_negative_offset(<2 x i32>* %p) {
   %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 -1
   %v = load <2 x i32>, <2 x i32>* %s

 define <2 x i32> @load_ext_v2i64_with_unfolded_gep_negative_offset(<2 x i32>* %p) {
   %s = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i32 -1
   %v = load <2 x i32>, <2 x i32>* %s
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_offset(<2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_with_unfolded_offset(i64* %p) {
   %q = ptrtoint i64* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to i64*
   %e = load i64, i64* %s
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64_with_unfolded_offset(<2 x i32>* %p) {
   %q = ptrtoint <2 x i32>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_with_unfolded_offset(<2 x i32>* %p) {
   %q = ptrtoint <2 x i32>* %p to i32
   %r = add nsw i32 %q, 16
define <2 x i32> @load_ext_v2i64_with_unfolded_offset(<2 x i32>* %p) {
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_with_unfolded_gep_offset(<2 x i64>* %p) {
   %s = getelementptr <2 x i64>, <2 x i64>* %p, i32 1
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_with_unfolded_gep_offset(i64* %p) {
   %s = getelementptr i64, i64* %p, i32 1
   %e = load i64, i64* %s
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64_with_unfolded_gep_offset(<2 x i32>* %p) {
   %s = getelementptr <2 x i32>, <2 x i32>* %p, i32 1
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_with_unfolded_gep_offset(<2 x i32>* %p) {
   %s = getelementptr <2 x i32>, <2 x i32>* %p, i32 1
   %v = load <2 x i32>, <2 x i32>* %s

 define <2 x i32> @load_ext_v2i64_with_unfolded_gep_offset(<2 x i32>* %p) {
   %s = getelementptr <2 x i32>, <2 x i32>* %p, i32 1
   %v = load <2 x i32>, <2 x i32>* %s
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x i64>*
   %v = load <2 x i64>, <2 x i64>* %s
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to i64*
   %e = load i64, i64* %s
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_sext_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   %v2 = zext <2 x i32> %v to <2 x i64>

 define <2 x i32> @load_ext_v2i64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x i32>*
   %v = load <2 x i32>, <2 x i32>* %s
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: load_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2i64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2i64 = global <2 x i64> <i64 42, i64 42>
 define <2 x i64> @load_v2i64_from_global_address() {
   %v = load <2 x i64>, <2 x i64>* @gv_v2i64
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: load_splat_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, gv_i64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_i64 = global i64 42
 define <2 x i64> @load_splat_v2i64_from_global_address() {
   %e = load i64, i64* @gv_i64
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
   %v2 = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_sext_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2i32 = global <2 x i32> <i32 42, i32 42>
 define <2 x i64> @load_sext_v2i64_from_global_address() {
   %v = load <2 x i32>, <2 x i32>* @gv_v2i32
   %v2 = sext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_zext_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_zext_v2i64_from_global_address() {
   %v = load <2 x i32>, <2 x i32>* @gv_v2i32
   %v2 = zext <2 x i32> %v to <2 x i64>
   ret <2 x i64> %v2
 }
 
 ; CHECK-LABEL: load_ext_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
 ; SIMD128-VM-NOT: load32x2
 ; SIMD128-NEXT: .functype load_ext_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i32> @load_ext_v2i64_from_global_address() {
   %v = load <2 x i32>, <2 x i32>* @gv_v2i32
   ret <2 x i32> %v
 }
 
 ; CHECK-LABEL: store_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2i64(<2 x i64> %v, <2 x i64>* %p) {
   store <2 x i64> %v , <2 x i64>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2i64_with_folded_offset(<2 x i64> %v, <2 x i64>* %p) {
   %q = ptrtoint <2 x i64>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x i64>*
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2i64_with_folded_gep_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2i64_with_unfolded_gep_negative_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2i64_with_unfolded_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr inbounds <2 x i64>, <2 x i64>* %p, i32 -1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2i64_with_unfolded_gep_offset(<2 x i64> %v, <2 x i64>* %p) {
   %s = getelementptr <2 x i64>, <2 x i64>* %p, i32 1
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v2i64_to_numeric_address(<2 x i64> %v) {
   %s = inttoptr i32 32 to <2 x i64>*
   store <2 x i64> %v , <2 x i64>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2i64_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v2i64($pop[[R]]), $0{{$}}
 define void @store_v2i64_to_global_address(<2 x i64> %v) {
   store <2 x i64> %v , <2 x i64>* @gv_v2i64
   ret void
 }
 
define void @store_v4f32_to_global_address(<4 x float> %v) {
   ret void
 }
 
 ; ==============================================================================
 ; 2 x double
 ; ==============================================================================
 ; CHECK-LABEL: load_v2f64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64(<2 x double>* %p) {
   %v = load <2 x double>, <2 x double>* %p
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64(double* %p) {
   %e = load double, double* %p
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_folded_offset(<2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64_with_folded_offset(double* %p) {
   %q = ptrtoint double* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to double*
   %e = load double, double* %s
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_folded_gep_offset(<2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64_with_folded_gep_offset(double* %p) {
   %s = getelementptr inbounds double, double* %p, i32 1
   %e = load double, double* %s
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_gep_negative_offset(<2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64_with_unfolded_gep_negative_offset(double* %p) {
   %s = getelementptr inbounds double, double* %p, i32 -1
   %e = load double, double* %s
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_offset(<2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64_with_unfolded_offset(double* %p) {
   %q = ptrtoint double* %p to i32
   %r = add nsw i32 %q, 16
   %s = inttoptr i32 %r to double*
   %e = load double, double* %s
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_with_unfolded_gep_offset(<2 x double>* %p) {
   %s = getelementptr <2 x double>, <2 x double>* %p, i32 1
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($pop[[L1]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64_with_unfolded_gep_offset(double* %p) {
   %s = getelementptr double, double* %p, i32 1
   %e = load double, double* %s
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_v2f64_from_numeric_address() {
   %s = inttoptr i32 32 to <2 x double>*
   %v = load <2 x double>, <2 x double>* %s
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @load_splat_v2f64_from_numeric_address() {
   %s = inttoptr i32 32 to double*
   %e = load double, double* %s
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: load_v2f64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2f64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_v2f64 = global <2 x double> <double 42., double 42.>
 define <2 x double> @load_v2f64_from_global_address() {
   %v = load <2 x double>, <2 x double>* @gv_v2f64
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: load_splat_v2f64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, gv_f64($pop[[L0]]){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 @gv_f64 = global double 42.
 define <2 x double> @load_splat_v2f64_from_global_address() {
   %e = load double, double* @gv_f64
   %v1 = insertelement <2 x double> undef, double %e, i32 0
   %v2 = shufflevector <2 x double> %v1, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %v2
 }
 
 ; CHECK-LABEL: store_v2f64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2f64(<2 x double> %v, <2 x double>* %p) {
   store <2 x double> %v , <2 x double>* %p
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2f64_with_folded_offset(<2 x double> %v, <2 x double>* %p) {
   %q = ptrtoint <2 x double>* %p to i32
   %r = add nuw i32 %q, 16
   %s = inttoptr i32 %r to <2 x double>*
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2f64_with_folded_gep_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2f64_with_unfolded_gep_negative_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2f64_with_unfolded_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr inbounds <2 x double>, <2 x double>* %p, i32 -1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[R]]), $0{{$}}
 define void @store_v2f64_with_unfolded_gep_offset(<2 x double> %v, <2 x double>* %p) {
   %s = getelementptr <2 x double>, <2 x double>* %p, i32 1
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
 define void @store_v2f64_to_numeric_address(<2 x double> %v) {
   %s = inttoptr i32 32 to <2 x double>*
   store <2 x double> %v , <2 x double>* %s
   ret void
 }
 
 ; CHECK-LABEL: store_v2f64_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v2f64($pop[[R]]), $0{{$}}
 define void @store_v2f64_to_global_address(<2 x double> %v) {
   store <2 x double> %v , <2 x double>* @gv_v2f64
   ret void
 }

llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll

 ;     t57: ch = store<(store 2 into `<4 x i16>* undef` + 6, align 1), trunc to i16> t32:1, t48, undef:i32, undef:i32
 ;   t58: ch = TokenFactor t52, t53, t55, t57
 ; t24: ch = WebAssemblyISD::RETURN t58
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: foo:
-; CHECK: i32x4.splat
+; CHECK: i64x2.splat
 define void @foo() {
 entry:
   %a = load <2 x i16>, <2 x i16>* undef, align 1
   %b = shufflevector <2 x i16> %a, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %0 = bitcast <8 x i16> %b to <16 x i8>
   %shuffle.i214 = shufflevector <16 x i8> %0, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
   %1 = bitcast <16 x i8> %shuffle.i214 to <8 x i16>
   %add82 = add <8 x i16> %1, zeroinitializer
   %2 = select <8 x i1> undef, <8 x i16> undef, <8 x i16> %add82
   %3 = bitcast <8 x i16> %2 to <16 x i8>
   %shuffle.i204 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
   %4 = bitcast <16 x i8> %shuffle.i204 to <8 x i16>
   %dst2.0.vec.extract = shufflevector <8 x i16> %4, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   store <4 x i16> %dst2.0.vec.extract, <4 x i16>* undef, align 1
   ret void
 }

llvm/test/CodeGen/WebAssembly/simd.ll

 define i32 @extract_undef_v16i8_s(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 undef
   %a = sext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-VM-NOT: i8x16.extract_lane_u
 ; SIMD128-NEXT: .functype extract_v16i8_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 13{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v16i8_u(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 13
   %a = zext i8 %elem to i32
   ret i32 %a
 }

 define i32 @extract_var_v16i8_u(<16 x i8> %v, i32 %i) {
   %elem = extractelement <16 x i8> %v, i32 %i
   %a = zext i8 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_undef_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-VM-NOT: i8x16.extract_lane_u
 ; SIMD128-NEXT: .functype extract_undef_v16i8_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v16i8_u(<16 x i8> %v) {
   %elem = extractelement <16 x i8> %v, i8 undef
   %a = zext i8 %elem to i32
   ret i32 %a
 }
define <16 x i8> @build_v16i8(i8 %x0, i8 %x1, i8 %x2, i8 %x3,
   ret <16 x i8> %res
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: const_v8i16:
 ; NO-SIMD128-NOT: i16x8
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v8i16 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 256, 770, 1284, 1798, 2312, 2826, 3340, 3854{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @const_v8i16() {
   ret <8 x i16> <i16 256, i16 770, i16 1284, i16 1798,
                  i16 2312, i16 2826, i16 3340, i16 3854>
 }
 

 define i32 @extract_undef_v8i16_s(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 undef
   %a = sext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-VM-NOT: i16x8.extract_lane_u
 ; SIMD128-NEXT: .functype extract_v8i16_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 5{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_v8i16_u(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 5
   %a = zext i16 %elem to i32
   ret i32 %a
 }

 define i32 @extract_var_v8i16_u(<8 x i16> %v, i32 %i) {
   %elem = extractelement <8 x i16> %v, i32 %i
   %a = zext i16 %elem to i32
   ret i32 %a
 }
 
 ; CHECK-LABEL: extract_undef_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-VM-NOT: i16x8.extract_lane_u
 ; SIMD128-NEXT: .functype extract_undef_v8i16_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i32 @extract_undef_v8i16_u(<8 x i16> %v) {
   %elem = extractelement <8 x i16> %v, i16 undef
   %a = zext i16 %elem to i32
   ret i32 %a
 }
define <8 x i16> @build_v8i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3,
   ret <8 x i16> %res
 }
 
 ; ==============================================================================
 ; 4 x i32
 ; ==============================================================================
 ; CHECK-LABEL: const_v4i32:
 ; NO-SIMD128-NOT: i32x4
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4i32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 50462976, 117835012, 185207048, 252579084{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @const_v4i32() {
   ret <4 x i32> <i32 50462976, i32 117835012, i32 185207048, i32 252579084>
 }
 
 ; CHECK-LABEL: splat_v4i32:
define <4 x i32> @build_v4i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
   ret <4 x i32> %res
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2i64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 506097522914230528, 1084818905618843912{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @const_v2i64() {
   ret <2 x i64> <i64 506097522914230528, i64 1084818905618843912>
 }
 
 ; CHECK-LABEL: splat_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype splat_v2i64 (i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @splat_v2i64(i64 %x) {
   %t1 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
   %res = insertelement <2 x i64> %t1, i64 %x, i32 1
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: const_splat_v2i64:
 ; SIMD128: i64x2.splat
 define <2 x i64> @const_splat_v2i64() {
   ret <2 x i64> <i64 42, i64 42>
 }
 
 ; CHECK-LABEL: extract_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype extract_v2i64 (v128) -> (i64){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i64 @extract_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 1
   ret i64 %elem
 }
 

 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i64 @extract_var_v2i64(<2 x i64> %v, i32 %i) {
   %elem = extractelement <2 x i64> %v, i32 %i
   ret i64 %elem
 }
 
 ; CHECK-LABEL: extract_zero_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype extract_zero_v2i64 (v128) -> (i64){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define i64 @extract_zero_v2i64(<2 x i64> %v) {
   %elem = extractelement <2 x i64> %v, i64 0
   ret i64 %elem
 }
 
 ; CHECK-LABEL: replace_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype replace_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 0
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: replace_var_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype replace_var_v2i64 (v128, i32, i64) -> (v128){{$}}
 ; SIMD128-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: local.tee $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: i64.store 0($pop[[L2]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @replace_var_v2i64(<2 x i64> %v, i32 %i, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 %i
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: replace_zero_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype replace_zero_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @replace_zero_v2i64(<2 x i64> %v, i64 %x) {
   %res = insertelement <2 x i64> %v, i64 %x, i32 0
   ret <2 x i64> %res
 }
 

 define <2 x i64> @shuffle_undef_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %res = shufflevector <2 x i64> %x, <2 x i64> %y,
     <2 x i32> <i32 1, i32 undef>
   ret <2 x i64> %res
 }
 
 ; CHECK-LABEL: build_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype build_v2i64 (i64, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @build_v2i64(i64 %x0, i64 %x1) {
   %t0 = insertelement <2 x i64> undef, i64 %x0, i32 0
   %res = insertelement <2 x i64> %t0, i64 %x1, i32 1
   ret <2 x i64> %res
 }
 
 ; ==============================================================================
 ; 4 x f32
 ; ==============================================================================
 ; CHECK-LABEL: const_v4f32:
 ; NO-SIMD128-NOT: f32x4
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @const_v4f32() {
   ret <4 x float> <float 0x3860402000000000, float 0x38e0c0a080000000,
                    float 0x3961412100000000, float 0x39e1c1a180000000>
 }
define <4 x float> @build_v4f32(float %x0, float %x1, float %x2, float %x3) {
   ret <4 x float> %res
 }
 
 ; ==============================================================================
 ; 2 x f64
 ; ==============================================================================
 ; CHECK-LABEL: const_v2f64:
 ; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @const_v2f64() {
   ret <2 x double> <double 0x0706050403020100, double 0x0F0E0D0C0B0A0908>
 }
 
 ; CHECK-LABEL: splat_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype splat_v2f64 (f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @splat_v2f64(double %x) {
   %t1 = insertelement <2 x double> zeroinitializer, double %x, i3 0
   %res = insertelement <2 x double> %t1, double %x, i32 1
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: const_splat_v2f64:
 ; SIMD128: f64x2.splat
 define <2 x double> @const_splat_v2f64() {
   ret <2 x double> <double 42., double 42.>
 }
 
 ; CHECK-LABEL: extract_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype extract_v2f64 (v128) -> (f64){{$}}
 ; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define double @extract_v2f64(<2 x double> %v) {
   %elem = extractelement <2 x double> %v, i32 1
   ret double %elem
 }
 

 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define double @extract_var_v2f64(<2 x double> %v, i32 %i) {
   %elem = extractelement <2 x double> %v, i32 %i
   ret double %elem
 }
 
 ; CHECK-LABEL: extract_zero_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype extract_zero_v2f64 (v128) -> (f64){{$}}
 ; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define double @extract_zero_v2f64(<2 x double> %v) {
   %elem = extractelement <2 x double> %v, i32 0
   ret double %elem
 }
 
 ; CHECK-LABEL: replace_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype replace_v2f64 (v128, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @replace_v2f64(<2 x double> %v, double %x) {
   %res = insertelement <2 x double> %v, double %x, i32 0
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: replace_var_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype replace_var_v2f64 (v128, i32, f64) -> (v128){{$}}
 ; SIMD128-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.sub $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
 ; SIMD128-NEXT: local.tee $push[[L3:[0-9]+]]=, $3=, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: v128.store 0($pop[[L3]]), $0{{$}}
 ; SIMD128-NEXT: i32.const $push[[L2:[0-9]+]]=, 1{{$}}
 ; SIMD128-NEXT: i32.and $push[[L5:[0-9]+]]=, $1, $pop[[L2]]{{$}}
 ; SIMD128-NEXT: i32.const $push[[L6:[0-9]+]]=, 3{{$}}
 ; SIMD128-NEXT: i32.shl $push[[L7:[0-9]+]]=, $pop[[L5]], $pop[[L6]]{{$}}
 ; SIMD128-NEXT: i32.or $push[[L2:[0-9]+]]=, $3, $pop[[L7]]{{$}}
 ; SIMD128-NEXT: f64.store 0($pop[[L2]]), $2{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($3){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @replace_var_v2f64(<2 x double> %v, i32 %i, double %x) {
   %res = insertelement <2 x double> %v, double %x, i32 %i
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: replace_zero_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype replace_zero_v2f64 (v128, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @replace_zero_v2f64(<2 x double> %v, double %x) {
   %res = insertelement <2 x double> %v, double %x, i32 0
   ret <2 x double> %res
 }
 

 define <2 x double> @shuffle_undef_v2f64(<2 x double> %x, <2 x double> %y) {
   %res = shufflevector <2 x double> %x, <2 x double> %y,
     <2 x i32> <i32 1, i32 undef>
   ret <2 x double> %res
 }
 
 ; CHECK-LABEL: build_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype build_v2f64 (f64, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @build_v2f64(double %x0, double %x1) {
   %t0 = insertelement <2 x double> undef, double %x0, i32 0
   %res = insertelement <2 x double> %t0, double %x1, i32 1
   ret <2 x double> %res
 }