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Differential D73650

[GlobalISel][IRTranslator] Follow convention and put constant offset of getelementptr arithmetic on RHS.
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Authored by aemerson on Jan 29 2020, 11:20 AM.

Details

Reviewers
paquette
arsenm
Commits
rG9fee95dc2800: [GlobalISel][IRTranslator] Follow convention and put constant offset of…
rG0da937bb5c2b: [GlobalISel][IRTranslator] Follow convention and put constant offset of…
Summary

We were needlessly putting known constant values on the LHS of a G_MUL, which is suboptimal.

Diff Detail

Event Timeline

aemerson created this revision.Jan 29 2020, 11:20 AM
Herald added subscribers: kerbowa, Petar.Avramovic, volkan and 6 others. · View Herald TranscriptJan 29 2020, 11:21 AM
arsenm accepted this revision.Jan 29 2020, 11:22 AM
This revision is now accepted and ready to land.Jan 29 2020, 11:22 AM
Closed by commit rG0da937bb5c2b: [GlobalISel][IRTranslator] Follow convention and put constant offset of… (authored by aemerson). · Explain WhyJan 29 2020, 11:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
2 lines
test/
CodeGen/
AArch64/
GlobalISel/
24 lines
20 lines
36 lines
AMDGPU/
GlobalISel/
12 lines
2 lines
168 lines
384 lines
20 lines
20 lines
20 lines
252 lines
X86/
GlobalISel/
58 lines
14 lines

Diff 241243

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Show First 20 Lines • Show All 1,099 Lines • ▼ Show 20 Lines if (StructType *StTy = GTI.getStructTypeOrNull()) {
// N = N + Idx * ElementSize; // N = N + Idx * ElementSize;
// Avoid doing it for ElementSize of 1. // Avoid doing it for ElementSize of 1.
Register GepOffsetReg; Register GepOffsetReg;
if (ElementSize != 1) { if (ElementSize != 1) {
auto ElementSizeMIB = MIRBuilder.buildConstant( auto ElementSizeMIB = MIRBuilder.buildConstant(
getLLTForType(*OffsetIRTy, *DL), ElementSize); getLLTForType(*OffsetIRTy, *DL), ElementSize);
GepOffsetReg = GepOffsetReg =
MIRBuilder.buildMul(OffsetTy, ElementSizeMIB, IdxReg).getReg(0); MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0);
} else } else
GepOffsetReg = IdxReg; GepOffsetReg = IdxReg;
BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0); BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
} }
} }
if (Offset != 0) { if (Offset != 0) {
▲ Show 20 Lines • Show All 1,321 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0 ; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3 ; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--" target triple = "aarch64--"
define i32 @cse_gep([4 x i32]* %ptr, i32 %idx) { define i32 @cse_gep([4 x i32]* %ptr, i32 %idx) {
; O0-LABEL: name: cse_gep ; O0-LABEL: name: cse_gep
; O0: bb.1 (%ir-block.0): ; O0: bb.1 (%ir-block.0):
; O0: liveins: $w1, $x0 ; O0: liveins: $w1, $x0
; O0: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; O0: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; O0: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; O0: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; O0: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32) ; O0: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
; O0: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; O0: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; O0: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]] ; O0: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
; O0: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64) ; O0: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
; O0: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0) ; O0: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O0: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.gep1) ; O0: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.gep1)
; O0: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]] ; O0: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
; O0: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64) ; O0: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL1]](s64)
; O0: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; O0: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; O0: [[GEP2:%[0-9]+]]:_(p0) = G_PTR_ADD [[GEP1]], [[C1]](s64) ; O0: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
; O0: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.gep2) ; O0: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load 4 from %ir.gep2)
; O0: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[LOAD1]] ; O0: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[LOAD1]]
; O0: $w0 = COPY [[ADD]](s32) ; O0: $w0 = COPY [[ADD]](s32)
; O0: RET_ReallyLR implicit $w0 ; O0: RET_ReallyLR implicit $w0
; O3-LABEL: name: cse_gep ; O3-LABEL: name: cse_gep
; O3: bb.1 (%ir-block.0): ; O3: bb.1 (%ir-block.0):
; O3: liveins: $w1, $x0 ; O3: liveins: $w1, $x0
; O3: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; O3: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; O3: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; O3: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; O3: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32) ; O3: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
; O3: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; O3: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; O3: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]] ; O3: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
; O3: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64) ; O3: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
; O3: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0) ; O3: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; O3: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.gep1) ; O3: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.gep1)
; O3: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; O3: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; O3: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[GEP]], [[C1]](s64) ; O3: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
; O3: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.gep2) ; O3: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load 4 from %ir.gep2)
; O3: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[LOAD1]] ; O3: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[LOAD1]]
; O3: $w0 = COPY [[ADD]](s32) ; O3: $w0 = COPY [[ADD]](s32)
; O3: RET_ReallyLR implicit $w0 ; O3: RET_ReallyLR implicit $w0
%sidx = sext i32 %idx to i64 %sidx = sext i32 %idx to i64
%gep1 = getelementptr inbounds [4 x i32], [4 x i32]* %ptr, i64 %sidx, i64 0 %gep1 = getelementptr inbounds [4 x i32], [4 x i32]* %ptr, i64 %sidx, i64 0
%v1 = load i32, i32* %gep1 %v1 = load i32, i32* %gep1
%gep2 = getelementptr inbounds [4 x i32], [4 x i32]* %ptr, i64 %sidx, i64 1 %gep2 = getelementptr inbounds [4 x i32], [4 x i32]* %ptr, i64 %sidx, i64 1
%v2 = load i32, i32* %gep2 %v2 = load i32, i32* %gep2
%res = add i32 %v2, %v2 %res = add i32 %v2, %v2
ret i32 %res ret i32 %res
} }

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

Show First 20 Lines • Show All 176 Lines • ▼ Show 20 Linesdefine i32 @jt_test(i32 %x) {
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.4 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.4
; CHECK: bb.5.entry: ; CHECK: bb.5.entry:
; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
; CHECK: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 ; CHECK: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
; CHECK: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64) ; CHECK: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64)
; CHECK: bb.2.sw.bb: ; CHECK: bb.2.sw.bb:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: %11:_(s32) = nsw G_ADD [[COPY]], [[C2]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C2]]
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.3.sw.bb1: ; CHECK: bb.3.sw.bb1:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: %9:_(s32) = nsw G_MUL [[COPY]], [[C1]] ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C1]]
; CHECK: bb.4.return: ; CHECK: bb.4.return:
; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.3, %11(s32), %bb.2, [[C3]](s32), %bb.1, [[C3]](s32), %bb.5 ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C3]](s32), %bb.1, [[C3]](s32), %bb.5
; CHECK: $w0 = COPY [[PHI]](s32) ; CHECK: $w0 = COPY [[PHI]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
i32 75, label %sw.bb i32 75, label %sw.bb
i32 34, label %sw.bb i32 34, label %sw.bb
i32 56, label %sw.bb i32 56, label %sw.bb
i32 35, label %sw.bb i32 35, label %sw.bb
▲ Show 20 Lines • Show All 575 Lines • ▼ Show 20 Linesdefine void @jt_multiple_jump_tables(%1* %arg, i32 %arg1, i32* %arg2) {
; CHECK: successors: %bb.56(0x80000000) ; CHECK: successors: %bb.56(0x80000000)
; CHECK: G_BR %bb.56 ; CHECK: G_BR %bb.56
; CHECK: bb.55.bb56: ; CHECK: bb.55.bb56:
; CHECK: successors: %bb.56(0x80000000) ; CHECK: successors: %bb.56(0x80000000)
; CHECK: bb.56.bb57: ; CHECK: bb.56.bb57:
; CHECK: successors: %bb.59(0x80000000) ; CHECK: successors: %bb.59(0x80000000)
; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C55]](s64), %bb.1, [[C56]](s64), %bb.2, [[C57]](s64), %bb.3, [[C58]](s64), %bb.4, [[C59]](s64), %bb.5, [[C60]](s64), %bb.6, [[C61]](s64), %bb.7, [[C62]](s64), %bb.8, [[C63]](s64), %bb.9, [[C64]](s64), %bb.10, [[C65]](s64), %bb.11, [[C66]](s64), %bb.12, [[C67]](s64), %bb.13, [[C68]](s64), %bb.14, [[C69]](s64), %bb.15, [[C70]](s64), %bb.16, [[C71]](s64), %bb.17, [[C72]](s64), %bb.18, [[C73]](s64), %bb.19, [[C74]](s64), %bb.20, [[C75]](s64), %bb.21, [[C76]](s64), %bb.22, [[C77]](s64), %bb.23, [[C78]](s64), %bb.24, [[C79]](s64), %bb.25, [[C80]](s64), %bb.26, [[C81]](s64), %bb.27, [[C82]](s64), %bb.28, [[C83]](s64), %bb.29, [[C84]](s64), %bb.30, [[C85]](s64), %bb.31, [[C86]](s64), %bb.32, [[C87]](s64), %bb.33, [[C88]](s64), %bb.34, [[C89]](s64), %bb.35, [[C90]](s64), %bb.36, [[C91]](s64), %bb.37, [[C92]](s64), %bb.38, [[C93]](s64), %bb.39, [[C94]](s64), %bb.40, [[C95]](s64), %bb.41, [[C96]](s64), %bb.42, [[C97]](s64), %bb.43, [[C98]](s64), %bb.44, [[C99]](s64), %bb.45, [[C100]](s64), %bb.46, [[C101]](s64), %bb.47, [[C102]](s64), %bb.48, [[C103]](s64), %bb.49, [[C104]](s64), %bb.50, [[C105]](s64), %bb.51, [[C106]](s64), %bb.52, [[C107]](s64), %bb.53, [[C108]](s64), %bb.54, [[C109]](s64), %bb.55 ; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C55]](s64), %bb.1, [[C56]](s64), %bb.2, [[C57]](s64), %bb.3, [[C58]](s64), %bb.4, [[C59]](s64), %bb.5, [[C60]](s64), %bb.6, [[C61]](s64), %bb.7, [[C62]](s64), %bb.8, [[C63]](s64), %bb.9, [[C64]](s64), %bb.10, [[C65]](s64), %bb.11, [[C66]](s64), %bb.12, [[C67]](s64), %bb.13, [[C68]](s64), %bb.14, [[C69]](s64), %bb.15, [[C70]](s64), %bb.16, [[C71]](s64), %bb.17, [[C72]](s64), %bb.18, [[C73]](s64), %bb.19, [[C74]](s64), %bb.20, [[C75]](s64), %bb.21, [[C76]](s64), %bb.22, [[C77]](s64), %bb.23, [[C78]](s64), %bb.24, [[C79]](s64), %bb.25, [[C80]](s64), %bb.26, [[C81]](s64), %bb.27, [[C82]](s64), %bb.28, [[C83]](s64), %bb.29, [[C84]](s64), %bb.30, [[C85]](s64), %bb.31, [[C86]](s64), %bb.32, [[C87]](s64), %bb.33, [[C88]](s64), %bb.34, [[C89]](s64), %bb.35, [[C90]](s64), %bb.36, [[C91]](s64), %bb.37, [[C92]](s64), %bb.38, [[C93]](s64), %bb.39, [[C94]](s64), %bb.40, [[C95]](s64), %bb.41, [[C96]](s64), %bb.42, [[C97]](s64), %bb.43, [[C98]](s64), %bb.44, [[C99]](s64), %bb.45, [[C100]](s64), %bb.46, [[C101]](s64), %bb.47, [[C102]](s64), %bb.48, [[C103]](s64), %bb.49, [[C104]](s64), %bb.50, [[C105]](s64), %bb.51, [[C106]](s64), %bb.52, [[C107]](s64), %bb.53, [[C108]](s64), %bb.54, [[C109]](s64), %bb.55
; CHECK: [[C110:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK: [[C110:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C110]], [[PHI]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[PHI]], [[C110]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[MUL]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[MUL]](s64)
; CHECK: [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK: [[C111:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[GEP]], [[C111]](s64) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C111]](s64)
; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[GEP1]](p0) :: (load 8 from %ir.tmp59) ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[PTR_ADD1]](p0) :: (load 8 from %ir.tmp59)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0) ; CHECK: $x0 = COPY [[COPY]](p0)
; CHECK: $x1 = COPY [[LOAD]](p0) ; CHECK: $x1 = COPY [[LOAD]](p0)
; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0 ; CHECK: BL @wibble, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit-def $x0
; CHECK: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: G_BR %bb.59 ; CHECK: G_BR %bb.59
; CHECK: bb.57.bb62: ; CHECK: bb.57.bb62:
▲ Show 20 Lines • Show All 518 Lines • ▼ Show 20 Linesdefine i32 @range_test(i32 %x) {
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB]](s32), [[C5]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB]](s32), [[C5]]
; CHECK: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 true ; CHECK: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[C6]] ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[C6]]
; CHECK: G_BRCOND [[XOR]](s1), %bb.4 ; CHECK: G_BRCOND [[XOR]](s1), %bb.4
; CHECK: G_BR %bb.2 ; CHECK: G_BR %bb.2
; CHECK: bb.2.sw.bb: ; CHECK: bb.2.sw.bb:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: %12:_(s32) = nsw G_ADD [[COPY]], [[C3]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C3]]
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.3.sw.bb1: ; CHECK: bb.3.sw.bb1:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: %10:_(s32) = nsw G_MUL [[COPY]], [[C2]] ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C2]]
; CHECK: bb.4.return: ; CHECK: bb.4.return:
; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI %10(s32), %bb.3, %12(s32), %bb.2, [[C4]](s32), %bb.5 ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C4]](s32), %bb.5
; CHECK: $w0 = COPY [[PHI]](s32) ; CHECK: $w0 = COPY [[PHI]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
entry: entry:
switch i32 %x, label %return [ switch i32 %x, label %return [
i32 24, label %sw.bb i32 24, label %sw.bb
i32 25, label %sw.bb i32 25, label %sw.bb
i32 26, label %sw.bb i32 26, label %sw.bb
i32 6, label %sw.bb1 i32 6, label %sw.bb1
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
%type = type [4 x {i8, i32}] %type = type [4 x {i8, i32}]
define i8* @translate_element_size1(i64 %arg) { define i8* @translate_element_size1(i64 %arg) {
; CHECK-LABEL: name: translate_element_size1 ; CHECK-LABEL: name: translate_element_size1
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[COPY]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY [[GEP]](p0) ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK: $x0 = COPY [[COPY1]](p0) ; CHECK: $x0 = COPY [[COPY1]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%tmp = getelementptr i8, i8* null, i64 %arg %tmp = getelementptr i8, i8* null, i64 %arg
ret i8* %tmp ret i8* %tmp
} }
define %type* @first_offset_const(%type* %addr) { define %type* @first_offset_const(%type* %addr) {
; CHECK-LABEL: name: first_offset_const ; CHECK-LABEL: name: first_offset_const
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK: $x0 = COPY [[GEP]](p0) ; CHECK: $x0 = COPY [[PTR_ADD]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 1 %res = getelementptr %type, %type* %addr, i32 1
ret %type* %res ret %type* %res
} }
define %type* @first_offset_trivial(%type* %addr) { define %type* @first_offset_trivial(%type* %addr) {
; CHECK-LABEL: name: first_offset_trivial ; CHECK-LABEL: name: first_offset_trivial
Show All 10 Lines
define %type* @first_offset_variable(%type* %addr, i64 %idx) { define %type* @first_offset_variable(%type* %addr, i64 %idx) {
; CHECK-LABEL: name: first_offset_variable ; CHECK-LABEL: name: first_offset_variable
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[COPY1]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i64 %idx %res = getelementptr %type, %type* %addr, i64 %idx
ret %type* %res ret %type* %res
} }
define %type* @first_offset_ext(%type* %addr, i32 %idx) { define %type* @first_offset_ext(%type* %addr, i32 %idx) {
; CHECK-LABEL: name: first_offset_ext ; CHECK-LABEL: name: first_offset_ext
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $w1, $x0 ; CHECK: liveins: $w1, $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32) ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 %idx %res = getelementptr %type, %type* %addr, i32 %idx
ret %type* %res ret %type* %res
} }
%type1 = type [4 x [4 x i32]] %type1 = type [4 x [4 x i32]]
define i32* @const_then_var(%type1* %addr, i64 %idx) { define i32* @const_then_var(%type1* %addr, i64 %idx) {
; CHECK-LABEL: name: const_then_var ; CHECK-LABEL: name: const_then_var
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 272
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C1]], [[COPY1]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C1]]
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[GEP]], [[MUL]](s64) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[MUL]](s64)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP1]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD1]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx %res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx
ret i32* %res ret i32* %res
} }
define i32* @var_then_const(%type1* %addr, i64 %idx) { define i32* @var_then_const(%type1* %addr, i64 %idx) {
; CHECK-LABEL: name: var_then_const ; CHECK-LABEL: name: var_then_const
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[COPY1]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY1]], [[C]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[MUL]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[GEP]], [[C1]](s64) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
; CHECK: $x0 = COPY [[GEP1]](p0) ; CHECK: $x0 = COPY [[PTR_ADD1]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2 %res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
ret i32* %res ret i32* %res
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-getelementptr.ll

Show All 17 Linesdefine <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i64(<2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx) {
; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) ; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) ; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) ; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[BUILD_VECTOR1]] ; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
; CHECK: [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>) ; CHECK: [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY9]](<2 x p1>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY9]](<2 x p1>)
; CHECK: $vgpr0 = COPY [[UV]](s32) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32) ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32) ; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32) ; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]] ; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
Show All 11 Linesdefine <2 x i32 addrspace(3)*> @vector_gep_v2p3_index_v2i32(<2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx) {
; CHECK: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY]](p3), [[COPY1]](p3) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[COPY]](p3), [[COPY1]](p3)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[BUILD_VECTOR2]], [[BUILD_VECTOR1]] ; CHECK: [[MUL:%[0-9]+]]:_(<2 x s32>) = G_MUL [[BUILD_VECTOR1]], [[BUILD_VECTOR2]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p3>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s32>) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p3>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s32>)
; CHECK: [[COPY5:%[0-9]+]]:_(<2 x p3>) = COPY [[PTR_ADD]](<2 x p3>) ; CHECK: [[COPY5:%[0-9]+]]:_(<2 x p3>) = COPY [[PTR_ADD]](<2 x p3>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY5]](<2 x p3>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY5]](<2 x p3>)
; CHECK: $vgpr0 = COPY [[UV]](s32) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32) ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]] ; CHECK: [[COPY6:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
; CHECK: S_SETPC_B64_return [[COPY6]], implicit $vgpr0, implicit $vgpr1 ; CHECK: S_SETPC_B64_return [[COPY6]], implicit $vgpr0, implicit $vgpr1
%gep = getelementptr i32, <2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx %gep = getelementptr i32, <2 x i32 addrspace(3)*> %ptr, <2 x i32> %idx
Show All 14 Linesdefine <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i32(<2 x i32 addrspace(1)*> %ptr, <2 x i32> %idx) {
; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) ; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>) ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[SEXT]] ; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
; CHECK: [[COPY7:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>) ; CHECK: [[COPY7:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY7]](<2 x p1>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY7]](<2 x p1>)
; CHECK: $vgpr0 = COPY [[UV]](s32) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32) ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32) ; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32) ; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]] ; CHECK: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]]
Show All 17 Linesdefine <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_i64(<2 x i32 addrspace(1)*> %ptr, i64 %idx) {
; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) ; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) ; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV2]](s64) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV2]](s64)
; CHECK: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY [[BUILD_VECTOR1]](<2 x s64>) ; CHECK: [[COPY7:%[0-9]+]]:_(<2 x s64>) = COPY [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[COPY7]] ; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[COPY7]], [[BUILD_VECTOR2]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
; CHECK: [[COPY8:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>) ; CHECK: [[COPY8:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY8]](<2 x p1>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY8]](<2 x p1>)
; CHECK: $vgpr0 = COPY [[UV]](s32) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32) ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32) ; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32) ; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]] ; CHECK: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY6]]
Show All 15 Linesdefine <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_i32(<2 x i32 addrspace(1)*> %ptr, i32 %idx) {
; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) ; CHECK: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY4]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY4]](s32)
; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>) ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[SEXT]] ; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[SEXT]], [[BUILD_VECTOR2]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
; CHECK: [[COPY6:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>) ; CHECK: [[COPY6:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY6]](<2 x p1>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY6]](<2 x p1>)
; CHECK: $vgpr0 = COPY [[UV]](s32) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32) ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32) ; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32) ; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY5]] ; CHECK: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY5]]
Show All 22 Linesdefine <2 x i32 addrspace(1)*> @vector_gep_v2p1_index_v2i64_constant(<2 x i32 addrspace(1)*> %ptr, <2 x i64> %idx) {
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) ; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) ; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV2]](s64), [[MV3]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64) ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR3]], [[BUILD_VECTOR2]] ; CHECK: [[MUL:%[0-9]+]]:_(<2 x s64>) = G_MUL [[BUILD_VECTOR2]], [[BUILD_VECTOR3]]
; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p1>) = G_PTR_ADD [[BUILD_VECTOR]], [[MUL]](<2 x s64>)
; CHECK: [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>) ; CHECK: [[COPY9:%[0-9]+]]:_(<2 x p1>) = COPY [[PTR_ADD]](<2 x p1>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY9]](<2 x p1>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY9]](<2 x p1>)
; CHECK: $vgpr0 = COPY [[UV]](s32) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: $vgpr1 = COPY [[UV1]](s32) ; CHECK: $vgpr1 = COPY [[UV1]](s32)
; CHECK: $vgpr2 = COPY [[UV2]](s32) ; CHECK: $vgpr2 = COPY [[UV2]](s32)
; CHECK: $vgpr3 = COPY [[UV3]](s32) ; CHECK: $vgpr3 = COPY [[UV3]](s32)
; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]] ; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY8]]
; CHECK: S_SETPC_B64_return [[COPY10]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; CHECK: S_SETPC_B64_return [[COPY10]], implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
%gep = getelementptr i32, <2 x i32 addrspace(1)*> %ptr, <2 x i64> <i64 1, i64 2> %gep = getelementptr i32, <2 x i32 addrspace(1)*> %ptr, <2 x i64> <i64 1, i64 2>
ret <2 x i32 addrspace(1)*> %gep ret <2 x i32 addrspace(1)*> %gep
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll

; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN %s
; FIXME: Merge with DAG test ; FIXME: Merge with DAG test
@lds.external = external unnamed_addr addrspace(3) global [0 x i32] @lds.external = external unnamed_addr addrspace(3) global [0 x i32]
@lds.defined = unnamed_addr addrspace(3) global [8 x i32] undef, align 8 @lds.defined = unnamed_addr addrspace(3) global [8 x i32] undef, align 8
; GCN-LABEL: {{^}}test_basic: ; GCN-LABEL: {{^}}test_basic:
; GCN: s_add_u32 s0, lds.defined@abs32@lo, s0 ; encoding: [0xff,0x00,0x00,0x80,A,A,A,A] ; GCN: s_add_u32 s0, lds.defined@abs32@lo, s2 ; encoding: [0xff,0x02,0x00,0x80,A,A,A,A]
; GCN: v_add_u32_e32 v0, lds.external@abs32@lo, v0 ; encoding: [0xff,0x00,0x00,0x68,A,A,A,A] ; GCN: v_add_u32_e32 v0, lds.external@abs32@lo, v0 ; encoding: [0xff,0x00,0x00,0x68,A,A,A,A]
; GCN: .globl lds.external ; GCN: .globl lds.external
; GCN: .amdgpu_lds lds.external, 0, 4 ; GCN: .amdgpu_lds lds.external, 0, 4
; GCN: .globl lds.defined ; GCN: .globl lds.defined
; GCN: .amdgpu_lds lds.defined, 32, 8 ; GCN: .amdgpu_lds lds.defined, 32, 8
define amdgpu_gs float @test_basic(i32 inreg %wave, i32 %arg1) #0 { define amdgpu_gs float @test_basic(i32 inreg %wave, i32 %arg1) #0 {
main_body: main_body:
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll

Show First 20 Lines • Show All 363 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_dec_ret_i32_offset_addr64: ; CI-LABEL: global_atomic_dec_ret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v4, 4, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: flat_atomic_dec v0, v[0:1], v4 glc ; CI-NEXT: flat_atomic_dec v0, v[0:1], v4 glc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dword v[2:3], v0 ; CI-NEXT: flat_store_dword v[2:3], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_dec_ret_i32_offset_addr64: ; VI-LABEL: global_atomic_dec_ret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v4, 4, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
Show All 36 Lines; GFX9-NEXT: s_endpgm
store i32 %result, i32 addrspace(1)* %out.gep store i32 %result, i32 addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_dec_noret_i32_offset_addr64: ; CI-LABEL: global_atomic_dec_noret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v0, 4, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_atomic_dec v0, v[0:1], v2 glc ; CI-NEXT: flat_atomic_dec v0, v[0:1], v2 glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_dec_noret_i32_offset_addr64: ; VI-LABEL: global_atomic_dec_noret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v0, 4, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
; CI-LABEL: flat_atomic_dec_ret_i32_offset_addr64: ; CI-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v4, 4, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: flat_atomic_dec v0, v[0:1], v4 glc ; CI-NEXT: flat_atomic_dec v0, v[0:1], v4 glc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dword v[2:3], v0 ; CI-NEXT: flat_store_dword v[2:3], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_dec_ret_i32_offset_addr64: ; VI-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v4, 4, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
Show All 36 Lines; GFX9-NEXT: s_endpgm
store i32 %result, i32* %out.gep store i32 %result, i32* %out.gep
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0 {
; CI-LABEL: flat_atomic_dec_noret_i32_offset_addr64: ; CI-LABEL: flat_atomic_dec_noret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v0, 4, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_atomic_dec v0, v[0:1], v2 glc ; CI-NEXT: flat_atomic_dec v0, v[0:1], v2 glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_dec_noret_i32_offset_addr64: ; VI-LABEL: flat_atomic_dec_noret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v0, 4, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
; CI-LABEL: flat_atomic_dec_ret_i64_offset_addr64: ; CI-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v4, 8, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: v_mov_b32_e32 v5, 0 ; CI-NEXT: v_mov_b32_e32 v5, 0
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[4:5] glc ; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[4:5] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_dec_ret_i64_offset_addr64: ; VI-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v4, 8, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
Show All 38 Lines; GFX9-NEXT: s_endpgm
store i64 %result, i64* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 {
; CI-LABEL: flat_atomic_dec_noret_i64_offset_addr64: ; CI-LABEL: flat_atomic_dec_noret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v0, 8, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: v_mov_b32_e32 v3, 0 ; CI-NEXT: v_mov_b32_e32 v3, 0
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc ; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_dec_noret_i64_offset_addr64: ; VI-LABEL: flat_atomic_dec_noret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v0, 8, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
Show All 27 Lines; GFX9-NEXT: s_endpgm
ret void ret void
} }
@lds0 = internal addrspace(3) global [512 x i32] undef @lds0 = internal addrspace(3) global [512 x i32] undef
define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
; CI-LABEL: atomic_dec_shl_base_lds_0: ; CI-LABEL: atomic_dec_shl_base_lds_0:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_mul_lo_u32 v5, 4, v0 ; CI-NEXT: v_mul_lo_u32 v5, v0, 4
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mov_b32_e32 v6, 9 ; CI-NEXT: v_mov_b32_e32 v6, 9
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: v_add_i32_e32 v5, vcc, 0, v5 ; CI-NEXT: v_add_i32_e32 v5, vcc, 0, v5
; CI-NEXT: v_add_i32_e32 v5, vcc, 8, v5 ; CI-NEXT: v_add_i32_e32 v5, vcc, 8, v5
; CI-NEXT: ds_dec_rtn_u32 v5, v5, v6 ; CI-NEXT: ds_dec_rtn_u32 v5, v5, v6
; CI-NEXT: v_add_i32_e32 v4, vcc, 2, v0 ; CI-NEXT: v_add_i32_e32 v4, vcc, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v4 ; CI-NEXT: flat_store_dword v[0:1], v4
; CI-NEXT: flat_store_dword v[2:3], v5 ; CI-NEXT: flat_store_dword v[2:3], v5
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: atomic_dec_shl_base_lds_0: ; VI-LABEL: atomic_dec_shl_base_lds_0:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_mul_lo_u32 v5, 4, v0 ; VI-NEXT: v_mul_lo_u32 v5, v0, 4
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mov_b32_e32 v6, 9 ; VI-NEXT: v_mov_b32_e32 v6, 9
; VI-NEXT: s_mov_b32 m0, -1 ; VI-NEXT: s_mov_b32 m0, -1
; VI-NEXT: v_add_u32_e32 v5, vcc, 0, v5 ; VI-NEXT: v_add_u32_e32 v5, vcc, 0, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 8, v5 ; VI-NEXT: v_add_u32_e32 v5, vcc, 8, v5
; VI-NEXT: ds_dec_rtn_u32 v5, v5, v6 ; VI-NEXT: ds_dec_rtn_u32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0 ; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 393 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_dec_ret_i64_offset_addr64: ; CI-LABEL: global_atomic_dec_ret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v4, 8, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: v_mov_b32_e32 v5, 0 ; CI-NEXT: v_mov_b32_e32 v5, 0
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[4:5] glc ; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[4:5] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_dec_ret_i64_offset_addr64: ; VI-LABEL: global_atomic_dec_ret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v4, 8, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
Show All 38 Lines; GFX9-NEXT: s_endpgm
store i64 %result, i64 addrspace(1)* %out.gep store i64 %result, i64 addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_dec_noret_i64_offset_addr64: ; CI-LABEL: global_atomic_dec_noret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v0, 8, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: v_mov_b32_e32 v3, 0 ; CI-NEXT: v_mov_b32_e32 v3, 0
; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc ; CI-NEXT: flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_dec_noret_i64_offset_addr64: ; VI-LABEL: global_atomic_dec_noret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v0, 8, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
Show All 27 Lines; GFX9-NEXT: s_endpgm
ret void ret void
} }
@lds1 = internal addrspace(3) global [512 x i64] undef, align 8 @lds1 = internal addrspace(3) global [512 x i64] undef, align 8
define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
; CI-LABEL: atomic_dec_shl_base_lds_0_i64: ; CI-LABEL: atomic_dec_shl_base_lds_0_i64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_mul_lo_u32 v7, 8, v0 ; CI-NEXT: v_mul_lo_u32 v7, v0, 8
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_add_i32_e32 v6, vcc, 2, v0 ; CI-NEXT: v_add_i32_e32 v6, vcc, 2, v0
; CI-NEXT: v_mov_b32_e32 v0, 9 ; CI-NEXT: v_mov_b32_e32 v0, 9
; CI-NEXT: v_add_i32_e32 v7, vcc, 0, v7 ; CI-NEXT: v_add_i32_e32 v7, vcc, 0, v7
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_add_i32_e32 v7, vcc, 16, v7 ; CI-NEXT: v_add_i32_e32 v7, vcc, 16, v7
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_dec_rtn_u64 v[0:1], v7, v[0:1] ; CI-NEXT: ds_dec_rtn_u64 v[0:1], v7, v[0:1]
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2 ; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_mov_b32_e32 v3, s3 ; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: v_mov_b32_e32 v4, s0 ; CI-NEXT: v_mov_b32_e32 v4, s0
; CI-NEXT: flat_store_dword v[2:3], v6 ; CI-NEXT: flat_store_dword v[2:3], v6
; CI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: atomic_dec_shl_base_lds_0_i64: ; VI-LABEL: atomic_dec_shl_base_lds_0_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_mul_lo_u32 v7, 8, v0 ; VI-NEXT: v_mul_lo_u32 v7, v0, 8
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0 ; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0
; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v0, 9
; VI-NEXT: v_add_u32_e32 v7, vcc, 0, v7 ; VI-NEXT: v_add_u32_e32 v7, vcc, 0, v7
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v7 ; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v7
; VI-NEXT: s_mov_b32 m0, -1 ; VI-NEXT: s_mov_b32 m0, -1
; VI-NEXT: ds_dec_rtn_u64 v[0:1], v7, v[0:1] ; VI-NEXT: ds_dec_rtn_u64 v[0:1], v7, v[0:1]
Show All 38 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

Show First 20 Lines • Show All 365 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_inc_ret_i32_offset_addr64: ; CI-LABEL: global_atomic_inc_ret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v4, 4, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc ; CI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dword v[2:3], v0 ; CI-NEXT: flat_store_dword v[2:3], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_inc_ret_i32_offset_addr64: ; VI-LABEL: global_atomic_inc_ret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v4, 4, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_mov_b32_e32 v4, 42 ; VI-NEXT: v_mov_b32_e32 v4, 42
; VI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc ; VI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: global_atomic_inc_ret_i32_offset_addr64: ; GFX9-LABEL: global_atomic_inc_ret_i32_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 4
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 4
; GFX9-NEXT: v_mul_lo_u32 v4, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, 4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v5, 42 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add3_u32 v2, v2, v1, v3 ; GFX9-NEXT: v_add3_u32 v3, v1, v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
; GFX9-NEXT: global_atomic_inc v3, v[0:1], v5, off glc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, 42
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v4 ; GFX9-NEXT: global_atomic_inc v0, v[0:1], v4, off glc
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v3, off ; GFX9-NEXT: global_store_dword v[2:3], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id
%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(1)* %out.gep store i32 %result, i32 addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_inc_noret_i32_offset_addr64: ; CI-LABEL: global_atomic_inc_noret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v0, 4, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc ; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_inc_noret_i32_offset_addr64: ; VI-LABEL: global_atomic_inc_noret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v0, 4, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc ; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: global_atomic_inc_noret_i32_offset_addr64: ; GFX9-LABEL: global_atomic_inc_noret_i32_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 4
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 4
; GFX9-NEXT: v_mul_lo_u32 v0, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, 4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v5, 42 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_add3_u32 v1, v2, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_atomic_inc v0, v[0:1], v5, off glc ; GFX9-NEXT: v_mov_b32_e32 v2, 42
; GFX9-NEXT: global_atomic_inc v0, v[0:1], v2, off glc
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id
%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
@lds0 = internal addrspace(3) global [512 x i32] undef, align 4 @lds0 = internal addrspace(3) global [512 x i32] undef, align 4
define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
; CI-LABEL: atomic_inc_shl_base_lds_0_i32: ; CI-LABEL: atomic_inc_shl_base_lds_0_i32:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_mul_lo_u32 v5, 4, v0 ; CI-NEXT: v_mul_lo_u32 v5, v0, 4
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mov_b32_e32 v6, 9 ; CI-NEXT: v_mov_b32_e32 v6, 9
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: v_add_i32_e32 v5, vcc, 0, v5 ; CI-NEXT: v_add_i32_e32 v5, vcc, 0, v5
; CI-NEXT: v_add_i32_e32 v5, vcc, 8, v5 ; CI-NEXT: v_add_i32_e32 v5, vcc, 8, v5
; CI-NEXT: ds_inc_rtn_u32 v5, v5, v6 ; CI-NEXT: ds_inc_rtn_u32 v5, v5, v6
; CI-NEXT: v_add_i32_e32 v4, vcc, 2, v0 ; CI-NEXT: v_add_i32_e32 v4, vcc, 2, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_mov_b32_e32 v2, s0 ; CI-NEXT: v_mov_b32_e32 v2, s0
; CI-NEXT: flat_store_dword v[0:1], v4 ; CI-NEXT: flat_store_dword v[0:1], v4
; CI-NEXT: flat_store_dword v[2:3], v5 ; CI-NEXT: flat_store_dword v[2:3], v5
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: atomic_inc_shl_base_lds_0_i32: ; VI-LABEL: atomic_inc_shl_base_lds_0_i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_mul_lo_u32 v5, 4, v0 ; VI-NEXT: v_mul_lo_u32 v5, v0, 4
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mov_b32_e32 v6, 9 ; VI-NEXT: v_mov_b32_e32 v6, 9
; VI-NEXT: s_mov_b32 m0, -1 ; VI-NEXT: s_mov_b32 m0, -1
; VI-NEXT: v_add_u32_e32 v5, vcc, 0, v5 ; VI-NEXT: v_add_u32_e32 v5, vcc, 0, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 8, v5 ; VI-NEXT: v_add_u32_e32 v5, vcc, 8, v5
; VI-NEXT: ds_inc_rtn_u32 v5, v5, v6 ; VI-NEXT: ds_inc_rtn_u32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0 ; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v4 ; VI-NEXT: flat_store_dword v[0:1], v4
; VI-NEXT: flat_store_dword v[2:3], v5 ; VI-NEXT: flat_store_dword v[2:3], v5
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: atomic_inc_shl_base_lds_0_i32: ; GFX9-LABEL: atomic_inc_shl_base_lds_0_i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_add_u32_e32 v3, 2, v0 ; GFX9-NEXT: v_add_u32_e32 v3, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 9 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
; GFX9-NEXT: v_add_u32_e32 v0, 0, v1 ; GFX9-NEXT: v_add_u32_e32 v0, 0, v1
; GFX9-NEXT: v_add_u32_e32 v0, 8, v0 ; GFX9-NEXT: v_add_u32_e32 v0, 8, v0
; GFX9-NEXT: ds_inc_rtn_u32 v2, v0, v2 ; GFX9-NEXT: ds_inc_rtn_u32 v2, v0, v2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
▲ Show 20 Lines • Show All 383 Lines • ▼ Show 20 Lines; GFX9-NEXT: s_endpgm
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_inc_ret_i64_offset_addr64: ; CI-LABEL: global_atomic_inc_ret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v4, 8, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: v_mov_b32_e32 v5, 0 ; CI-NEXT: v_mov_b32_e32 v5, 0
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_inc_ret_i64_offset_addr64: ; VI-LABEL: global_atomic_inc_ret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v4, 8, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; VI-NEXT: v_mov_b32_e32 v4, 42 ; VI-NEXT: v_mov_b32_e32 v4, 42
; VI-NEXT: v_mov_b32_e32 v5, 0 ; VI-NEXT: v_mov_b32_e32 v5, 0
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: global_atomic_inc_ret_i64_offset_addr64: ; GFX9-LABEL: global_atomic_inc_ret_i64_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX9-NEXT: v_mul_hi_u32 v4, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v5, 8, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX9-NEXT: v_mul_lo_u32 v4, v0, 8
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v6, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v0, 42 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add3_u32 v4, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v3, v1, v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s2, v5 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 40, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 40, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v[2:3], v[0:1], off glc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, 42
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v5 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v[0:1], v[4:5], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(1)* %out.gep store i64 %result, i64 addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
; CI-LABEL: global_atomic_inc_noret_i64_offset_addr64: ; CI-LABEL: global_atomic_inc_noret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v0, 8, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: v_mov_b32_e32 v3, 0 ; CI-NEXT: v_mov_b32_e32 v3, 0
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: global_atomic_inc_noret_i64_offset_addr64: ; VI-LABEL: global_atomic_inc_noret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v0, 8, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, 0 ; VI-NEXT: v_mov_b32_e32 v3, 0
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: global_atomic_inc_noret_i64_offset_addr64: ; GFX9-LABEL: global_atomic_inc_noret_i64_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX9-NEXT: v_mul_hi_u32 v4, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v5, 8, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 8
; GFX9-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v6, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v0, 42 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, s0, v5 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 40, v0
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v2, 42
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 40, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v[0:1], v[2:3], off glc
; GFX9-NEXT: global_atomic_inc_x2 v[0:1], v[2:3], v[0:1], off glc
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; GCN-NEXT: s_endpgm
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
; CI-LABEL: flat_atomic_inc_ret_i32_offset_addr64: ; CI-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v4, 4, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc ; CI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dword v[2:3], v0 ; CI-NEXT: flat_store_dword v[2:3], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_inc_ret_i32_offset_addr64: ; VI-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v4, 4, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_mov_b32_e32 v4, 42 ; VI-NEXT: v_mov_b32_e32 v4, 42
; VI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc ; VI-NEXT: flat_atomic_inc v0, v[0:1], v4 glc
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: flat_atomic_inc_ret_i32_offset_addr64: ; GFX9-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 4
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 4
; GFX9-NEXT: v_mul_lo_u32 v4, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, 4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v5, 42 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add3_u32 v2, v2, v1, v3 ; GFX9-NEXT: v_add3_u32 v3, v1, v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s2, v4 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v1 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v1
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
; GFX9-NEXT: flat_atomic_inc v3, v[0:1], v5 glc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, 42
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v4 ; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v4 glc
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: flat_store_dword v[0:1], v3 ; GFX9-NEXT: flat_store_dword v[2:3], v0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%out.gep = getelementptr i32, i32* %out, i32 %id %out.gep = getelementptr i32, i32* %out, i32 %id
%gep = getelementptr i32, i32* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32* %out.gep store i32 %result, i32* %out.gep
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0 {
; CI-LABEL: flat_atomic_inc_noret_i32_offset_addr64: ; CI-LABEL: flat_atomic_inc_noret_i32_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 4
; CI-NEXT: v_mul_lo_u32 v1, 4, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 4, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 4
; CI-NEXT: v_mul_lo_u32 v0, 4, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 4
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 20, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc ; CI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_inc_noret_i32_offset_addr64: ; VI-LABEL: flat_atomic_inc_noret_i32_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 4
; VI-NEXT: v_mul_lo_u32 v1, 4, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 4, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 4
; VI-NEXT: v_mul_lo_u32 v0, 4, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 4
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 20, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc ; VI-NEXT: flat_atomic_inc v0, v[0:1], v2 glc
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: flat_atomic_inc_noret_i32_offset_addr64: ; GFX9-LABEL: flat_atomic_inc_noret_i32_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 4
; GFX9-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 4
; GFX9-NEXT: v_mul_lo_u32 v0, 4, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, 4
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s1 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v5, 42 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_add3_u32 v1, v2, v1, v3
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 20, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v5 glc ; GFX9-NEXT: v_mov_b32_e32 v2, 42
; GFX9-NEXT: flat_atomic_inc v0, v[0:1], v2 glc
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%gep = getelementptr i32, i32* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
@lds1 = internal addrspace(3) global [512 x i64] undef, align 8 @lds1 = internal addrspace(3) global [512 x i64] undef, align 8
define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
; CI-LABEL: atomic_inc_shl_base_lds_0_i64: ; CI-LABEL: atomic_inc_shl_base_lds_0_i64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_mul_lo_u32 v7, 8, v0 ; CI-NEXT: v_mul_lo_u32 v7, v0, 8
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_add_i32_e32 v6, vcc, 2, v0 ; CI-NEXT: v_add_i32_e32 v6, vcc, 2, v0
; CI-NEXT: v_mov_b32_e32 v0, 9 ; CI-NEXT: v_mov_b32_e32 v0, 9
; CI-NEXT: v_add_i32_e32 v7, vcc, 0, v7 ; CI-NEXT: v_add_i32_e32 v7, vcc, 0, v7
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: v_add_i32_e32 v7, vcc, 16, v7 ; CI-NEXT: v_add_i32_e32 v7, vcc, 16, v7
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_inc_rtn_u64 v[0:1], v7, v[0:1] ; CI-NEXT: ds_inc_rtn_u64 v[0:1], v7, v[0:1]
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v2, s2 ; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_mov_b32_e32 v3, s3 ; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: v_mov_b32_e32 v4, s0 ; CI-NEXT: v_mov_b32_e32 v4, s0
; CI-NEXT: flat_store_dword v[2:3], v6 ; CI-NEXT: flat_store_dword v[2:3], v6
; CI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: atomic_inc_shl_base_lds_0_i64: ; VI-LABEL: atomic_inc_shl_base_lds_0_i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_mul_lo_u32 v7, 8, v0 ; VI-NEXT: v_mul_lo_u32 v7, v0, 8
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0 ; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0
; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v0, 9
; VI-NEXT: v_add_u32_e32 v7, vcc, 0, v7 ; VI-NEXT: v_add_u32_e32 v7, vcc, 0, v7
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v7 ; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v7
; VI-NEXT: s_mov_b32 m0, -1 ; VI-NEXT: s_mov_b32 m0, -1
; VI-NEXT: ds_inc_rtn_u64 v[0:1], v7, v[0:1] ; VI-NEXT: ds_inc_rtn_u64 v[0:1], v7, v[0:1]
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v3, s3 ; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dword v[2:3], v6 ; VI-NEXT: flat_store_dword v[2:3], v6
; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: atomic_inc_shl_base_lds_0_i64: ; GFX9-LABEL: atomic_inc_shl_base_lds_0_i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, 8
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mov_b32_e32 v1, 9 ; GFX9-NEXT: v_mov_b32_e32 v1, 9
; GFX9-NEXT: v_add_u32_e32 v4, 2, v0 ; GFX9-NEXT: v_add_u32_e32 v4, 2, v0
; GFX9-NEXT: v_add_u32_e32 v0, 0, v3 ; GFX9-NEXT: v_add_u32_e32 v0, 0, v3
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_add_u32_e32 v0, 16, v0 ; GFX9-NEXT: v_add_u32_e32 v0, 16, v0
; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v0, v[1:2] ; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v0, v[1:2]
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; GCN-NEXT: s_endpgm
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
; CI-LABEL: flat_atomic_inc_ret_i64_offset_addr64: ; CI-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v4, 8, v0 ; CI-NEXT: v_mul_lo_u32 v4, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v3, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s3 ; CI-NEXT: v_mov_b32_e32 v0, s3
; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4 ; CI-NEXT: v_add_i32_e32 v1, vcc, s2, v4
; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v1
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; CI-NEXT: v_mov_b32_e32 v5, s1 ; CI-NEXT: v_mov_b32_e32 v5, s1
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v4
; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; CI-NEXT: v_mov_b32_e32 v4, 42 ; CI-NEXT: v_mov_b32_e32 v4, 42
; CI-NEXT: v_mov_b32_e32 v5, 0 ; CI-NEXT: v_mov_b32_e32 v5, 0
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_inc_ret_i64_offset_addr64: ; VI-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v4, 8, v0 ; VI-NEXT: v_mul_lo_u32 v4, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s3 ; VI-NEXT: v_mov_b32_e32 v0, s3
; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4 ; VI-NEXT: v_add_u32_e32 v1, vcc, s2, v4
; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; VI-NEXT: v_mov_b32_e32 v4, 42 ; VI-NEXT: v_mov_b32_e32 v4, 42
; VI-NEXT: v_mov_b32_e32 v5, 0 ; VI-NEXT: v_mov_b32_e32 v5, 0
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: flat_atomic_inc_ret_i64_offset_addr64: ; GFX9-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX9-NEXT: v_mul_hi_u32 v4, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v5, 8, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX9-NEXT: v_mul_lo_u32 v4, v0, 8
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v6, s3 ; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v0, 42 ; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_add3_u32 v4, v2, v3, v4 ; GFX9-NEXT: v_add3_u32 v3, v1, v2, v3
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s2, v5 ; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s2, v4
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v0, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 40, v2 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 40, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v4
; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc
; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: v_mov_b32_e32 v4, 42
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v5 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX9-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 {
; CI-LABEL: flat_atomic_inc_noret_i64_offset_addr64: ; CI-LABEL: flat_atomic_inc_noret_i64_offset_addr64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_mul_hi_u32 v3, 8, v0 ; CI-NEXT: v_mul_hi_u32 v3, v0, 8
; CI-NEXT: v_mul_lo_u32 v0, 8, v0 ; CI-NEXT: v_mul_lo_u32 v0, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v4, s1 ; CI-NEXT: v_mov_b32_e32 v4, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 40, v0
; CI-NEXT: v_mov_b32_e32 v2, 42 ; CI-NEXT: v_mov_b32_e32 v2, 42
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: v_mov_b32_e32 v3, 0 ; CI-NEXT: v_mov_b32_e32 v3, 0
; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc ; CI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: flat_atomic_inc_noret_i64_offset_addr64: ; VI-LABEL: flat_atomic_inc_noret_i64_offset_addr64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; VI-NEXT: v_mul_lo_u32 v2, 0, v0 ; VI-NEXT: v_mul_lo_u32 v1, v1, 8
; VI-NEXT: v_mul_lo_u32 v1, 8, v1 ; VI-NEXT: v_mul_lo_u32 v2, v0, 0
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: v_mul_hi_u32 v3, 8, v0 ; VI-NEXT: v_mul_hi_u32 v3, v0, 8
; VI-NEXT: v_mul_lo_u32 v0, 8, v0 ; VI-NEXT: v_mul_lo_u32 v0, v0, 8
; VI-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v4, s1 ; VI-NEXT: v_mov_b32_e32 v4, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 40, v0
; VI-NEXT: v_mov_b32_e32 v2, 42 ; VI-NEXT: v_mov_b32_e32 v2, 42
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, 0 ; VI-NEXT: v_mov_b32_e32 v3, 0
; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc ; VI-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: flat_atomic_inc_noret_i64_offset_addr64: ; GFX9-LABEL: flat_atomic_inc_noret_i64_offset_addr64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: v_mul_lo_u32 v3, 8, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX9-NEXT: v_mul_hi_u32 v4, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v5, 8, v0 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX9-NEXT: v_mul_lo_u32 v0, v0, 8
; GFX9-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v6, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v0, 42 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_add3_u32 v2, v2, v3, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, s0, v5 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 40, v0
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v2, 42
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 40, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GFX9-NEXT: flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; TODO: Merge with DAG test ; TODO: Merge with DAG test
define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) { define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) {
; CI-LABEL: is_private_vgpr: ; CI-LABEL: is_private_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: v_mul_lo_u32 v3, 8, v0 ; CI-NEXT: v_mul_lo_u32 v3, v0, 8
; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; CI-NEXT: v_mul_hi_u32 v0, 8, v0 ; CI-NEXT: v_mul_hi_u32 v0, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v0 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v3 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v3
; CI-NEXT: v_mov_b32_e32 v2, s1 ; CI-NEXT: v_mov_b32_e32 v2, s1
; CI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; CI-NEXT: s_load_dword s0, s[4:5], 0x11 ; CI-NEXT: s_load_dword s0, s[4:5], 0x11
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 ; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1
; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_private_vgpr: ; GFX9-LABEL: is_private_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX9-NEXT: v_mul_hi_u32 v3, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v1, 8, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX9-NEXT: v_mul_lo_u32 v0, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, 8
; GFX9-NEXT: v_add3_u32 v1, v2, v1, v3 ; GFX9-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; TODO: Merge with DAG test ; TODO: Merge with DAG test
define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) {
; CI-LABEL: is_local_vgpr: ; CI-LABEL: is_local_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; CI-NEXT: v_mul_lo_u32 v2, 0, v0 ; CI-NEXT: v_mul_lo_u32 v1, v1, 8
; CI-NEXT: v_mul_lo_u32 v1, 8, v1 ; CI-NEXT: v_mul_lo_u32 v2, v0, 0
; CI-NEXT: v_mul_lo_u32 v3, 8, v0 ; CI-NEXT: v_mul_lo_u32 v3, v0, 8
; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; CI-NEXT: v_mul_hi_u32 v0, 8, v0 ; CI-NEXT: v_mul_hi_u32 v0, v0, 8
; CI-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v0 ; CI-NEXT: v_add_i32_e32 v1, vcc, v1, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v3 ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v3
; CI-NEXT: v_mov_b32_e32 v2, s1 ; CI-NEXT: v_mov_b32_e32 v2, s1
; CI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; CI-NEXT: s_load_dword s0, s[4:5], 0x10 ; CI-NEXT: s_load_dword s0, s[4:5], 0x10
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 ; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1
; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_local_vgpr: ; GFX9-LABEL: is_local_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX9-NEXT: v_mul_hi_u32 v3, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX9-NEXT: v_mul_lo_u32 v1, 8, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX9-NEXT: v_mul_lo_u32 v0, 8, v0 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, 8
; GFX9-NEXT: v_add3_u32 v1, v2, v1, v3 ; GFX9-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

Show All 34 Lines; GFX10-NEXT: s_endpgm
%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false)
store i32 %tmp0, i32 addrspace(1)* %out store i32 %tmp0, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) { define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) {
; GFX8-LABEL: update_dpp64_test: ; GFX8-LABEL: update_dpp64_test:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX8-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX8-NEXT: v_mul_lo_u32 v1, 8, v1 ; GFX8-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: v_mul_hi_u32 v3, 8, v0 ; GFX8-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX8-NEXT: v_mul_lo_u32 v0, 8, v0 ; GFX8-NEXT: v_mul_lo_u32 v0, v0, 8
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, s1 ; GFX8-NEXT: v_mov_b32_e32 v4, s1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v4, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v5, s3 ; GFX8-NEXT: v_mov_b32_e32 v5, s3
; GFX8-NEXT: v_mov_b32_e32 v4, s2 ; GFX8-NEXT: v_mov_b32_e32 v4, s2
; GFX8-NEXT: s_nop 0 ; GFX8-NEXT: s_nop 0
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: update_dpp64_test: ; GFX10-LABEL: update_dpp64_test:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX10-NEXT: v_mul_lo_u32 v2, v0, 0
; GFX10-NEXT: v_mul_hi_u32 v3, 8, v0 ; GFX10-NEXT: v_mul_hi_u32 v3, v0, 8
; GFX10-NEXT: v_mul_lo_u32 v0, 8, v0 ; GFX10-NEXT: v_mul_lo_u32 v0, v0, 8
; GFX10-NEXT: v_mul_lo_u32 v1, 8, v1 ; GFX10-NEXT: v_mul_lo_u32 v1, v1, 8
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_add_co_u32_e64 v6, vcc_lo, s0, v0 ; GFX10-NEXT: v_add_co_u32_e64 v6, vcc_lo, s0, v0
; GFX10-NEXT: v_add3_u32 v1, v2, v1, v3 ; GFX10-NEXT: v_add3_u32 v1, v1, v2, v3
; GFX10-NEXT: v_mov_b32_e32 v5, s3 ; GFX10-NEXT: v_mov_b32_e32 v5, s3
; GFX10-NEXT: v_mov_b32_e32 v4, s2 ; GFX10-NEXT: v_mov_b32_e32 v4, s2
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: global_load_dwordx2 v[2:3], v[6:7], off ; GFX10-NEXT: global_load_dwordx2 v[2:3], v[6:7], off
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX10-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
; GFX10-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX10-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
; GFX10-NEXT: global_store_dwordx2 v[6:7], v[4:5], off ; GFX10-NEXT: global_store_dwordx2 v[6:7], v[4:5], off
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Lines; GFX7-NEXT: s_endpgm
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
ret void ret void
} }
define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(i32 addrspace(1)* inreg %ptr, i32 inreg %soffset) { define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(i32 addrspace(1)* inreg %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_store_sgpr_ptr_sgpr_offset: ; GFX6-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v0, 4, s4 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, 4
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mul_i32 s3, s4, 4 ; GFX6-NEXT: s_mul_i32 s3, s4, 4
; GFX6-NEXT: s_mul_i32 s6, s4, 0 ; GFX6-NEXT: s_mul_i32 s5, s5, 4
; GFX6-NEXT: s_mul_i32 s4, s5, 4 ; GFX6-NEXT: s_mul_i32 s4, s4, 0
; GFX6-NEXT: s_add_i32 s6, s6, s4 ; GFX6-NEXT: s_add_i32 s5, s5, s4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s6, v0 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, s5, v0
; GFX6-NEXT: v_mov_b32_e32 v0, s3 ; GFX6-NEXT: v_mov_b32_e32 v0, s3
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: v_mov_b32_e32 v2, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_sgpr_ptr_sgpr_offset: ; GFX7-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v0, 4, s4 ; GFX7-NEXT: v_mul_hi_u32 v0, s4, 4
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mul_i32 s3, s4, 4 ; GFX7-NEXT: s_mul_i32 s3, s4, 4
; GFX7-NEXT: s_mul_i32 s6, s4, 0 ; GFX7-NEXT: s_mul_i32 s5, s5, 4
; GFX7-NEXT: s_mul_i32 s4, s5, 4 ; GFX7-NEXT: s_mul_i32 s4, s4, 0
; GFX7-NEXT: s_add_i32 s6, s6, s4 ; GFX7-NEXT: s_add_i32 s5, s5, s4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: v_add_i32_e32 v1, vcc, s6, v0 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, s5, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s3 ; GFX7-NEXT: v_mov_b32_e32 v0, s3
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %soffset %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %soffset
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
ret void ret void
} }
define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset(i32 addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset(i32 addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset: ; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX6-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX6-NEXT: s_mul_i32 s2, s0, 4 ; GFX6-NEXT: s_mul_i32 s2, s0, 4
; GFX6-NEXT: s_mul_i32 s3, s0, 0 ; GFX6-NEXT: s_mul_i32 s1, s1, 4
; GFX6-NEXT: s_mul_i32 s0, s1, 4 ; GFX6-NEXT: s_mul_i32 s0, s0, 0
; GFX6-NEXT: s_add_i32 s3, s3, s0 ; GFX6-NEXT: s_add_i32 s1, s1, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_mov_b32_e32 v2, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[4:5], 0 ; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset: ; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX7-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX7-NEXT: s_mul_i32 s2, s0, 4 ; GFX7-NEXT: s_mul_i32 s2, s0, 4
; GFX7-NEXT: s_mul_i32 s3, s0, 0 ; GFX7-NEXT: s_mul_i32 s1, s1, 4
; GFX7-NEXT: s_mul_i32 s0, s1, 4 ; GFX7-NEXT: s_mul_i32 s0, s0, 0
; GFX7-NEXT: s_add_i32 s3, s3, s0 ; GFX7-NEXT: s_add_i32 s1, s1, s0
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s3, v2 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %soffset %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %soffset
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
ret void ret void
} }
define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset_offset256(i32 addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset_offset256(i32 addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256: ; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX6-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX6-NEXT: s_mul_i32 s2, s0, 4 ; GFX6-NEXT: s_mul_i32 s2, s0, 4
; GFX6-NEXT: s_mul_i32 s3, s0, 0 ; GFX6-NEXT: s_mul_i32 s1, s1, 4
; GFX6-NEXT: s_mul_i32 s0, s1, 4 ; GFX6-NEXT: s_mul_i32 s0, s0, 0
; GFX6-NEXT: s_add_i32 s3, s3, s0 ; GFX6-NEXT: s_add_i32 s1, s1, s0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s3, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_mov_b32_e32 v2, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[4:5], 0 ; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:1024 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:1024
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256: ; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX7-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX7-NEXT: s_mul_i32 s2, s0, 4 ; GFX7-NEXT: s_mul_i32 s2, s0, 4
; GFX7-NEXT: s_mul_i32 s3, s0, 0 ; GFX7-NEXT: s_mul_i32 s1, s1, 4
; GFX7-NEXT: s_mul_i32 s0, s1, 4 ; GFX7-NEXT: s_mul_i32 s0, s0, 0
; GFX7-NEXT: s_add_i32 s3, s3, s0 ; GFX7-NEXT: s_add_i32 s1, s1, s0
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s3, v2 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:1024 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64 offset:1024
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
%gep0 = getelementptr i32, i32 addrspace(1)* %ptr, i32 %soffset %gep0 = getelementptr i32, i32 addrspace(1)* %ptr, i32 %soffset
%gep1 = getelementptr i32, i32 addrspace(1)* %gep0, i32 256 %gep1 = getelementptr i32, i32 addrspace(1)* %gep0, i32 256
store i32 0, i32 addrspace(1)* %gep1 store i32 0, i32 addrspace(1)* %gep1
ret void ret void
} }
define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset256_offset(i32 addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset256_offset(i32 addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset: ; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s1, 0 ; GFX6-NEXT: s_mov_b32 s1, 0
; GFX6-NEXT: s_movk_i32 s0, 0x400 ; GFX6-NEXT: s_movk_i32 s0, 0x400
; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x200000
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_mul_hi_u32 v2, 4, s2 ; GFX6-NEXT: v_mul_hi_u32 v2, s2, 4
; GFX6-NEXT: s_mul_i32 s0, s2, 4 ; GFX6-NEXT: s_mul_i32 s0, s2, 4
; GFX6-NEXT: s_mul_i32 s4, s2, 0 ; GFX6-NEXT: s_mul_i32 s3, s3, 4
; GFX6-NEXT: s_mul_i32 s2, s3, 4 ; GFX6-NEXT: s_mul_i32 s2, s2, 0
; GFX6-NEXT: s_add_i32 s4, s4, s2 ; GFX6-NEXT: s_add_i32 s3, s3, s2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s4, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, s3, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s2, s1 ; GFX6-NEXT: s_mov_b32 s2, s1
; GFX6-NEXT: v_mov_b32_e32 v2, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b64 s[0:1], 0 ; GFX6-NEXT: s_mov_b64 s[0:1], 0
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset: ; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s1, 0 ; GFX7-NEXT: s_mov_b32 s1, 0
; GFX7-NEXT: s_movk_i32 s0, 0x400 ; GFX7-NEXT: s_movk_i32 s0, 0x400
; GFX7-NEXT: v_mov_b32_e32 v3, s1 ; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x200000
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX7-NEXT: v_mul_hi_u32 v2, 4, s2 ; GFX7-NEXT: v_mul_hi_u32 v2, s2, 4
; GFX7-NEXT: s_mul_i32 s0, s2, 4 ; GFX7-NEXT: s_mul_i32 s0, s2, 4
; GFX7-NEXT: s_mul_i32 s4, s2, 0 ; GFX7-NEXT: s_mul_i32 s3, s3, 4
; GFX7-NEXT: s_mul_i32 s2, s3, 4 ; GFX7-NEXT: s_mul_i32 s2, s2, 0
; GFX7-NEXT: s_add_i32 s4, s4, s2 ; GFX7-NEXT: s_add_i32 s3, s3, s2
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s4, v2 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s3, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-NEXT: s_mov_b32 s2, s1 ; GFX7-NEXT: s_mov_b32 s2, s1
; GFX7-NEXT: v_mov_b32_e32 v2, 0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
%gep0 = getelementptr i32, i32 addrspace(1)* %ptr, i32 256 %gep0 = getelementptr i32, i32 addrspace(1)* %ptr, i32 256
%gep1 = getelementptr i32, i32 addrspace(1)* %gep0, i32 %soffset %gep1 = getelementptr i32, i32 addrspace(1)* %gep0, i32 %soffset
store i32 0, i32 addrspace(1)* %gep1 store i32 0, i32 addrspace(1)* %gep1
ret void ret void
} }
define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset(i32 addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset(i32 addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_store_sgpr_ptr_vgpr_offset: ; GFX6-LABEL: mubuf_store_sgpr_ptr_vgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX6-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX6-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX6-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_sgpr_ptr_vgpr_offset: ; GFX7-LABEL: mubuf_store_sgpr_ptr_vgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX7-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX7-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX7-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX7-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX7-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX7-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX7-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %voffset %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 %voffset
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
ret void ret void
} }
define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset_offset4095(i32 addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset_offset4095(i32 addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095: ; GFX6-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX6-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX6-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX6-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc ; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[0:3], s4 addr64 ; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[0:3], s4 addr64
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095: ; GFX7-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX7-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX7-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX7-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX7-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX7-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX7-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX7-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc ; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
; GFX7-NEXT: buffer_store_dword v0, v[1:2], s[0:3], s4 addr64 ; GFX7-NEXT: buffer_store_dword v0, v[1:2], s[0:3], s4 addr64
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
%gep0 = getelementptr i32, i32 addrspace(1)* %ptr, i32 %voffset %gep0 = getelementptr i32, i32 addrspace(1)* %ptr, i32 %voffset
%gep1 = getelementptr i32, i32 addrspace(1)* %gep0, i32 4095 %gep1 = getelementptr i32, i32 addrspace(1)* %gep0, i32 4095
store i32 0, i32 addrspace(1)* %gep1 store i32 0, i32 addrspace(1)* %gep1
ret void ret void
} }
define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4095_vgpr_offset(i32 addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4095_vgpr_offset(i32 addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset: ; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX6-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX6-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX6-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX6-NEXT: s_add_u32 s4, s2, 0x3ffc ; GFX6-NEXT: s_add_u32 s4, s2, 0x3ffc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX6-NEXT: s_addc_u32 s5, s3, 0 ; GFX6-NEXT: s_addc_u32 s5, s3, 0
; GFX6-NEXT: v_mov_b32_e32 v0, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset: ; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX7-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX7-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX7-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX7-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX7-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX7-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX7-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX7-NEXT: s_add_u32 s4, s2, 0x3ffc ; GFX7-NEXT: s_add_u32 s4, s2, 0x3ffc
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX7-NEXT: s_addc_u32 s5, s3, 0 ; GFX7-NEXT: s_addc_u32 s5, s3, 0
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
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} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(float addrspace(1)* inreg %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(float addrspace(1)* inreg %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_sgpr_offset: ; GFX6-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v0, 4, s2 ; GFX6-NEXT: v_mul_hi_u32 v0, s2, 4
; GFX6-NEXT: s_mul_i32 s4, s2, 0 ; GFX6-NEXT: s_mul_i32 s4, s2, 0
; GFX6-NEXT: s_mul_i32 s3, s3, 4 ; GFX6-NEXT: s_mul_i32 s3, s3, 4
; GFX6-NEXT: s_add_i32 s4, s4, s3 ; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_mul_i32 s2, s2, 4 ; GFX6-NEXT: s_mul_i32 s2, s2, 4
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s4, v0 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, s3, v0
; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_sgpr_offset: ; GFX7-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v0, 4, s2 ; GFX7-NEXT: v_mul_hi_u32 v0, s2, 4
; GFX7-NEXT: s_mul_i32 s4, s2, 0 ; GFX7-NEXT: s_mul_i32 s4, s2, 0
; GFX7-NEXT: s_mul_i32 s3, s3, 4 ; GFX7-NEXT: s_mul_i32 s3, s3, 4
; GFX7-NEXT: s_add_i32 s4, s4, s3 ; GFX7-NEXT: s_add_i32 s3, s3, s4
; GFX7-NEXT: s_mul_i32 s2, s2, 4 ; GFX7-NEXT: s_mul_i32 s2, s2, 4
; GFX7-NEXT: v_add_i32_e32 v1, vcc, s4, v0 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, s3, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset %gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset
%val = load float, float addrspace(1)* %gep %val = load float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset(float addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset(float addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset: ; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX6-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX6-NEXT: s_mul_i32 s2, s0, 0 ; GFX6-NEXT: s_mul_i32 s2, s0, 0
; GFX6-NEXT: s_mul_i32 s1, s1, 4 ; GFX6-NEXT: s_mul_i32 s1, s1, 4
; GFX6-NEXT: s_add_i32 s2, s2, s1 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; GFX6-NEXT: s_mul_i32 s0, s0, 4 ; GFX6-NEXT: s_mul_i32 s0, s0, 4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b64 s[0:1], 0 ; GFX6-NEXT: s_mov_b64 s[0:1], 0
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset: ; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX7-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX7-NEXT: s_mul_i32 s2, s0, 0 ; GFX7-NEXT: s_mul_i32 s2, s0, 0
; GFX7-NEXT: s_mul_i32 s1, s1, 4 ; GFX7-NEXT: s_mul_i32 s1, s1, 4
; GFX7-NEXT: s_add_i32 s2, s2, s1 ; GFX7-NEXT: s_add_i32 s1, s1, s2
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; GFX7-NEXT: s_mul_i32 s0, s0, 4 ; GFX7-NEXT: s_mul_i32 s0, s0, 4
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset %gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset
%val = load float, float addrspace(1)* %gep %val = load float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset_offset256(float addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset_offset256(float addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256: ; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX6-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX6-NEXT: s_mul_i32 s2, s0, 0 ; GFX6-NEXT: s_mul_i32 s2, s0, 0
; GFX6-NEXT: s_mul_i32 s1, s1, 4 ; GFX6-NEXT: s_mul_i32 s1, s1, 4
; GFX6-NEXT: s_add_i32 s2, s2, s1 ; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; GFX6-NEXT: s_mul_i32 s0, s0, 4 ; GFX6-NEXT: s_mul_i32 s0, s0, 4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b64 s[0:1], 0 ; GFX6-NEXT: s_mov_b64 s[0:1], 0
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256: ; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v2, 4, s0 ; GFX7-NEXT: v_mul_hi_u32 v2, s0, 4
; GFX7-NEXT: s_mul_i32 s2, s0, 0 ; GFX7-NEXT: s_mul_i32 s2, s0, 0
; GFX7-NEXT: s_mul_i32 s1, s1, 4 ; GFX7-NEXT: s_mul_i32 s1, s1, 4
; GFX7-NEXT: s_add_i32 s2, s2, s1 ; GFX7-NEXT: s_add_i32 s1, s1, s2
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s2, v2
; GFX7-NEXT: s_mul_i32 s0, s0, 4 ; GFX7-NEXT: s_mul_i32 s0, s0, 4
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s1, v2
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %soffset %gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %soffset
%gep1 = getelementptr float, float addrspace(1)* %gep0, i32 256 %gep1 = getelementptr float, float addrspace(1)* %gep0, i32 256
%val = load float, float addrspace(1)* %gep1 %val = load float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset256_offset(float addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset256_offset(float addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset: ; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: v_mul_hi_u32 v4, 4, s0 ; GFX6-NEXT: v_mul_hi_u32 v4, s0, 4
; GFX6-NEXT: s_movk_i32 s4, 0x400 ; GFX6-NEXT: s_movk_i32 s4, 0x400
; GFX6-NEXT: s_mov_b32 s5, 0 ; GFX6-NEXT: s_mov_b32 s5, 0
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: s_mul_i32 s2, s0, 0 ; GFX6-NEXT: s_mul_i32 s2, s0, 0
; GFX6-NEXT: s_mul_i32 s1, s1, 4 ; GFX6-NEXT: s_mul_i32 s1, s1, 4
; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: s_add_i32 s2, s2, s1
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s2, v4
; GFX6-NEXT: s_mul_i32 s0, s0, 4 ; GFX6-NEXT: s_mul_i32 s0, s0, 4
; GFX6-NEXT: v_add_i32_e32 v2, vcc, s1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, s5 ; GFX6-NEXT: s_mov_b32 s2, s5
; GFX6-NEXT: s_mov_b64 s[0:1], 0 ; GFX6-NEXT: s_mov_b64 s[0:1], 0
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset: ; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: v_mul_hi_u32 v4, 4, s0 ; GFX7-NEXT: v_mul_hi_u32 v4, s0, 4
; GFX7-NEXT: s_movk_i32 s4, 0x400 ; GFX7-NEXT: s_movk_i32 s4, 0x400
; GFX7-NEXT: s_mov_b32 s5, 0 ; GFX7-NEXT: s_mov_b32 s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s4 ; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_mul_i32 s2, s0, 0 ; GFX7-NEXT: s_mul_i32 s2, s0, 0
; GFX7-NEXT: s_mul_i32 s1, s1, 4 ; GFX7-NEXT: s_mul_i32 s1, s1, 4
; GFX7-NEXT: s_add_i32 s1, s1, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s5 ; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX7-NEXT: s_add_i32 s2, s2, s1
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s2, v4
; GFX7-NEXT: s_mul_i32 s0, s0, 4 ; GFX7-NEXT: s_mul_i32 s0, s0, 4
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s1, v4
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s5 ; GFX7-NEXT: s_mov_b32 s2, s5
; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 256 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 256
%gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %soffset %gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %soffset
%val = load float, float addrspace(1)* %gep1 %val = load float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset: ; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX6-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX6-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX6-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset: ; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_mul_lo_u32 v3, 4, v1 ; GFX7-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX7-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX7-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX7-NEXT: v_mul_lo_u32 v1, 4, v0 ; GFX7-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX7-NEXT: v_mul_hi_u32 v0, 4, v0 ; GFX7-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %voffset %gep = getelementptr float, float addrspace(1)* %ptr, i32 %voffset
%val = load float, float addrspace(1)* %gep %val = load float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset_offset4095(float addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset_offset4095(float addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095: ; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX6-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX6-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX6-NEXT: v_mul_lo_u32 v0, 4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc ; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[1:2], s[0:3], s4 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095: ; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX7-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX7-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX7-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX7-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX7-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX7-NEXT: v_mul_lo_u32 v0, 4, v0 ; GFX7-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc ; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[1:2], s[0:3], s4 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %voffset %gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %voffset
%gep1 = getelementptr float, float addrspace(1)* %gep0, i64 4095 %gep1 = getelementptr float, float addrspace(1)* %gep0, i64 4095
%val = load float, float addrspace(1)* %gep1 %val = load float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset: ; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX6-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX6-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX6-NEXT: v_mul_lo_u32 v0, 4, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX6-NEXT: s_add_u32 s0, s2, 0x3ffc ; GFX6-NEXT: s_add_u32 s0, s2, 0x3ffc
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_addc_u32 s1, s3, 0 ; GFX6-NEXT: s_addc_u32 s1, s3, 0
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset: ; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_mul_lo_u32 v2, 0, v0 ; GFX7-NEXT: v_mul_lo_u32 v2, v1, 4
; GFX7-NEXT: v_mul_lo_u32 v1, 4, v1 ; GFX7-NEXT: v_mul_lo_u32 v3, v0, 0
; GFX7-NEXT: v_mul_hi_u32 v3, 4, v0 ; GFX7-NEXT: v_mul_lo_u32 v1, v0, 4
; GFX7-NEXT: v_mul_lo_u32 v0, 4, v0 ; GFX7-NEXT: v_mul_hi_u32 v0, v0, 4
; GFX7-NEXT: s_add_u32 s0, s2, 0x3ffc ; GFX7-NEXT: s_add_u32 s0, s2, 0x3ffc
; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX7-NEXT: s_addc_u32 s1, s3, 0 ; GFX7-NEXT: s_addc_u32 s1, s3, 0
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v2, v0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[1:2], s[0:3], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 4095 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 4095
%gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %voffset %gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %voffset
%val = load float, float addrspace(1)* %gep1 %val = load float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
; define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4095(i32 addrspace(1)* inreg %ptr) { ; define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4095(i32 addrspace(1)* inreg %ptr) {
; %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4095 ; %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4095
; %result = atomicrmw add i32 addrspace(1)* %gep, i32 2 seq_cst ; %result = atomicrmw add i32 addrspace(1)* %gep, i32 2 seq_cst
; %cast = bitcast i32 %result to float ; %cast = bitcast i32 %result to float
; ret float %cast ; ret float %cast
; } ; }

llvm/test/CodeGen/X86/GlobalISel/add-ext.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
ret i8* %idx ret i8* %idx
} }
define i16* @gep16(i32 %i, i16* %x) { define i16* @gep16(i32 %i, i16* %x) {
; CHECK-LABEL: gep16: ; CHECK-LABEL: gep16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addl $-5, %edi ; CHECK-NEXT: addl $-5, %edi
; CHECK-NEXT: movslq %edi, %rax ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $2, %rcx ; CHECK-NEXT: imulq $2, %rax, %rax
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, -5 %add = add nsw i32 %i, -5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i16, i16* %x, i64 %ext %idx = getelementptr i16, i16* %x, i64 %ext
ret i16* %idx ret i16* %idx
} }
define i32* @gep32(i32 %i, i32* %x) { define i32* @gep32(i32 %i, i32* %x) {
; CHECK-LABEL: gep32: ; CHECK-LABEL: gep32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addl $5, %edi ; CHECK-NEXT: addl $5, %edi
; CHECK-NEXT: movslq %edi, %rax ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $4, %rcx ; CHECK-NEXT: imulq $4, %rax, %rax
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, 5 %add = add nsw i32 %i, 5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i32, i32* %x, i64 %ext %idx = getelementptr i32, i32* %x, i64 %ext
ret i32* %idx ret i32* %idx
} }
define i64* @gep64(i32 %i, i64* %x) { define i64* @gep64(i32 %i, i64* %x) {
; CHECK-LABEL: gep64: ; CHECK-LABEL: gep64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addl $-5, %edi ; CHECK-NEXT: addl $-5, %edi
; CHECK-NEXT: movslq %edi, %rax ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $8, %rcx ; CHECK-NEXT: imulq $8, %rax, %rax
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, -5 %add = add nsw i32 %i, -5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i64, i64* %x, i64 %ext %idx = getelementptr i64, i64* %x, i64 %ext
ret i64* %idx ret i64* %idx
} }
; LEA can't scale by 16, but the adds can still be combined into an LEA. ; LEA can't scale by 16, but the adds can still be combined into an LEA.
define i128* @gep128(i32 %i, i128* %x) { define i128* @gep128(i32 %i, i128* %x) {
; CHECK-LABEL: gep128: ; CHECK-LABEL: gep128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addl $5, %edi ; CHECK-NEXT: addl $5, %edi
; CHECK-NEXT: movslq %edi, %rax ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq $16, %rcx ; CHECK-NEXT: imulq $16, %rax, %rax
; CHECK-NEXT: imulq %rax, %rcx ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: leaq (%rsi,%rcx), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add = add nsw i32 %i, 5 %add = add nsw i32 %i, 5
%ext = sext i32 %add to i64 %ext = sext i32 %add to i64
%idx = getelementptr i128, i128* %x, i64 %ext %idx = getelementptr i128, i128* %x, i64 %ext
ret i128* %idx ret i128* %idx
} }
; A bigger win can be achieved when there is more than one use of the ; A bigger win can be achieved when there is more than one use of the
; sign extended value. In this case, we can eliminate sign extension ; sign extended value. In this case, we can eliminate sign extension
; instructions plus use more efficient addressing modes for memory ops. ; instructions plus use more efficient addressing modes for memory ops.
define void @PR20134(i32* %a, i32 %i) { define void @PR20134(i32* %a, i32 %i) {
; CHECK-LABEL: PR20134: ; CHECK-LABEL: PR20134:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: leal 1(%rsi), %eax ; CHECK-NEXT: leal 1(%rsi), %eax
; CHECK-NEXT: cltq ; CHECK-NEXT: cltq
; CHECK-NEXT: movq $4, %rcx ; CHECK-NEXT: imulq $4, %rax, %rax
; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: leal 2(%rsi), %edx ; CHECK-NEXT: leal 2(%rsi), %ecx
; CHECK-NEXT: movslq %edx, %rdx ; CHECK-NEXT: movslq %ecx, %rcx
; CHECK-NEXT: imulq %rcx, %rdx ; CHECK-NEXT: imulq $4, %rcx, %rcx
; CHECK-NEXT: addq %rdi, %rdx ; CHECK-NEXT: addq %rdi, %rcx
; CHECK-NEXT: movl (%rdx), %edx ; CHECK-NEXT: movl (%rcx), %ecx
; CHECK-NEXT: addl (%rax), %edx ; CHECK-NEXT: addl (%rax), %ecx
; CHECK-NEXT: movslq %esi, %rax ; CHECK-NEXT: movslq %esi, %rax
; CHECK-NEXT: imulq %rcx, %rax ; CHECK-NEXT: imulq $4, %rax, %rax
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: movl %edx, (%rax) ; CHECK-NEXT: movl %ecx, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add1 = add nsw i32 %i, 1 %add1 = add nsw i32 %i, 1
%idx1 = sext i32 %add1 to i64 %idx1 = sext i32 %add1 to i64
%gep1 = getelementptr i32, i32* %a, i64 %idx1 %gep1 = getelementptr i32, i32* %a, i64 %idx1
%load1 = load i32, i32* %gep1, align 4 %load1 = load i32, i32* %gep1, align 4
%add2 = add nsw i32 %i, 2 %add2 = add nsw i32 %i, 2
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; The same as @PR20134 but sign extension is replaced with zero extension ; The same as @PR20134 but sign extension is replaced with zero extension
define void @PR20134_zext(i32* %a, i32 %i) { define void @PR20134_zext(i32* %a, i32 %i) {
; CHECK-LABEL: PR20134_zext: ; CHECK-LABEL: PR20134_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: leal 1(%rsi), %eax ; CHECK-NEXT: leal 1(%rsi), %eax
; CHECK-NEXT: movl %eax, %eax ; CHECK-NEXT: movl %eax, %eax
; CHECK-NEXT: movq $4, %rcx ; CHECK-NEXT: imulq $4, %rax, %rax
; CHECK-NEXT: imulq %rcx, %rax
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: leal 2(%rsi), %edx ; CHECK-NEXT: leal 2(%rsi), %ecx
; CHECK-NEXT: movl %edx, %edx ; CHECK-NEXT: movl %ecx, %ecx
; CHECK-NEXT: imulq %rcx, %rdx ; CHECK-NEXT: imulq $4, %rcx, %rcx
; CHECK-NEXT: addq %rdi, %rdx ; CHECK-NEXT: addq %rdi, %rcx
; CHECK-NEXT: movl (%rdx), %edx ; CHECK-NEXT: movl (%rcx), %ecx
; CHECK-NEXT: addl (%rax), %edx ; CHECK-NEXT: addl (%rax), %ecx
; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: imulq %rcx, %rax ; CHECK-NEXT: imulq $4, %rax, %rax
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: movl %edx, (%rax) ; CHECK-NEXT: movl %ecx, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%add1 = add nuw i32 %i, 1 %add1 = add nuw i32 %i, 1
%idx1 = zext i32 %add1 to i64 %idx1 = zext i32 %add1 to i64
%gep1 = getelementptr i32, i32* %a, i64 %idx1 %gep1 = getelementptr i32, i32* %a, i64 %idx1
%load1 = load i32, i32* %gep1, align 4 %load1 = load i32, i32* %gep1, align 4
%add2 = add nuw i32 %i, 2 %add2 = add nuw i32 %i, 2
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llvm/test/CodeGen/X86/GlobalISel/ptr-add.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64_GISEL ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64_GISEL
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
define i32* @test_gep_i8(i32 *%arr, i8 %ind) { define i32* @test_gep_i8(i32 *%arr, i8 %ind) {
; X64_GISEL-LABEL: test_gep_i8: ; X64_GISEL-LABEL: test_gep_i8:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi ; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi
; X64_GISEL-NEXT: shlq $56, %rsi ; X64_GISEL-NEXT: shlq $56, %rsi
; X64_GISEL-NEXT: sarq $56, %rsi ; X64_GISEL-NEXT: sarq $56, %rsi
; X64_GISEL-NEXT: movq $4, %rax ; X64_GISEL-NEXT: imulq $4, %rsi, %rax
; X64_GISEL-NEXT: imulq %rsi, %rax
; X64_GISEL-NEXT: addq %rdi, %rax ; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i8: ; X64-LABEL: test_gep_i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: # kill: def $esi killed $esi def $rsi ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movsbq %sil, %rax ; X64-NEXT: movsbq %sil, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax
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} }
define i32* @test_gep_i16(i32 *%arr, i16 %ind) { define i32* @test_gep_i16(i32 *%arr, i16 %ind) {
; X64_GISEL-LABEL: test_gep_i16: ; X64_GISEL-LABEL: test_gep_i16:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi ; X64_GISEL-NEXT: # kill: def $esi killed $esi def $rsi
; X64_GISEL-NEXT: shlq $48, %rsi ; X64_GISEL-NEXT: shlq $48, %rsi
; X64_GISEL-NEXT: sarq $48, %rsi ; X64_GISEL-NEXT: sarq $48, %rsi
; X64_GISEL-NEXT: movq $4, %rax ; X64_GISEL-NEXT: imulq $4, %rsi, %rax
; X64_GISEL-NEXT: imulq %rsi, %rax
; X64_GISEL-NEXT: addq %rdi, %rax ; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i16: ; X64-LABEL: test_gep_i16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: # kill: def $esi killed $esi def $rsi ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: movswq %si, %rax ; X64-NEXT: movswq %si, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax
Show All 16 Lines; X64-NEXT: retq
%arrayidx = getelementptr i32, i32* %arr, i16 20 %arrayidx = getelementptr i32, i32* %arr, i16 20
ret i32* %arrayidx ret i32* %arrayidx
} }
define i32* @test_gep_i32(i32 *%arr, i32 %ind) { define i32* @test_gep_i32(i32 *%arr, i32 %ind) {
; X64_GISEL-LABEL: test_gep_i32: ; X64_GISEL-LABEL: test_gep_i32:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: movslq %esi, %rax ; X64_GISEL-NEXT: movslq %esi, %rax
; X64_GISEL-NEXT: movq $4, %rcx ; X64_GISEL-NEXT: imulq $4, %rax, %rax
; X64_GISEL-NEXT: imulq %rax, %rcx ; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: leaq (%rdi,%rcx), %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i32: ; X64-LABEL: test_gep_i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movslq %esi, %rax ; X64-NEXT: movslq %esi, %rax
; X64-NEXT: leaq (%rdi,%rax,4), %rax ; X64-NEXT: leaq (%rdi,%rax,4), %rax
; X64-NEXT: retq ; X64-NEXT: retq
%arrayidx = getelementptr i32, i32* %arr, i32 %ind %arrayidx = getelementptr i32, i32* %arr, i32 %ind
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; X64-NEXT: retq ; X64-NEXT: retq
%arrayidx = getelementptr i32, i32* %arr, i32 5 %arrayidx = getelementptr i32, i32* %arr, i32 5
ret i32* %arrayidx ret i32* %arrayidx
} }
define i32* @test_gep_i64(i32 *%arr, i64 %ind) { define i32* @test_gep_i64(i32 *%arr, i64 %ind) {
; X64_GISEL-LABEL: test_gep_i64: ; X64_GISEL-LABEL: test_gep_i64:
; X64_GISEL: # %bb.0: ; X64_GISEL: # %bb.0:
; X64_GISEL-NEXT: movq $4, %rax ; X64_GISEL-NEXT: imulq $4, %rsi, %rax
; X64_GISEL-NEXT: imulq %rsi, %rax
; X64_GISEL-NEXT: addq %rdi, %rax ; X64_GISEL-NEXT: addq %rdi, %rax
; X64_GISEL-NEXT: retq ; X64_GISEL-NEXT: retq
; ;
; X64-LABEL: test_gep_i64: ; X64-LABEL: test_gep_i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: leaq (%rdi,%rsi,4), %rax ; X64-NEXT: leaq (%rdi,%rsi,4), %rax
; X64-NEXT: retq ; X64-NEXT: retq
%arrayidx = getelementptr i32, i32* %arr, i64 %ind %arrayidx = getelementptr i32, i32* %arr, i64 %ind
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