AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics.

[mshivama]

Summary

This is a very first patch that I am sending to phabricator, I wanted to myself get used to the process, and hence did a minor clean-up around ISel for Intrinsics. Kindly request you to review the patch.

[mshivama]

Hello Matt,

Thanks for reviewing the code and approving it. At this point in time, I do not have LLVM commit access. It would be great if you commit this patch on behalf of me.

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

private:
   bool selectG_INSERT(MachineInstr &I) const;
 
   bool selectInterpP1F16(MachineInstr &MI) const;
   bool selectG_INTRINSIC(MachineInstr &I) const;
 
   std::tuple<Register, unsigned, unsigned>
   splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
 
+  bool selectEndCfIntrinsic(MachineInstr &MI) const;
   bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
 
   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
   bool selectG_ICMP(MachineInstr &I) const;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (Overflow != 0) {
     }
 
     B.setInsertPt(OldMBB, OldInsPt);
   }
 
   return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset);
 }
 
+bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
+  // FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
+  // SelectionDAG uses for wave32 vs wave64.
+  MachineBasicBlock *BB = MI.getParent();
+  BuildMI(*BB, &MI, MI.getDebugLoc(), TII.get(AMDGPU::SI_END_CF))
+      .add(MI.getOperand(1));
+
+  Register Reg = MI.getOperand(1).getReg();
+  MI.eraseFromParent();
+
+  if (!MRI->getRegClassOrNull(Reg))
+    MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
+  return true;
+}
+
 bool AMDGPUInstructionSelector::selectStoreIntrinsic(MachineInstr &MI,
                                                      bool IsFormat) const {
   MachineIRBuilder B(MI);
   MachineFunction &MF = B.getMF();
   Register VData = MI.getOperand(1).getReg();
   LLT Ty = MRI->getType(VData);
 
   int Size = Ty.getSizeInBits();
BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg())
     .cloneMemRefs(MI);
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
     MachineInstr &I) const {
-  MachineBasicBlock *BB = I.getParent();
   unsigned IntrinsicID = I.getIntrinsicID();
   switch (IntrinsicID) {
-  case Intrinsic::amdgcn_end_cf: {
-    // FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
-    // SelectionDAG uses for wave32 vs wave64.
-    BuildMI(*BB, &I, I.getDebugLoc(),
-            TII.get(AMDGPU::SI_END_CF))
-      .add(I.getOperand(1));
-
-    Register Reg = I.getOperand(1).getReg();
-    I.eraseFromParent();
-
-    if (!MRI->getRegClassOrNull(Reg))
-      MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
-    return true;
-  }
+  case Intrinsic::amdgcn_end_cf:
+    return selectEndCfIntrinsic(I);
   case Intrinsic::amdgcn_raw_buffer_store:
     return selectStoreIntrinsic(I, false);
   case Intrinsic::amdgcn_raw_buffer_store_format:
     return selectStoreIntrinsic(I, true);
   case Intrinsic::amdgcn_ds_ordered_add:
   case Intrinsic::amdgcn_ds_ordered_swap:
     return selectDSOrderedIntrinsic(I, IntrinsicID);
   case Intrinsic::amdgcn_ds_gws_init: