[AMDGPU] Fix GCN regpressure trackers for INLINEASM instructions

[vpykhtin]

Summary

Replace iteration over defs() with operands() as INLINEASM instruction isn't compatible with defs() - it has completly different order of operands: asm string, flags and pairs of flags:operand. defs() assumes all def operands go sequentally from the beginning of operands.

How LLVM could work all these years? Should an assert not using on INLINEASM in defs be added?

Not sure how to test this.

[rampitec]

LGTM. Thanks.

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
   auto AtMIPressure = CurPressure;
   for (const auto &U : RegUses) {
     auto LiveMask = LiveRegs[U.RegUnit];
     AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
   }
   // update max pressure
   MaxPressure = max(AtMIPressure, MaxPressure);
 
-  for (const auto &MO : MI.defs()) {
-    if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
+  for (const auto &MO : MI.operands()) {
+    if (!MO.isReg() || !MO.isDef() ||
+        !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
       continue;
 
     auto Reg = MO.getReg();
     auto I = LiveRegs.find(Reg);
     if (I == LiveRegs.end())
       continue;
     auto &LiveMask = I->second;
     auto PrevMask = LiveMask;
bool GCNDownwardRPTracker::advanceBeforeNext() {
 
   return true;
 }
 
 void GCNDownwardRPTracker::advanceToNext() {
   LastTrackedMI = &*NextMI++;
 
   // Add new registers or mask bits.
-  for (const auto &MO : LastTrackedMI->defs()) {
-    if (!MO.isReg())
+  for (const auto &MO : LastTrackedMI->operands()) {
+    if (!MO.isReg() || !MO.isDef())
       continue;
     Register Reg = MO.getReg();
     if (!Register::isVirtualRegister(Reg))
       continue;
     auto &LiveMask = LiveRegs[Reg];
     auto PrevMask = LiveMask;
     LiveMask |= getDefRegMask(MO, *MRI);
     CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);