[CodeGen] Make use of MachineInstrBuilder::getReg

[merge_guards_bot]

Unit tests: pass. 62130 tests passed, 0 failed and 808 were skipped.

clang-tidy: fail. clang-tidy found 0 errors and 3 warnings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp

 MachineInstrBuilder
 CSEMIRBuilder::generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
                                         MachineInstrBuilder &MIB) {
   assert(checkCopyToDefsPossible(DstOps) &&
          "Impossible return a single MIB with copies to multiple defs");
   if (DstOps.size() == 1) {
     const DstOp &Op = DstOps[0];
     if (Op.getDstOpKind() == DstOp::DstType::Ty_Reg)
-      return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());
+      return buildCopy(Op.getReg(), MIB.getReg(0));
   }
   return MIB;
 }
 
 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
                                               ArrayRef<DstOp> DstOps,
                                               ArrayRef<SrcOp> SrcOps,
                                               Optional<unsigned> Flag) {

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Register CallLowering::ValueHandler::extendRegister(Register ValReg,
   default: break;
   case CCValAssign::Full:
   case CCValAssign::BCvt:
     // FIXME: bitconverting between vector types may or may not be a
     // nop in big-endian situations.
     return ValReg;
   case CCValAssign::AExt: {
     auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
-    return MIB->getOperand(0).getReg();
+    return MIB.getReg(0);
   }
   case CCValAssign::SExt: {
     Register NewReg = MRI.createGenericVirtualRegister(LocTy);
     MIRBuilder.buildSExt(NewReg, ValReg);
     return NewReg;
   }
   case CCValAssign::ZExt: {
     Register NewReg = MRI.createGenericVirtualRegister(LocTy);
     MIRBuilder.buildZExt(NewReg, ValReg);
     return NewReg;
   }
   }
   llvm_unreachable("unable to extend register");
 }
 
 void CallLowering::ValueHandler::anchor() {}

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

if (CI->getBitWidth() != PreferredVecIdxWidth) {
       auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
       Idx = getOrCreateVReg(*NewIdxCI);
     }
   }
   if (!Idx)
     Idx = getOrCreateVReg(*U.getOperand(1));
   if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
     const LLT &VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
-    Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
+    Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0);
   }
   MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
   return true;
 }
 
 bool IRTranslator::translateShuffleVector(const User &U,
                                           MachineIRBuilder &MIRBuilder) {
   SmallVector<int, 8> Mask;

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case TargetOpcode::G_IMPLICIT_DEF: {
     // FIXME: add support for when SizeOp0 isn't an exact multiple of
     // NarrowSize.
     if (SizeOp0 % NarrowSize != 0)
       return UnableToLegalize;
     int NumParts = SizeOp0 / NarrowSize;
 
     SmallVector<Register, 2> DstRegs;
     for (int i = 0; i < NumParts; ++i)
       DstRegs.push_back(
-          MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
+          MIRBuilder.buildUndef(NarrowTy).getReg(0));
 
     Register DstReg = MI.getOperand(0).getReg();
     if(MRI.getType(DstReg).isVector())
       MIRBuilder.buildBuildVector(DstReg, DstRegs);
     else
       MIRBuilder.buildMerge(DstReg, DstRegs);
     MI.eraseFromParent();
     return Legalized;
case TargetOpcode::G_SEXT_INREG: {
     // So long as the new type has more bits than the bits we're extending we
     // don't need to break it apart.
     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
       Observer.changingInstr(MI);
       // We don't lose any non-extension bits by truncating the src and
       // sign-extending the dst.
       MachineOperand &MO1 = MI.getOperand(1);
       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
-      MO1.setReg(TruncMIB->getOperand(0).getReg());
+      MO1.setReg(TruncMIB.getReg(0));
 
       MachineOperand &MO2 = MI.getOperand(0);
       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
       MIRBuilder.buildSExt(MO2, DstExt);
       MO2.setReg(DstExt);
       Observer.changedInstr(MI);
       return Legalized;
for (int i = 0; i < NumParts; ++i) {
       SrcRegs.push_back(SrcReg);
     }
 
     // Explode the big arguments into smaller chunks.
     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1));
 
     Register AshrCstReg =
         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
-            ->getOperand(0)
-            .getReg();
+            .getReg(0);
     Register FullExtensionReg = 0;
     Register PartialExtensionReg = 0;
 
     // Do the operation on each small part.
     for (int i = 0; i < NumParts; ++i) {
       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
         DstRegs.push_back(SrcRegs[i]);
       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
         assert(PartialExtensionReg &&
                "Expected to visit partial extension before full");
         if (FullExtensionReg) {
           DstRegs.push_back(FullExtensionReg);
           continue;
         }
         DstRegs.push_back(
             MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
-                ->getOperand(0)
-                .getReg());
+                .getReg(0));
         FullExtensionReg = DstRegs.back();
       } else {
         DstRegs.push_back(
             MIRBuilder
                 .buildInstr(
                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
-                ->getOperand(0)
-                .getReg());
+                .getReg(0));
         PartialExtensionReg = DstRegs.back();
       }
     }
 
     // Gather the destination registers into the final destination.
     Register DstReg = MI.getOperand(0).getReg();
     MIRBuilder.buildMerge(DstReg, DstRegs);
     MI.eraseFromParent();
LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
   }
   }
 }
 
 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
                                      unsigned OpIdx, unsigned ExtOpcode) {
   MachineOperand &MO = MI.getOperand(OpIdx);
   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
-  MO.setReg(ExtB->getOperand(0).getReg());
+  MO.setReg(ExtB.getReg(0));
 }
 
 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
                                       unsigned OpIdx) {
   MachineOperand &MO = MI.getOperand(OpIdx);
   auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
-  MO.setReg(ExtB->getOperand(0).getReg());
+  MO.setReg(ExtB.getReg(0));
 }
 
 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
                                      unsigned OpIdx, unsigned TruncOpcode) {
   MachineOperand &MO = MI.getOperand(OpIdx);
   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
   MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
   for (unsigned I = 1; I != NumDst; ++I) {
     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
   }
 
   Observer.changingInstr(MI);
 
-  MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
+  MI.getOperand(NumDst).setReg(WideSrc.getReg(0));
   for (unsigned I = 0; I != NumDst; ++I)
     widenScalarDst(MI, WideTy, I);
 
   Observer.changedInstr(MI);
 
   return Legalized;
 }
 
case 128:
       break;
     default:
       llvm_unreachable("unexpected floating-point type");
     }
     ConstantFP &ZeroForNegation =
         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
     Register SubByReg = MI.getOperand(1).getReg();
-    Register ZeroReg = Zero->getOperand(0).getReg();
+    Register ZeroReg = Zero.getReg(0);
     MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_FSUB: {
     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
     // First, check if G_FNEG is marked as Lower. If so, we may
     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
   LLT Unused;
   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
                     Src1Regs, Src1LeftoverRegs))
     llvm_unreachable("inconsistent extractParts result");
 
   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
                                         {Src0Regs[I], Src1Regs[I]});
-    DstRegs.push_back(Inst->getOperand(0).getReg());
+    DstRegs.push_back(Inst.getReg(0));
   }
 
   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
     auto Inst = MIRBuilder.buildInstr(
       MI.getOpcode(),
       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
-    DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
+    DstLeftoverRegs.push_back(Inst.getReg(0));
   }
 
   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
               LeftoverTy, DstLeftoverRegs);
 
   MI.eraseFromParent();
   return Legalized;
 }
LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
   LLT Unused;
   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
                     Src2Regs, Src2LeftoverRegs))
     llvm_unreachable("inconsistent extractParts result");
 
   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
     auto Select = MIRBuilder.buildSelect(NarrowTy,
                                          CondReg, Src1Regs[I], Src2Regs[I]);
-    DstRegs.push_back(Select->getOperand(0).getReg());
+    DstRegs.push_back(Select.getReg(0));
   }
 
   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
     auto Select = MIRBuilder.buildSelect(
       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
-    DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
+    DstLeftoverRegs.push_back(Select.getReg(0));
   }
 
   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
               LeftoverTy, DstLeftoverRegs);
 
   MI.eraseFromParent();
   return Legalized;
 }
case TargetOpcode::G_CTLZ: {
     //
     // Ref: "Hacker's Delight" by Henry Warren
     Register Op = SrcReg;
     unsigned NewLen = PowerOf2Ceil(Len);
     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
       auto MIBOp =
           MIRBuilder.buildOr(Ty, Op, MIRBuilder.buildLShr(Ty, Op, MIBShiftAmt));
-      Op = MIBOp->getOperand(0).getReg();
+      Op = MIBOp.getReg(0);
     }
     auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op);
     MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(Ty, Len),
                         MIBPop);
     MI.eraseFromParent();
     return Legalized;
   }
   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
       MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
                           MIRBuilder.buildCTLZ(Ty, MIBTmp));
       MI.eraseFromParent();
       return Legalized;
     }
     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
-    MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
+    MI.getOperand(1).setReg(MIBTmp.getReg(0));
     return Legalized;
   }
   }
 }
 
 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
 // representation.
 LegalizerHelper::LegalizeResult

llvm/lib/CodeGen/MachineSSAUpdater.cpp

if (unsigned ConstVal = InsertedPHI->isConstantValuePHI()) {
     InsertedPHI->eraseFromParent();
     return ConstVal;
   }
 
   // If the client wants to know about all new instructions, tell it.
   if (InsertedPHIs) InsertedPHIs->push_back(InsertedPHI);
 
   LLVM_DEBUG(dbgs() << "  Inserted PHI: " << *InsertedPHI << "\n");
-  return InsertedPHI->getOperand(0).getReg();
+  return InsertedPHI.getReg(0);
 }
 
 static
 MachineBasicBlock *findCorrespondingPred(const MachineInstr *MI,
                                          MachineOperand *U) {
   for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
     if (&MI->getOperand(i) == U)
       return MI->getOperand(i+1).getMBB();

llvm/lib/Target/AArch64/AArch64CallLowering.cpp

void assignValueToReg(Register ValVReg, Register PhysReg,
     Register ExtReg = extendRegister(ValVReg, VA);
     MIRBuilder.buildCopy(PhysReg, ExtReg);
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
                             MachinePointerInfo &MPO, CCValAssign &VA) override {
     if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
       Size = VA.getLocVT().getSizeInBits() / 8;
       ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg)
-                    ->getOperand(0)
-                    .getReg();
+                    .getReg(0);
     }
     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
         MPO, MachineMemOperand::MOStore, Size, 1);
     MIRBuilder.buildStore(ValVReg, Addr, *MMO);
   }
 
   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
                  CCValAssign::LocInfo LocInfo,

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

static bool selectMergeValues(MachineInstrBuilder &MIB,
                               const ARMBaseInstrInfo &TII,
                               MachineRegisterInfo &MRI,
                               const TargetRegisterInfo &TRI,
                               const RegisterBankInfo &RBI) {
   assert(TII.getSubtarget().hasVFP2Base() && "Can't select merge without VFP");
 
   // We only support G_MERGE_VALUES as a way to stick together two scalar GPRs
   // into one DPR.
-  Register VReg0 = MIB->getOperand(0).getReg();
+  Register VReg0 = MIB.getReg(0);
   (void)VReg0;
   assert(MRI.getType(VReg0).getSizeInBits() == 64 &&
          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID &&
          "Unsupported operand for G_MERGE_VALUES");
-  Register VReg1 = MIB->getOperand(1).getReg();
+  Register VReg1 = MIB.getReg(1);
   (void)VReg1;
   assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
          "Unsupported operand for G_MERGE_VALUES");
-  Register VReg2 = MIB->getOperand(2).getReg();
+  Register VReg2 = MIB.getReg(2);
   (void)VReg2;
   assert(MRI.getType(VReg2).getSizeInBits() == 32 &&
          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID &&
          "Unsupported operand for G_MERGE_VALUES");
 
   MIB->setDesc(TII.get(ARM::VMOVDRR));
   MIB.add(predOps(ARMCC::AL));
 
   return true;
 }
 
 static bool selectUnmergeValues(MachineInstrBuilder &MIB,
                                 const ARMBaseInstrInfo &TII,
                                 MachineRegisterInfo &MRI,
                                 const TargetRegisterInfo &TRI,
                                 const RegisterBankInfo &RBI) {
   assert(TII.getSubtarget().hasVFP2Base() &&
          "Can't select unmerge without VFP");
 
   // We only support G_UNMERGE_VALUES as a way to break up one DPR into two
   // GPRs.
-  Register VReg0 = MIB->getOperand(0).getReg();
+  Register VReg0 = MIB.getReg(0);
   (void)VReg0;
   assert(MRI.getType(VReg0).getSizeInBits() == 32 &&
          RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID &&
          "Unsupported operand for G_UNMERGE_VALUES");
-  Register VReg1 = MIB->getOperand(1).getReg();
+  Register VReg1 = MIB.getReg(1);
   (void)VReg1;
   assert(MRI.getType(VReg1).getSizeInBits() == 32 &&
          RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID &&
          "Unsupported operand for G_UNMERGE_VALUES");
-  Register VReg2 = MIB->getOperand(2).getReg();
+  Register VReg2 = MIB.getReg(2);
   (void)VReg2;
   assert(MRI.getType(VReg2).getSizeInBits() == 64 &&
          RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID &&
          "Unsupported operand for G_UNMERGE_VALUES");
 
   MIB->setDesc(TII.get(ARM::VMOVRRD));
   MIB.add(predOps(ARMCC::AL));
 
bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
   return true;
 }
 
 bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
                                        MachineInstrBuilder &MIB,
                                        MachineRegisterInfo &MRI) const {
   const InsertInfo I(MIB);
 
-  auto ResReg = MIB->getOperand(0).getReg();
+  auto ResReg = MIB.getReg(0);
   if (!validReg(MRI, ResReg, 1, ARM::GPRRegBankID))
     return false;
 
   auto Cond =
       static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
   if (Cond == CmpInst::FCMP_TRUE || Cond == CmpInst::FCMP_FALSE) {
     putConstant(I, ResReg, Cond == CmpInst::FCMP_TRUE ? 1 : 0);
     MIB->eraseFromParent();
     return true;
   }
 
-  auto LHSReg = MIB->getOperand(2).getReg();
-  auto RHSReg = MIB->getOperand(3).getReg();
+  auto LHSReg = MIB.getReg(2);
+  auto RHSReg = MIB.getReg(3);
   if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
                       Helper.OperandRegBankID))
     return false;
 
   auto ARMConds = getComparePreds(Cond);
   auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
   putConstant(I, ZeroReg, 0);
 
if (TM.isPositionIndependent()) {
     if (STI.isTargetDarwin())
       TargetFlags |= ARMII::MO_NONLAZY;
     if (STI.isGVInGOT(GV))
       TargetFlags |= ARMII::MO_GOT;
     MIB->getOperand(1).setTargetFlags(TargetFlags);
 
     if (Indirect) {
       if (!UseOpcodeThatLoads) {
-        auto ResultReg = MIB->getOperand(0).getReg();
+        auto ResultReg = MIB.getReg(0);
         auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
 
         MIB->getOperand(0).setReg(AddressReg);
 
         auto InsertBefore = std::next(MIB->getIterator());
         auto MIBLoad = BuildMI(MBB, InsertBefore, MIB->getDebugLoc(),
                                TII.get(Opcodes.LOAD32))
                            .addDef(ResultReg)

 
 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
                                           MachineRegisterInfo &MRI) const {
   auto &MBB = *MIB->getParent();
   auto InsertBefore = std::next(MIB->getIterator());
   auto &DbgLoc = MIB->getDebugLoc();
 
   // Compare the condition to 1.
-  auto CondReg = MIB->getOperand(1).getReg();
+  auto CondReg = MIB.getReg(1);
   assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) &&
          "Unsupported types for select operation");
   auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
                   .addUse(CondReg)
                   .addImm(1)
                   .add(predOps(ARMCC::AL));
   if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI))
     return false;
 
   // Move a value into the result register based on the result of the
   // comparison.
-  auto ResReg = MIB->getOperand(0).getReg();
-  auto TrueReg = MIB->getOperand(2).getReg();
-  auto FalseReg = MIB->getOperand(3).getReg();
+  auto ResReg = MIB.getReg(0);
+  auto TrueReg = MIB.getReg(2);
+  auto FalseReg = MIB.getReg(3);
   assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
          validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
          "Unsupported types for select operation");
   auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr))
                    .addDef(ResReg)
                    .addUse(TrueReg)
                    .addUse(FalseReg)
                    .add(predOps(ARMCC::EQ, ARM::CPSR));

llvm/lib/Target/X86/X86CallLowering.cpp

void assignValueToReg(Register ValVReg, Register PhysReg,
     // we expect normal extendRegister mechanism to work.
     unsigned PhysRegSize =
         MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
     unsigned ValSize = VA.getValVT().getSizeInBits();
     unsigned LocSize = VA.getLocVT().getSizeInBits();
     if (PhysRegSize > ValSize && LocSize == ValSize) {
       assert((PhysRegSize == 128 || PhysRegSize == 80)  && "We expect that to be 128 bit");
       auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
-      ExtReg = MIB->getOperand(0).getReg();
+      ExtReg = MIB.getReg(0);
     } else
       ExtReg = extendRegister(ValVReg, VA);
 
     MIRBuilder.buildCopy(PhysReg, ExtReg);
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
                             MachinePointerInfo &MPO, CCValAssign &VA) override {

llvm/lib/Target/X86/X86InstrInfo.cpp

 /// This is used for mapping:
 ///   %xmm4 = V_SET0
 /// to:
 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
 ///
 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
                              const MCInstrDesc &Desc) {
   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
-  Register Reg = MIB->getOperand(0).getReg();
+  Register Reg = MIB.getReg(0);
   MIB->setDesc(Desc);
 
   // MachineInstr::addOperand() will insert explicit operands before any
   // implicit operands.
   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
   // But we don't trust that.
-  assert(MIB->getOperand(1).getReg() == Reg &&
-         MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
+  assert(MIB.getReg(1) == Reg &&
+         MIB.getReg(2) == Reg && "Misplaced operand");
   return true;
 }
 
 /// Expand a single-def pseudo instruction to a two-addr
 /// instruction with two %k0 reads.
 /// This is used for mapping:
 ///   %k4 = K_SET1
 /// to:
 ///   %k4 = KXNORrr %k0, %k0
 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
                             const MCInstrDesc &Desc, unsigned Reg) {
   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
   MIB->setDesc(Desc);
   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
   return true;
 }
 
 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
                           bool MinusOne) {
   MachineBasicBlock &MBB = *MIB->getParent();
   DebugLoc DL = MIB->getDebugLoc();
-  Register Reg = MIB->getOperand(0).getReg();
+  Register Reg = MIB.getReg(0);
 
   // Insert the XOR.
   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
       .addReg(Reg, RegState::Undef)
       .addReg(Reg, RegState::Undef);
 
   // Turn the pseudo into an INC or DEC.
   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
if (X86FI->getUsesRedZone()) {
       return true;
     }
 
     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
     // widen the register if necessary.
     StackAdjustment = 8;
     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
     MIB->setDesc(TII.get(X86::POP64r));
     MIB->getOperand(0)
-        .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
+        .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
   } else {
     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
     StackAdjustment = 4;
     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
     MIB->setDesc(TII.get(X86::POP32r));
   }
 
   // Build CFI if necessary.

 }
 
 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
 // code sequence is needed for other targets.
 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
                                  const TargetInstrInfo &TII) {
   MachineBasicBlock &MBB = *MIB->getParent();
   DebugLoc DL = MIB->getDebugLoc();
-  Register Reg = MIB->getOperand(0).getReg();
+  Register Reg = MIB.getReg(0);
   const GlobalValue *GV =
       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
   auto Flags = MachineMemOperand::MOLoad |
                MachineMemOperand::MODereferenceable |
                MachineMemOperand::MOInvariant;
   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
   MachineBasicBlock::iterator I = MIB.getInstr();

 // This is used to handle spills for 128/256-bit registers when we have AVX512,
 // but not VLX. If it uses an extended register we need to use an instruction
 // that loads the lower 128/256-bit, but is available with only AVX512F.
 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
                             const TargetRegisterInfo *TRI,
                             const MCInstrDesc &LoadDesc,
                             const MCInstrDesc &BroadcastDesc,
                             unsigned SubIdx) {
-  Register DestReg = MIB->getOperand(0).getReg();
+  Register DestReg = MIB.getReg(0);
   // Check if DestReg is XMM16-31 or YMM16-31.
   if (TRI->getEncodingValue(DestReg) < 16) {
     // We can use a normal VEX encoded load.
     MIB->setDesc(LoadDesc);
   } else {
     // Use a 128/256-bit VBROADCAST instruction.
     MIB->setDesc(BroadcastDesc);
     // Change the destination to a 512-bit register.
     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
     MIB->getOperand(0).setReg(DestReg);
   }
   return true;
 }
 
 // This is used to handle spills for 128/256-bit registers when we have AVX512,
 // but not VLX. If it uses an extended register we need to use an instruction
 // that stores the lower 128/256-bit, but is available with only AVX512F.
 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
                              const TargetRegisterInfo *TRI,
                              const MCInstrDesc &StoreDesc,
                              const MCInstrDesc &ExtractDesc,
                              unsigned SubIdx) {
-  Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
+  Register SrcReg = MIB.getReg(X86::AddrNumOperands);
   // Check if DestReg is XMM16-31 or YMM16-31.
   if (TRI->getEncodingValue(SrcReg) < 16) {
     // We can use a normal VEX encoded store.
     MIB->setDesc(StoreDesc);
   } else {
     // Use a VEXTRACTF instruction.
     MIB->setDesc(ExtractDesc);
     // Change the destination to a 512-bit register.
     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
   }
 
   return true;
 }
 
 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
   MIB->setDesc(Desc);
   int64_t ShiftAmt = MIB->getOperand(2).getImm();
   // Temporarily remove the immediate so we can add another source register.
   MIB->RemoveOperand(2);
   // Add the register. Don't copy the kill flag if there is one.
-  MIB.addReg(MIB->getOperand(1).getReg(),
+  MIB.addReg(MIB.getReg(1),
              getUndefRegState(MIB->getOperand(1).isUndef()));
   // Add back the immediate.
   MIB.addImm(ShiftAmt);
   return true;
 }
 
 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   bool HasAVX = Subtarget.hasAVX();
bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   case X86::V_SET0:
   case X86::FsFLD0SS:
   case X86::FsFLD0SD:
   case X86::FsFLD0F128:
     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
   case X86::AVX_SET0: {
     assert(HasAVX && "AVX not supported");
     const TargetRegisterInfo *TRI = &getRegisterInfo();
-    Register SrcReg = MIB->getOperand(0).getReg();
+    Register SrcReg = MIB.getReg(0);
     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
     MIB->getOperand(0).setReg(XReg);
     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
     MIB.addReg(SrcReg, RegState::ImplicitDefine);
     return true;
   }
   case X86::AVX512_128_SET0:
   case X86::AVX512_FsFLD0SS:
   case X86::AVX512_FsFLD0SD:
   case X86::AVX512_FsFLD0F128: {
     bool HasVLX = Subtarget.hasVLX();
-    Register SrcReg = MIB->getOperand(0).getReg();
+    Register SrcReg = MIB.getReg(0);
     const TargetRegisterInfo *TRI = &getRegisterInfo();
     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
       return Expand2AddrUndef(MIB,
                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
     // Extended register without VLX. Use a larger XOR.
     SrcReg =
         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
     MIB->getOperand(0).setReg(SrcReg);
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }
   case X86::AVX512_256_SET0:
   case X86::AVX512_512_SET0: {
     bool HasVLX = Subtarget.hasVLX();
-    Register SrcReg = MIB->getOperand(0).getReg();
+    Register SrcReg = MIB.getReg(0);
     const TargetRegisterInfo *TRI = &getRegisterInfo();
     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
       MIB->getOperand(0).setReg(XReg);
       Expand2AddrUndef(MIB,
                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
       MIB.addReg(SrcReg, RegState::ImplicitDefine);
       return true;
     }
     if (MI.getOpcode() == X86::AVX512_256_SET0) {
       // No VLX so we must reference a zmm.
       unsigned ZReg =
         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
       MIB->getOperand(0).setReg(ZReg);
     }
     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   }
   case X86::V_SETALLONES:
     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
   case X86::AVX2_SETALLONES:
     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
   case X86::AVX1_SETALLONES: {
-    Register Reg = MIB->getOperand(0).getReg();
+    Register Reg = MIB.getReg(0);
     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
     MIB->setDesc(get(X86::VCMPPSYrri));
     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
     return true;
   }
   case X86::AVX512_512_SETALLONES: {
-    Register Reg = MIB->getOperand(0).getReg();
+    Register Reg = MIB.getReg(0);
     MIB->setDesc(get(X86::VPTERNLOGDZrri));
     // VPTERNLOGD needs 3 register inputs and an immediate.
     // 0xff will return 1s for any input.
     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
        .addReg(Reg, RegState::Undef).addImm(0xff);
     return true;
   }
   case X86::AVX512_512_SEXT_MASK_32:
   case X86::AVX512_512_SEXT_MASK_64: {
-    Register Reg = MIB->getOperand(0).getReg();
-    Register MaskReg = MIB->getOperand(1).getReg();
+    Register Reg = MIB.getReg(0);
+    Register MaskReg = MIB.getReg(1);
     unsigned MaskState = getRegState(MIB->getOperand(1));
     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
     MI.RemoveOperand(1);
     MIB->setDesc(get(Opc));
     // VPTERNLOG needs 3 register inputs and an immediate.
     // 0xff will return 1s for any input.
     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
   case X86::VMOVAPSZ256mr_NOVLX:
     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
   case X86::VMOVUPSZ256mr_NOVLX:
     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
   case X86::MOV32ri64: {
-    Register Reg = MIB->getOperand(0).getReg();
+    Register Reg = MIB.getReg(0);
     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
     MI.setDesc(get(X86::MOV32ri));
     MIB->getOperand(0).setReg(Reg32);
     MIB.addReg(Reg, RegState::ImplicitDefine);
     return true;
   }
 
   // KNL does not recognize dependency-breaking idioms for mask registers,

llvm/unittests/CodeGen/GlobalISel/CSETest.cpp

TEST_F(GISelMITest, TestCSE) {
   auto MIBFP0_1 = CSEB.buildFConstant(s32, 1.0);
   EXPECT_TRUE(&*MIBFP0 == &*MIBFP0_1);
   CSEInfo.print();
 
   // Make sure buildConstant with a vector type doesn't crash, and the elements
   // CSE.
   auto Splat0 = CSEB.buildConstant(LLT::vector(2, s32), 0);
   EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, Splat0->getOpcode());
-  EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
-  EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0->getOperand(1).getReg()));
+  EXPECT_EQ(Splat0.getReg(1), Splat0.getReg(2));
+  EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0.getReg(1)));
 
   auto FSplat = CSEB.buildFConstant(LLT::vector(2, s32), 1.0);
   EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, FSplat->getOpcode());
-  EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
-  EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat->getOperand(1).getReg()));
+  EXPECT_EQ(FSplat.getReg(1), FSplat.getReg(2));
+  EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat.getReg(1)));
 
   // Check G_UNMERGE_VALUES
   auto MIBUnmerge = CSEB.buildUnmerge({s32, s32}, Copies[0]);
   auto MIBUnmerge2 = CSEB.buildUnmerge({s32, s32}, Copies[0]);
   EXPECT_TRUE(&*MIBUnmerge == &*MIBUnmerge2);
 }
 
 TEST_F(GISelMITest, TestCSEConstantConfig) {

llvm/unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp

if (!TM)
     return;
   // Try to use the FoldableInstructionsBuilder to build binary ops.
   ConstantFoldingMIRBuilder CFB(B.getState());
   LLT s32 = LLT::scalar(32);
   int64_t Cst;
   auto MIBCAdd =
       CFB.buildAdd(s32, CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1));
   // This should be a constant now.
-  bool match = mi_match(MIBCAdd->getOperand(0).getReg(), *MRI, m_ICst(Cst));
+  bool match = mi_match(MIBCAdd.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 1);
   auto MIBCAdd1 =
       CFB.buildInstr(TargetOpcode::G_ADD, {s32},
                      {CFB.buildConstant(s32, 0), CFB.buildConstant(s32, 1)});
   // This should be a constant now.
-  match = mi_match(MIBCAdd1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
+  match = mi_match(MIBCAdd1.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 1);
 
   // Try one of the other constructors of MachineIRBuilder to make sure it's
   // compatible.
   ConstantFoldingMIRBuilder CFB1(*MF);
   CFB1.setInsertPt(*EntryMBB, EntryMBB->end());
   auto MIBCSub =
       CFB1.buildInstr(TargetOpcode::G_SUB, {s32},
                       {CFB1.buildConstant(s32, 1), CFB1.buildConstant(s32, 1)});
   // This should be a constant now.
-  match = mi_match(MIBCSub->getOperand(0).getReg(), *MRI, m_ICst(Cst));
+  match = mi_match(MIBCSub.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 0);
 
   auto MIBCSext1 =
       CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32},
                       {CFB1.buildConstant(s32, 0x01), uint64_t(8)});
   // This should be a constant now.
-  match = mi_match(MIBCSext1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
+  match = mi_match(MIBCSext1.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(1, Cst);
 
   auto MIBCSext2 =
       CFB1.buildInstr(TargetOpcode::G_SEXT_INREG, {s32},
                       {CFB1.buildConstant(s32, 0x80), uint64_t(8)});
   // This should be a constant now.
-  match = mi_match(MIBCSext2->getOperand(0).getReg(), *MRI, m_ICst(Cst));
+  match = mi_match(MIBCSext2.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(-0x80, Cst);
 }
 
 TEST_F(GISelMITest, FoldBinOp) {
   setUp();
   if (!TM)
     return;
 
   LLT s32{LLT::scalar(32)};
   auto MIBCst1 = B.buildConstant(s32, 16);
   auto MIBCst2 = B.buildConstant(s32, 9);
   auto MIBFCst1 = B.buildFConstant(s32, 1.0000001);
   auto MIBFCst2 = B.buildFConstant(s32, 2.0);
 
   // Test G_ADD folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGAddInt =
-      ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGAddInt.hasValue());
   EXPECT_EQ(25ULL, FoldGAddInt.getValue().getLimitedValue());
   Optional<APInt> FoldGAddMix =
-      ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGAddMix.hasValue());
   EXPECT_EQ(1073741840ULL, FoldGAddMix.getValue().getLimitedValue());
 
   // Test G_AND folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGAndInt =
-      ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGAndInt.hasValue());
   EXPECT_EQ(0ULL, FoldGAndInt.getValue().getLimitedValue());
   Optional<APInt> FoldGAndMix =
-      ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2->getOperand(0).getReg(),
-                        MIBFCst1->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2.getReg(0),
+                        MIBFCst1.getReg(0), *MRI);
   EXPECT_TRUE(FoldGAndMix.hasValue());
   EXPECT_EQ(1ULL, FoldGAndMix.getValue().getLimitedValue());
 
   // Test G_ASHR folding Integer + Mixed cases
   Optional<APInt> FoldGAShrInt =
-      ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGAShrInt.hasValue());
   EXPECT_EQ(0ULL, FoldGAShrInt.getValue().getLimitedValue());
   Optional<APInt> FoldGAShrMix =
-      ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGAShrMix.hasValue());
   EXPECT_EQ(2097152ULL, FoldGAShrMix.getValue().getLimitedValue());
 
   // Test G_LSHR folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGLShrInt =
-      ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGLShrInt.hasValue());
   EXPECT_EQ(0ULL, FoldGLShrInt.getValue().getLimitedValue());
   Optional<APInt> FoldGLShrMix =
-      ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGLShrMix.hasValue());
   EXPECT_EQ(2080768ULL, FoldGLShrMix.getValue().getLimitedValue());
 
   // Test G_MUL folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGMulInt =
-      ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGMulInt.hasValue());
   EXPECT_EQ(144ULL, FoldGMulInt.getValue().getLimitedValue());
   Optional<APInt> FoldGMulMix =
-      ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGMulMix.hasValue());
   EXPECT_EQ(0ULL, FoldGMulMix.getValue().getLimitedValue());
 
   // Test G_OR folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGOrInt =
-      ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGOrInt.hasValue());
   EXPECT_EQ(25ULL, FoldGOrInt.getValue().getLimitedValue());
   Optional<APInt> FoldGOrMix =
-      ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGOrMix.hasValue());
   EXPECT_EQ(1073741840ULL, FoldGOrMix.getValue().getLimitedValue());
 
   // Test G_SHL folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGShlInt =
-      ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGShlInt.hasValue());
   EXPECT_EQ(8192ULL, FoldGShlInt.getValue().getLimitedValue());
   Optional<APInt> FoldGShlMix =
-      ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGShlMix.hasValue());
   EXPECT_EQ(0ULL, FoldGShlMix.getValue().getLimitedValue());
 
   // Test G_SUB folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGSubInt =
-      ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSubInt.hasValue());
   EXPECT_EQ(7ULL, FoldGSubInt.getValue().getLimitedValue());
   Optional<APInt> FoldGSubMix =
-      ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSubMix.hasValue());
   EXPECT_EQ(3221225488ULL, FoldGSubMix.getValue().getLimitedValue());
 
   // Test G_XOR folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGXorInt =
-      ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGXorInt.hasValue());
   EXPECT_EQ(25ULL, FoldGXorInt.getValue().getLimitedValue());
   Optional<APInt> FoldGXorMix =
-      ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGXorMix.hasValue());
   EXPECT_EQ(1073741840ULL, FoldGXorMix.getValue().getLimitedValue());
 
   // Test G_UDIV folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGUdivInt =
-      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGUdivInt.hasValue());
   EXPECT_EQ(1ULL, FoldGUdivInt.getValue().getLimitedValue());
   Optional<APInt> FoldGUdivMix =
-      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGUdivMix.hasValue());
   EXPECT_EQ(0ULL, FoldGUdivMix.getValue().getLimitedValue());
 
   // Test G_SDIV folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGSdivInt =
-      ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSdivInt.hasValue());
   EXPECT_EQ(1ULL, FoldGSdivInt.getValue().getLimitedValue());
   Optional<APInt> FoldGSdivMix =
-      ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSdivMix.hasValue());
   EXPECT_EQ(0ULL, FoldGSdivMix.getValue().getLimitedValue());
 
   // Test G_UREM folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGUremInt =
-      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGUremInt.hasValue());
   EXPECT_EQ(1ULL, FoldGUremInt.getValue().getLimitedValue());
   Optional<APInt> FoldGUremMix =
-      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGUremMix.hasValue());
   EXPECT_EQ(0ULL, FoldGUremMix.getValue().getLimitedValue());
 
   // Test G_SREM folding Integer + Mixed Int-Float cases
   Optional<APInt> FoldGSremInt =
-      ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
-                        MIBCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1.getReg(0),
+                        MIBCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSremInt.hasValue());
   EXPECT_EQ(7ULL, FoldGSremInt.getValue().getLimitedValue());
   Optional<APInt> FoldGSremMix =
-      ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
-                        MIBFCst2->getOperand(0).getReg(), *MRI);
+      ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1.getReg(0),
+                        MIBFCst2.getReg(0), *MRI);
   EXPECT_TRUE(FoldGSremMix.hasValue());
   EXPECT_EQ(16ULL, FoldGSremMix.getValue().getLimitedValue());
 }
 
 } // namespace
 No newline at end of file

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

 }
 
 TEST_F(GISelMITest, BuildMerge) {
   setUp();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
-  Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
-  Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
-  Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
-  Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
+  Register RegC0 = B.buildConstant(S32, 0).getReg(0);
+  Register RegC1 = B.buildConstant(S32, 1).getReg(0);
+  Register RegC2 = B.buildConstant(S32, 2).getReg(0);
+  Register RegC3 = B.buildConstant(S32, 3).getReg(0);
 
   // Merging plain constants as one big blob of bit should produce a
   // G_MERGE_VALUES.
   B.buildMerge(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3});
   // Merging plain constants to a vector should produce a G_BUILD_VECTOR.
   LLT V2x32 = LLT::vector(2, 32);
   Register RegC0C1 =
-      B.buildMerge(V2x32, {RegC0, RegC1})->getOperand(0).getReg();
+      B.buildMerge(V2x32, {RegC0, RegC1}).getReg(0);
   Register RegC2C3 =
-      B.buildMerge(V2x32, {RegC2, RegC3})->getOperand(0).getReg();
+      B.buildMerge(V2x32, {RegC2, RegC3}).getReg(0);
   // Merging vector constants to a vector should produce a G_CONCAT_VECTORS.
   B.buildMerge(LLT::vector(4, 32), {RegC0C1, RegC2C3});
   // Merging vector constants to a plain type is not allowed.
   // Nothing else to test.
 
   auto CheckStr = R"(
   ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1

llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

 namespace {
 
 TEST_F(GISelMITest, MatchIntConstant) {
   setUp();
   if (!TM)
     return;
   auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
   int64_t Cst;
-  bool match = mi_match(MIBCst->getOperand(0).getReg(), *MRI, m_ICst(Cst));
+  bool match = mi_match(MIBCst.getReg(0), *MRI, m_ICst(Cst));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 42);
 }
 
 TEST_F(GISelMITest, MatchBinaryOp) {
   setUp();
   if (!TM)
     return;
   LLT s64 = LLT::scalar(64);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   // Test case for no bind.
   bool match =
-      mi_match(MIBAdd->getOperand(0).getReg(), *MRI, m_GAdd(m_Reg(), m_Reg()));
+      mi_match(MIBAdd.getReg(0), *MRI, m_GAdd(m_Reg(), m_Reg()));
   EXPECT_TRUE(match);
   Register Src0, Src1, Src2;
-  match = mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBAdd.getReg(0), *MRI,
                    m_GAdd(m_Reg(Src0), m_Reg(Src1)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, Copies[1]);
 
   // Build MUL(ADD %0, %1), %2
   auto MIBMul = B.buildMul(s64, MIBAdd, Copies[2]);
 
   // Try to match MUL.
-  match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBMul.getReg(0), *MRI,
                    m_GMul(m_Reg(Src0), m_Reg(Src1)));
   EXPECT_TRUE(match);
-  EXPECT_EQ(Src0, MIBAdd->getOperand(0).getReg());
+  EXPECT_EQ(Src0, MIBAdd.getReg(0));
   EXPECT_EQ(Src1, Copies[2]);
 
   // Try to match MUL(ADD)
-  match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBMul.getReg(0), *MRI,
                    m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, Copies[1]);
   EXPECT_EQ(Src2, Copies[2]);
 
   // Test Commutativity.
   auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42));
   // Try to match MUL(Cst, Reg) on src of MUL(Reg, Cst) to validate
   // commutativity.
   int64_t Cst;
-  match = mi_match(MIBMul2->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBMul2.getReg(0), *MRI,
                    m_GMul(m_ICst(Cst), m_Reg(Src0)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 42);
   EXPECT_EQ(Src0, Copies[0]);
 
   // Make sure commutative doesn't work with something like SUB.
   auto MIBSub = B.buildSub(s64, Copies[0], B.buildConstant(s64, 42));
-  match = mi_match(MIBSub->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBSub.getReg(0), *MRI,
                    m_GSub(m_ICst(Cst), m_Reg(Src0)));
   EXPECT_FALSE(match);
 
   auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64},
                               {Copies[0], B.buildConstant(s64, 42)});
   // Match and test commutativity for FMUL.
-  match = mi_match(MIBFMul->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBFMul.getReg(0), *MRI,
                    m_GFMul(m_ICst(Cst), m_Reg(Src0)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Cst, 42);
   EXPECT_EQ(Src0, Copies[0]);
 
   // FSUB
   auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64},
                               {Copies[0], B.buildConstant(s64, 42)});
-  match = mi_match(MIBFSub->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBFSub.getReg(0), *MRI,
                    m_GFSub(m_Reg(Src0), m_Reg()));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 
   // Build AND %0, %1
   auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]);
   // Try to match AND.
-  match = mi_match(MIBAnd->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBAnd.getReg(0), *MRI,
                    m_GAnd(m_Reg(Src0), m_Reg(Src1)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, Copies[1]);
 
   // Build OR %0, %1
   auto MIBOr = B.buildOr(s64, Copies[0], Copies[1]);
   // Try to match OR.
-  match = mi_match(MIBOr->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBOr.getReg(0), *MRI,
                    m_GOr(m_Reg(Src0), m_Reg(Src1)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, Copies[1]);
 }
 
 TEST_F(GISelMITest, MatchFPUnaryOp) {
   setUp();
   if (!TM)
     return;
 
   // Truncate s64 to s32.
   LLT s32 = LLT::scalar(32);
   auto Copy0s32 = B.buildFPTrunc(s32, Copies[0]);
 
   // Match G_FABS.
   auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32});
   bool match =
-      mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg()));
+      mi_match(MIBFabs.getReg(0), *MRI, m_GFabs(m_Reg()));
   EXPECT_TRUE(match);
 
   Register Src;
   auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});
-  match = mi_match(MIBFNeg->getOperand(0).getReg(), *MRI, m_GFNeg(m_Reg(Src)));
+  match = mi_match(MIBFNeg.getReg(0), *MRI, m_GFNeg(m_Reg(Src)));
   EXPECT_TRUE(match);
-  EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
+  EXPECT_EQ(Src, Copy0s32.getReg(0));
 
-  match = mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg(Src)));
+  match = mi_match(MIBFabs.getReg(0), *MRI, m_GFabs(m_Reg(Src)));
   EXPECT_TRUE(match);
-  EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
+  EXPECT_EQ(Src, Copy0s32.getReg(0));
 
   // Build and match FConstant.
   auto MIBFCst = B.buildFConstant(s32, .5);
   const ConstantFP *TmpFP{};
-  match = mi_match(MIBFCst->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP));
+  match = mi_match(MIBFCst.getReg(0), *MRI, m_GFCst(TmpFP));
   EXPECT_TRUE(match);
   EXPECT_TRUE(TmpFP);
   APFloat APF((float).5);
   auto *CFP = ConstantFP::get(Context, APF);
   EXPECT_EQ(CFP, TmpFP);
 
   // Build double float.
   LLT s64 = LLT::scalar(64);
   auto MIBFCst64 = B.buildFConstant(s64, .5);
   const ConstantFP *TmpFP64{};
-  match = mi_match(MIBFCst64->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP64));
+  match = mi_match(MIBFCst64.getReg(0), *MRI, m_GFCst(TmpFP64));
   EXPECT_TRUE(match);
   EXPECT_TRUE(TmpFP64);
   APFloat APF64(.5);
   auto CFP64 = ConstantFP::get(Context, APF64);
   EXPECT_EQ(CFP64, TmpFP64);
   EXPECT_NE(TmpFP64, TmpFP);
 
   // Build half float.
   LLT s16 = LLT::scalar(16);
   auto MIBFCst16 = B.buildFConstant(s16, .5);
   const ConstantFP *TmpFP16{};
-  match = mi_match(MIBFCst16->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP16));
+  match = mi_match(MIBFCst16.getReg(0), *MRI, m_GFCst(TmpFP16));
   EXPECT_TRUE(match);
   EXPECT_TRUE(TmpFP16);
   bool Ignored;
   APFloat APF16(.5);
   APF16.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
   auto CFP16 = ConstantFP::get(Context, APF16);
   EXPECT_EQ(TmpFP16, CFP16);
   EXPECT_NE(TmpFP16, TmpFP);
 }
 
 TEST_F(GISelMITest, MatchExtendsTrunc) {
   setUp();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
 
   auto MIBTrunc = B.buildTrunc(s32, Copies[0]);
   auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
   auto MIBZExt = B.buildZExt(s64, MIBTrunc);
   auto MIBSExt = B.buildSExt(s64, MIBTrunc);
   Register Src0;
   bool match =
-      mi_match(MIBTrunc->getOperand(0).getReg(), *MRI, m_GTrunc(m_Reg(Src0)));
+      mi_match(MIBTrunc.getReg(0), *MRI, m_GTrunc(m_Reg(Src0)));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   match =
-      mi_match(MIBAExt->getOperand(0).getReg(), *MRI, m_GAnyExt(m_Reg(Src0)));
+      mi_match(MIBAExt.getReg(0), *MRI, m_GAnyExt(m_Reg(Src0)));
   EXPECT_TRUE(match);
-  EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
+  EXPECT_EQ(Src0, MIBTrunc.getReg(0));
 
-  match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI, m_GSExt(m_Reg(Src0)));
+  match = mi_match(MIBSExt.getReg(0), *MRI, m_GSExt(m_Reg(Src0)));
   EXPECT_TRUE(match);
-  EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
+  EXPECT_EQ(Src0, MIBTrunc.getReg(0));
 
-  match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI, m_GZExt(m_Reg(Src0)));
+  match = mi_match(MIBZExt.getReg(0), *MRI, m_GZExt(m_Reg(Src0)));
   EXPECT_TRUE(match);
-  EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
+  EXPECT_EQ(Src0, MIBTrunc.getReg(0));
 
   // Match ext(trunc src)
-  match = mi_match(MIBAExt->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBAExt.getReg(0), *MRI,
                    m_GAnyExt(m_GTrunc(m_Reg(Src0))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 
-  match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBSExt.getReg(0), *MRI,
                    m_GSExt(m_GTrunc(m_Reg(Src0))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 
-  match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI,
+  match = mi_match(MIBZExt.getReg(0), *MRI,
                    m_GZExt(m_GTrunc(m_Reg(Src0))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 }
 
 TEST_F(GISelMITest, MatchSpecificType) {
   setUp();
   if (!TM)
     return;
 
   // Try to match a 64bit add.
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
-  EXPECT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
+  EXPECT_FALSE(mi_match(MIBAdd.getReg(0), *MRI,
                         m_GAdd(m_SpecificType(s32), m_Reg())));
-  EXPECT_TRUE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
+  EXPECT_TRUE(mi_match(MIBAdd.getReg(0), *MRI,
                        m_GAdd(m_SpecificType(s64), m_Reg())));
 
   // Try to match the destination type of a bitcast.
   LLT v2s32 = LLT::vector(2, 32);
   auto MIBCast = B.buildCast(v2s32, Copies[0]);
   EXPECT_TRUE(
-      mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_GBitcast(m_Reg())));
+      mi_match(MIBCast.getReg(0), *MRI, m_GBitcast(m_Reg())));
   EXPECT_TRUE(
-      mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_SpecificType(v2s32)));
+      mi_match(MIBCast.getReg(0), *MRI, m_SpecificType(v2s32)));
   EXPECT_TRUE(
-      mi_match(MIBCast->getOperand(1).getReg(), *MRI, m_SpecificType(s64)));
+      mi_match(MIBCast.getReg(1), *MRI, m_SpecificType(s64)));
 
   // Build a PTRToInt and INTTOPTR and match and test them.
   LLT PtrTy = LLT::pointer(0, 64);
   auto MIBIntToPtr = B.buildCast(PtrTy, Copies[0]);
   auto MIBPtrToInt = B.buildCast(s64, MIBIntToPtr);
   Register Src0;
 
   // match the ptrtoint(inttoptr reg)
-  bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), *MRI,
+  bool match = mi_match(MIBPtrToInt.getReg(0), *MRI,
                         m_GPtrToInt(m_GIntToPtr(m_Reg(Src0))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
 }
 
 TEST_F(GISelMITest, MatchCombinators) {
   setUp();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   Register Src0, Src1;
   bool match =
-      mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
+      mi_match(MIBAdd.getReg(0), *MRI,
                m_all_of(m_SpecificType(s64), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, Copies[1]);
   // Check for s32 (which should fail).
   match =
-      mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
+      mi_match(MIBAdd.getReg(0), *MRI,
                m_all_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
   EXPECT_FALSE(match);
   match =
-      mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
+      mi_match(MIBAdd.getReg(0), *MRI,
                m_any_of(m_SpecificType(s32), m_GAdd(m_Reg(Src0), m_Reg(Src1))));
   EXPECT_TRUE(match);
   EXPECT_EQ(Src0, Copies[0]);
   EXPECT_EQ(Src1, Copies[1]);
 
   // Match a case where none of the predicates hold true.
   match = mi_match(
-      MIBAdd->getOperand(0).getReg(), *MRI,
+      MIBAdd.getReg(0), *MRI,
       m_any_of(m_SpecificType(LLT::scalar(16)), m_GSub(m_Reg(), m_Reg())));
   EXPECT_FALSE(match);
 }
 
 TEST_F(GISelMITest, MatchMiscellaneous) {
   setUp();
   if (!TM)
     return;