[llvm-exegesis] Serial snippet: Restrict the set of back-to-back instructions

[courbet]

Summary

Right now when picking a back-to-back instruction at random, we might select
instructions that we do not know how to handle.
Add a ExegesisTarget hook to possibly filter instructions.

llvm/tools/llvm-exegesis/lib/Target.h

public:
   // Assigns a random operand of the right type to variable Var.
   // The default implementation only handles generic operand types.
   // The target is responsible for handling any operand
   // starting from OPERAND_FIRST_TARGET.
   virtual void randomizeMCOperand(const Instruction &Instr, const Variable &Var,
                                   MCOperand &AssignedValue,
                                   const BitVector &ForbiddenRegs) const;
 
+  // Returns true if this instruction is supported as a back-to-back
+  // instructions.
+  // FIXME: Eventually we should discover this dynamically.
+  virtual bool allowAsBackToBack(const Instruction &Instr) const {
+    return true;
+  }
+
   // Creates a snippet generator for the given mode.
   std::unique_ptr<SnippetGenerator>
   createSnippetGenerator(InstructionBenchmark::ModeE Mode,
                          const LLVMState &State,
                          const SnippetGenerator::Options &Opts) const;
   // Creates a benchmark runner for the given mode.
   std::unique_ptr<BenchmarkRunner>
   createBenchmarkRunner(InstructionBenchmark::ModeE Mode,

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

 #include "X86RegisterInfo.h"
 #include "X86Subtarget.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/Support/FormatVariadic.h"
 
 namespace llvm {
 namespace exegesis {
 
-// Returns an error if we cannot handle the memory references in this
+// Returns a non-null reason if we cannot handle the memory references in this
 // instruction.
-static Error isInvalidMemoryInstr(const Instruction &Instr) {
+static const char *isInvalidMemoryInstr(const Instruction &Instr) {
   switch (Instr.Description.TSFlags & X86II::FormMask) {
   default:
     llvm_unreachable("Unknown FormMask value");
   // These have no memory access.
   case X86II::Pseudo:
   case X86II::RawFrm:
   case X86II::AddCCFrm:
   case X86II::MRMDestReg:
static const char *isInvalidMemoryInstr(const Instruction &Instr) {
   case X86II::MRM_F9:
   case X86II::MRM_FA:
   case X86II::MRM_FB:
   case X86II::MRM_FC:
   case X86II::MRM_FD:
   case X86II::MRM_FE:
   case X86II::MRM_FF:
   case X86II::RawFrmImm8:
-    return Error::success();
+    return nullptr;
   case X86II::AddRegFrm:
     return (Instr.Description.Opcode == X86::POP16r ||
             Instr.Description.Opcode == X86::POP32r ||
             Instr.Description.Opcode == X86::PUSH16r ||
             Instr.Description.Opcode == X86::PUSH32r)
-               ? make_error<Failure>(
-                     "unsupported opcode: unsupported memory access")
-               : Error::success();
+               ? "unsupported opcode: unsupported memory access"
+               : nullptr;
   // These access memory and are handled.
   case X86II::MRMDestMem:
   case X86II::MRMSrcMem:
   case X86II::MRMSrcMem4VOp3:
   case X86II::MRMSrcMemOp4:
   case X86II::MRMSrcMemCC:
   case X86II::MRMXmCC:
   case X86II::MRMXm:
   case X86II::MRM0m:
   case X86II::MRM1m:
   case X86II::MRM2m:
   case X86II::MRM3m:
   case X86II::MRM4m:
   case X86II::MRM5m:
   case X86II::MRM6m:
   case X86II::MRM7m:
-    return Error::success();
+    return nullptr;
   // These access memory and are not handled yet.
   case X86II::RawFrmImm16:
   case X86II::RawFrmMemOffs:
   case X86II::RawFrmSrc:
   case X86II::RawFrmDst:
   case X86II::RawFrmDstSrc:
-    return make_error<Failure>("unsupported opcode: non uniform memory access");
+    return "unsupported opcode: non uniform memory access";
   }
 }
 
-static Error IsInvalidOpcode(const Instruction &Instr) {
+// If the opcode is invalid, returns a pointer to a character literal indicating
+// the reason. nullptr indicates a valid opcode.
+static const char *isInvalidOpcode(const Instruction &Instr) {
   const auto OpcodeName = Instr.Name;
   if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
-    return make_error<Failure>("unsupported opcode: pseudo instruction");
-  if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
-      OpcodeName.startswith("ADJCALLSTACK"))
-    return make_error<Failure>("unsupported opcode: Push/Pop/AdjCallStack");
-  if (Error Error = isInvalidMemoryInstr(Instr))
-    return Error;
+    return "unsupported opcode: pseudo instruction";
+  if (OpcodeName.startswith("POP") || OpcodeName.startswith("PUSH") ||
+      OpcodeName.startswith("ADJCALLSTACK") || OpcodeName.startswith("LEAVE"))
+    return "unsupported opcode: Push/Pop/AdjCallStack/Leave";
+  if (const auto reason = isInvalidMemoryInstr(Instr))
+    return reason;
   // We do not handle instructions with OPERAND_PCREL.
   for (const Operand &Op : Instr.Operands)
     if (Op.isExplicit() &&
         Op.getExplicitOperandInfo().OperandType == MCOI::OPERAND_PCREL)
-      return make_error<Failure>("unsupported opcode: PC relative operand");
+      return "unsupported opcode: PC relative operand";
   // We do not handle second-form X87 instructions. We only handle first-form
   // ones (_Fp), see comment in X86InstrFPStack.td.
   for (const Operand &Op : Instr.Operands)
     if (Op.isReg() && Op.isExplicit() &&
         Op.getExplicitOperandInfo().RegClass == X86::RSTRegClassID)
-      return make_error<Failure>("unsupported second-form X87 instruction");
-  return Error::success();
+      return "unsupported second-form X87 instruction";
+  return nullptr;
 }
 
 static unsigned getX86FPFlags(const Instruction &Instr) {
   return Instr.Description.TSFlags & X86II::FPTypeMask;
 }
 
 // Helper to fill a memory operand with a value.
 static void setMemOp(InstructionTemplate &IT, int OpIdx,
public:
   generateCodeTemplates(const Instruction &Instr,
                         const BitVector &ForbiddenRegisters) const override;
 };
 } // namespace
 
 Expected<std::vector<CodeTemplate>>
 X86SerialSnippetGenerator::generateCodeTemplates(
     const Instruction &Instr, const BitVector &ForbiddenRegisters) const {
-  if (auto E = IsInvalidOpcode(Instr))
-    return std::move(E);
+  if (const auto reason = isInvalidOpcode(Instr))
+    return make_error<Failure>(reason);
 
   // LEA gets special attention.
   const auto Opcode = Instr.Description.getOpcode();
   if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
     return generateLEATemplatesCommon(
         Instr, ForbiddenRegisters, State, Opts,
         [this](unsigned BaseReg, unsigned IndexReg,
                BitVector &CandidateDestRegs) {
           // We just select a destination register that aliases the base
           // register.
           CandidateDestRegs &=
               State.getRATC().getRegister(BaseReg).aliasedBits();
         });
   }
 
+  if (Instr.hasMemoryOperands())
+    return make_error<Failure>(
+        "unsupported memory operand in latency measurements");
+
   switch (getX86FPFlags(Instr)) {
   case X86II::NotFP:
     return SerialSnippetGenerator::generateCodeTemplates(Instr,
                                                           ForbiddenRegisters);
   case X86II::ZeroArgFP:
   case X86II::OneArgFP:
   case X86II::SpecialFP:
   case X86II::CompareFP:
generateCodeTemplates(const Instruction &Instr,
                         const BitVector &ForbiddenRegisters) const override;
 };
 
 } // namespace
 
 Expected<std::vector<CodeTemplate>>
 X86ParallelSnippetGenerator::generateCodeTemplates(
     const Instruction &Instr, const BitVector &ForbiddenRegisters) const {
-  if (auto E = IsInvalidOpcode(Instr))
-    return std::move(E);
+  if (const auto reason = isInvalidOpcode(Instr))
+    return make_error<Failure>(reason);
 
   // LEA gets special attention.
   const auto Opcode = Instr.Description.getOpcode();
   if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
     return generateLEATemplatesCommon(
         Instr, ForbiddenRegisters, State, Opts,
         [this](unsigned BaseReg, unsigned IndexReg,
                BitVector &CandidateDestRegs) {
std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override;
 
   ArrayRef<unsigned> getUnavailableRegisters() const override {
     return makeArrayRef(kUnavailableRegisters,
                         sizeof(kUnavailableRegisters) /
                             sizeof(kUnavailableRegisters[0]));
   }
 
+  bool allowAsBackToBack(const Instruction &Instr) const override {
+    const unsigned Opcode = Instr.Description.Opcode;
+    return !isInvalidOpcode(Instr) && Opcode != X86::LEA64r &&
+           Opcode != X86::LEA64_32r && Opcode != X86::LEA16r;
+  }
+
   std::unique_ptr<SnippetGenerator> createSerialSnippetGenerator(
       const LLVMState &State,
       const SnippetGenerator::Options &Opts) const override {
     return std::make_unique<X86SerialSnippetGenerator>(State, Opts);
   }
 
   std::unique_ptr<SnippetGenerator> createParallelSnippetGenerator(
       const LLVMState &State,
std::vector<MCInst> ExegesisX86Target::setRegTo(const MCSubtargetInfo &STI,
   if (X86::RFP32RegClass.contains(Reg) || X86::RFP64RegClass.contains(Reg) ||
       X86::RFP80RegClass.contains(Reg)) {
     return CI.loadX87FPAndFinalize(Reg);
   }
   if (Reg == X86::EFLAGS)
     return CI.popFlagAndFinalize();
   if (Reg == X86::MXCSR)
     return CI.loadImplicitRegAndFinalize(
-              STI.getFeatureBits()[X86::FeatureAVX] ? X86::VLDMXCSR
-                                                    : X86::LDMXCSR, 0x1f80);
+        STI.getFeatureBits()[X86::FeatureAVX] ? X86::VLDMXCSR : X86::LDMXCSR,
+        0x1f80);
   if (Reg == X86::FPCW)
     return CI.loadImplicitRegAndFinalize(X86::FLDCW16m, 0x37f);
   return {}; // Not yet implemented.
 }
 
 static ExegesisTarget *getTheExegesisX86Target() {
   static ExegesisX86Target Target;
   return &Target;
 }
 
 void InitializeX86ExegesisTarget() {
   ExegesisTarget::registerTarget(getTheExegesisX86Target());
 }
 
 } // namespace exegesis
 } // namespace llvm

llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp

TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
   // Memory is operands 4-8.
   EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI));
   EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(1));
   EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
   EXPECT_THAT(IT.getValueFor(I.Operands[7]), IsImm(kOffset));
   EXPECT_THAT(IT.getValueFor(I.Operands[8]), IsReg(0));
 }
 
+TEST_F(Core2TargetTest, AllowAsBackToBack) {
+  EXPECT_TRUE(
+      State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr)));
+  EXPECT_FALSE(
+      State.getExegesisTarget().allowAsBackToBack(getInstr(X86::LEA64r)));
+}
+
 } // namespace
 } // namespace exegesis
 } // namespace llvm