Page MenuHomePhabricator

[AArch64][SVE] Add intrinsics for FFR manipulation
ClosedPublic

Authored by kmclaughlin on Jan 21 2020, 5:54 AM.

Details

Summary

Implements the following intrinsics:

  • llvm.aarch64.sve.setffr
  • llvm.aarch64.sve.rdffr
  • llvm.aarch64.sve.rdffr.z
  • llvm.aarch64.sve.wrffr

Diff Detail

Event Timeline

kmclaughlin created this revision.Jan 21 2020, 5:54 AM
Herald added a project: Restricted Project. · View Herald Transcript
efriedma accepted this revision.Jan 21 2020, 9:20 AM

LGTM

I think it's fairly likely that we'll eventually decide that the correct model of the FFR register doesn't require these intrinsics at all. They're just register copies, which is not something we normally model explicitly in IR. Instead, it would be much simpler to reason about the semantics if the faulting load intrinsics took the FFR value explicitly as an operand/result. (clang can lower the ACLE intrinsics onto this model by storing "FFR" into a hidden alloca.)

In the meantime, though, this implementation looks correct, ignoring the issue with FFR getting clobbered we discussed before.

It would be nice if we could use COPY MachineInstrs instead of introducing new pseudo-instructions, but I guess that has the same issue of reading a register that wasn't previously defined.

This revision is now accepted and ready to land.Jan 21 2020, 9:20 AM

Thanks for your input on this @efriedma, I will submit this patch for now and we will revisit the modelling of the FFR as also discussed in D71698

This revision was automatically updated to reflect the committed changes.