[llvm-exegesis] Add support for AVX512 explicit rounding operands.

[courbet]

Check error even when OK (debug mode tests).

[gchatelet]

llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

211

nit: you don't need the cast to bool for ASSERT_FALSE, ASSERT_TRUE

[courbet]

review comments, clang-format

[courbet]

Thanks.

[courbet]

rebase

llvm/tools/llvm-exegesis/lib/X86/Target.cpp

 
 void ExegesisX86Target::randomizeMCOperand(
     const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
     const BitVector &ForbiddenRegs) const {
   ExegesisTarget::randomizeMCOperand(Instr, Var, AssignedValue, ForbiddenRegs);
 
   const Operand &Op = Instr.getPrimaryOperand(Var);
   switch (Op.getExplicitOperandInfo().OperandType) {
+  case X86::OperandType::OPERAND_ROUNDING_CONTROL:
+    AssignedValue =
+        MCOperand::createImm(randomIndex(X86::STATIC_ROUNDING::NO_EXC));
+    break;
   case X86::OperandType::OPERAND_COND_CODE:
     AssignedValue =
         MCOperand::createImm(randomIndex(X86::CondCode::LAST_VALID_COND));
     break;
   default:
     break;
   }
 }

llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

for (const auto &CT : CodeTemplates) {
     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
     ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
   }
 }
 
+TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
+  // - VCVTUSI642SDZrrb_Int
+  // - Op0 Explicit Def RegClass(VR128X)
+  // - Op1 Explicit Use RegClass(VR128X)
+  // - Op2 Explicit Use STATIC_ROUNDING
+  // - Op2 Explicit Use RegClass(GR64)
+  // - Op4 Implicit Use Reg(MXSCR)
+  const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
+  const Instruction &Instr = State.getIC().getInstr(Opcode);
+  auto Configs =
+      Generator.generateConfigurations(Instr, State.getRATC().emptyRegisters());
+  ASSERT_FALSE(Configs.takeError());
+  ASSERT_THAT(*Configs, SizeIs(1));
+  const BenchmarkCode &BC = (*Configs)[0];
+  ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
+  ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
+}
+
 TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) {
   // - BNDCL32rr
   // - Op0 Explicit Use RegClass(BNDR)
   // - Op1 Explicit Use RegClass(GR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   const unsigned Opcode = X86::BNDCL32rr;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);