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AMDGPU: Add option to expand 64-bit integer division in IR
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Authored by arsenm on Jan 20 2020, 4:58 PM.

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Reviewers

Summary

I didn't realize we were already expanding 24/32-bit division here
already. Use the available IntegerDivision utilities. This uses loops,
so produces significantly smaller code than the inline DAG expansion.

This now requires width reductions of 64-bit divisions before
introducing the expanded loops.

This helps work around missing legalization in GlobalISel for
division, which are the only remaining core instructions that didn't
work at all.

I think this is plausibly a better implementation than exists in the
DAG, although turning it on by default misses out on the constant
value optimizations and also needs benchmarking.

Diff Detail

Event Timeline

arsenm created this revision.Jan 20 2020, 4:58 PM

Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2020, 4:58 PM

Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald Transcript

ping

LGTM

This revision is now accepted and ready to land.Jan 29 2020, 10:25 AM

Rebase and fix special cases

Correct patch

rampitec accepted this revision.Feb 11 2020, 2:05 PM

This revision is now accepted and ready to land.Feb 11 2020, 2:05 PM

34d9a16e54becbea4c790b19804d35453018a53f

Revision Contents

Path

Size

llvm/

lib/

Target/

AMDGPU/

AMDGPUCodeGenPrepare.cpp

3 lines

test/

CodeGen/

AMDGPU/

amdgpu-codegenprepare-idiv.ll

581 lines

72 lines

72 lines

47 lines

49 lines

Diff 243986

llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

Show First 20 Lines • Show All 1,132 Lines • ▼ Show 20 Lines	Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
Res = Builder.CreateTrunc(Res, Ty);		Res = Builder.CreateTrunc(Res, Ty);

return Res;		return Res;
}		}

Value *AMDGPUCodeGenPrepare::shrinkDivRem64(IRBuilder<> &Builder,		Value *AMDGPUCodeGenPrepare::shrinkDivRem64(IRBuilder<> &Builder,
BinaryOperator &I,		BinaryOperator &I,
Value Num, Value Den) const {		Value Num, Value Den) const {
		if (!ExpandDiv64InIR && divHasSpecialOptimization(I, Num, Den))
		return nullptr; // Keep it for later optimization.

Instruction::BinaryOps Opc = I.getOpcode();		Instruction::BinaryOps Opc = I.getOpcode();

bool IsDiv = Opc == Instruction::SDiv \|\| Opc == Instruction::UDiv;		bool IsDiv = Opc == Instruction::SDiv \|\| Opc == Instruction::UDiv;
bool IsSigned = Opc == Instruction::SDiv \|\| Opc == Instruction::SRem;		bool IsSigned = Opc == Instruction::SDiv \|\| Opc == Instruction::SRem;

int NumDivBits = getDivNumBits(I, Num, Den, 32, IsSigned);		int NumDivBits = getDivNumBits(I, Num, Den, 32, IsSigned);
if (NumDivBits == -1)		if (NumDivBits == -1)
return nullptr;		return nullptr;
▲ Show 20 Lines • Show All 266 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 5,499 Lines • ▼ Show 20 Lines	; GCN-NEXT: s_endpgm
%shl.y = shl i64 4096, %y		%shl.y = shl i64 4096, %y
%r = udiv i64 %x, %shl.y		%r = udiv i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out		store i64 %r, i64 addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {		define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
; CHECK-LABEL: @udiv_v2i64_pow2k_denom(		; CHECK-LABEL: @udiv_v2i64_pow2k_denom(
; CHECK-NEXT: [[R:%.]] = udiv <2 x i64> [[X:%.]], <i64 4096, i64 4096>		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
		; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
		; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP4]], 4096
		; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: udiv_v2i64_pow2k_denom:		; GCN-LABEL: udiv_v2i64_pow2k_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 12		; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 12
		; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 12
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1		; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2		; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3		; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%r = udiv <2 x i64> %x, <i64 4096, i64 4096>		%r = udiv <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {		define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(		; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom(
; CHECK-NEXT: [[R:%.]] = udiv <2 x i64> [[X:%.]], <i64 4096, i64 4095>		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 4096
		; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
		; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP5:%.*]] = udiv i64 [[TMP4]], 4095
		; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: udiv_v2i64_mixed_pow2k_denom:		; GCN-LABEL: udiv_v2i64_mixed_pow2k_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000		; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000		; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000
; GCN-NEXT: v_rcp_f32_e32 v0, v0		; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: s_movk_i32 s4, 0xf001		; GCN-NEXT: s_movk_i32 s6, 0xf001
; GCN-NEXT: v_mov_b32_e32 v7, 0		; GCN-NEXT: v_mov_b32_e32 v7, 0
; GCN-NEXT: v_mov_b32_e32 v2, 0		; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0		; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0		; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1		; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1		; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0		; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1		; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
		; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
		; GCN-NEXT: s_movk_i32 s0, 0xfff
		; GCN-NEXT: v_mul_hi_u32 v3, v0, s6
		; GCN-NEXT: v_mul_lo_u32 v5, v1, s6
		; GCN-NEXT: v_mul_lo_u32 v4, v0, s6
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_mul_hi_u32 v3, v0, s4
; GCN-NEXT: v_mul_lo_u32 v5, v1, s4
; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3		; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_mul_hi_u32 v6, v0, v4		; GCN-NEXT: v_mul_hi_u32 v6, v0, v4
; GCN-NEXT: v_mul_lo_u32 v5, v0, v3		; GCN-NEXT: v_mul_lo_u32 v5, v0, v3
; GCN-NEXT: v_mul_hi_u32 v8, v0, v3		; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v1, v3		; GCN-NEXT: v_mul_hi_u32 v9, v1, v3
; GCN-NEXT: v_mul_lo_u32 v3, v1, v3		; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5		; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc		; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4		; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4		; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5		; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3		; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_mul_hi_u32 v5, v0, s4		; GCN-NEXT: v_mul_hi_u32 v5, v0, s6
; GCN-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]		; GCN-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
; GCN-NEXT: v_mul_lo_u32 v6, v3, s4		; GCN-NEXT: v_mul_lo_u32 v6, v3, s6
; GCN-NEXT: v_mul_lo_u32 v8, v0, s4		; GCN-NEXT: v_mul_lo_u32 v8, v0, s6
; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5		; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6		; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GCN-NEXT: v_mul_lo_u32 v6, v0, v5		; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
; GCN-NEXT: v_mul_hi_u32 v9, v0, v8		; GCN-NEXT: v_mul_hi_u32 v9, v0, v8
; GCN-NEXT: v_mul_hi_u32 v10, v0, v5		; GCN-NEXT: v_mul_hi_u32 v10, v0, v5
; GCN-NEXT: v_mul_hi_u32 v11, v3, v5		; GCN-NEXT: v_mul_hi_u32 v11, v3, v5
; GCN-NEXT: s_movk_i32 s0, 0xfff
; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6		; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc		; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc
; GCN-NEXT: v_mul_lo_u32 v10, v3, v8		; GCN-NEXT: v_mul_lo_u32 v10, v3, v8
; GCN-NEXT: v_mul_hi_u32 v8, v3, v8		; GCN-NEXT: v_mul_hi_u32 v8, v3, v8
; GCN-NEXT: v_mul_lo_u32 v3, v3, v5		; GCN-NEXT: v_mul_lo_u32 v3, v3, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6		; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v8, vcc		; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v8, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v2, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4		; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]		; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mul_lo_u32 v3, s10, v1		; GCN-NEXT: v_mul_lo_u32 v3, s10, v1
; GCN-NEXT: v_mul_hi_u32 v4, s10, v0		; GCN-NEXT: v_mul_hi_u32 v4, s10, v0
; GCN-NEXT: v_mul_hi_u32 v5, s10, v1		; GCN-NEXT: v_mul_hi_u32 v5, s10, v1
; GCN-NEXT: v_mul_hi_u32 v6, s11, v1		; GCN-NEXT: v_mul_hi_u32 v6, s11, v1
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1		; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0		; GCN-NEXT: v_mul_lo_u32 v5, s11, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0		; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
		; GCN-NEXT: s_lshr_b64 s[2:3], s[8:9], 12
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc		; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v1, s0		; GCN-NEXT: v_mul_lo_u32 v2, v1, s0
; GCN-NEXT: v_mul_hi_u32 v3, v0, s0		; GCN-NEXT: v_mul_hi_u32 v3, v0, s0
; GCN-NEXT: v_mul_lo_u32 v4, v0, s0		; GCN-NEXT: v_mul_lo_u32 v4, v0, s0
Show All 17 Lines
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2		; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3		; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc		; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2		; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
; GCN-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc		; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1]
; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], 12		; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%r = udiv <2 x i64> %x, <i64 4096, i64 4095>		%r = udiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {		define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(		; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(
; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]		; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]
; CHECK-NEXT: [[R:%.]] = udiv <2 x i64> [[X:%.]], [[SHL_Y]]		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
		; CHECK-NEXT: [[TMP3:%.*]] = udiv i64 [[TMP1]], [[TMP2]]
		; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
		; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
		; CHECK-NEXT: [[TMP7:%.*]] = udiv i64 [[TMP5]], [[TMP6]]
		; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: udiv_v2i64_pow2_shl_denom:		; GCN-LABEL: udiv_v2i64_pow2_shl_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11		; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_add_i32 s1, s2, 12
; GCN-NEXT: s_add_i32 s0, s0, 12		; GCN-NEXT: s_add_i32 s0, s0, 12
; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s1		; GCN-NEXT: s_add_i32 s2, s2, 12
; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], s0		; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
		; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1		; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2		; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3		; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y		%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = udiv <2 x i64> %x, %shl.y		%r = udiv <2 x i64> %x, %shl.y
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines	; GCN-NEXT: s_endpgm
%shl.y = shl i64 4096, %y		%shl.y = shl i64 4096, %y
%r = urem i64 %x, %shl.y		%r = urem i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out		store i64 %r, i64 addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {		define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
; CHECK-LABEL: @urem_v2i64_pow2k_denom(		; CHECK-LABEL: @urem_v2i64_pow2k_denom(
; CHECK-NEXT: [[R:%.]] = urem <2 x i64> [[X:%.]], <i64 4096, i64 4096>		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = urem i64 [[TMP1]], 4096
		; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
		; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP5:%.*]] = urem i64 [[TMP4]], 4096
		; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: urem_v2i64_pow2k_denom:		; GCN-LABEL: urem_v2i64_pow2k_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GCN-NEXT: s_movk_i32 s8, 0xfff		; GCN-NEXT: s_movk_i32 s8, 0xfff
; GCN-NEXT: v_mov_b32_e32 v1, 0		; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s1, s2, s8
; GCN-NEXT: s_and_b32 s0, s0, s8		; GCN-NEXT: s_and_b32 s0, s0, s8
		; GCN-NEXT: s_and_b32 s1, s2, s8
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v2, s1		; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: v_mov_b32_e32 v3, v1		; GCN-NEXT: v_mov_b32_e32 v3, v1
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%r = urem <2 x i64> %x, <i64 4096, i64 4096>		%r = urem <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {		define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(		; CHECK-LABEL: @urem_v2i64_pow2_shl_denom(
; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]		; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]
; CHECK-NEXT: [[R:%.]] = urem <2 x i64> [[X:%.]], [[SHL_Y]]		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
		; CHECK-NEXT: [[TMP3:%.*]] = urem i64 [[TMP1]], [[TMP2]]
		; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
		; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
		; CHECK-NEXT: [[TMP7:%.*]] = urem i64 [[TMP5]], [[TMP6]]
		; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: urem_v2i64_pow2_shl_denom:		; GCN-LABEL: urem_v2i64_pow2_shl_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11		; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11
; GCN-NEXT: s_mov_b32 s13, 0		; GCN-NEXT: s_mov_b32 s13, 0
; GCN-NEXT: s_movk_i32 s12, 0x1000		; GCN-NEXT: s_movk_i32 s12, 0x1000
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshl_b64 s[0:1], s[12:13], s0
; GCN-NEXT: s_lshl_b64 s[2:3], s[12:13], s2		; GCN-NEXT: s_lshl_b64 s[2:3], s[12:13], s2
; GCN-NEXT: s_add_u32 s2, s2, -1		; GCN-NEXT: s_lshl_b64 s[0:1], s[12:13], s0
; GCN-NEXT: s_addc_u32 s3, s3, -1
; GCN-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]
; GCN-NEXT: s_add_u32 s0, s0, -1		; GCN-NEXT: s_add_u32 s0, s0, -1
; GCN-NEXT: s_addc_u32 s1, s1, -1		; GCN-NEXT: s_addc_u32 s1, s1, -1
; GCN-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]		; GCN-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1]
		; GCN-NEXT: s_add_u32 s2, s2, -1
		; GCN-NEXT: s_addc_u32 s3, s3, -1
		; GCN-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3]
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1		; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2		; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3		; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y		%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = urem <2 x i64> %x, %shl.y		%r = urem <2 x i64> %x, %shl.y
▲ Show 20 Lines • Show All 309 Lines • ▼ Show 20 Lines	; GCN-NEXT: s_endpgm
%shl.y = shl i64 4096, %y		%shl.y = shl i64 4096, %y
%r = sdiv i64 %x, %shl.y		%r = sdiv i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out		store i64 %r, i64 addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {		define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(		; CHECK-LABEL: @sdiv_v2i64_pow2k_denom(
; CHECK-NEXT: [[R:%.]] = sdiv <2 x i64> [[X:%.]], <i64 4096, i64 4096>		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
		; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
		; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4096
		; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: sdiv_v2i64_pow2k_denom:		; GCN-LABEL: sdiv_v2i64_pow2k_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s8, s3, 31
; GCN-NEXT: s_lshr_b32 s8, s8, 20
; GCN-NEXT: s_add_u32 s2, s2, s8
; GCN-NEXT: s_addc_u32 s3, s3, 0
; GCN-NEXT: s_ashr_i32 s8, s1, 31		; GCN-NEXT: s_ashr_i32 s8, s1, 31
; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
; GCN-NEXT: s_lshr_b32 s8, s8, 20		; GCN-NEXT: s_lshr_b32 s8, s8, 20
; GCN-NEXT: s_add_u32 s0, s0, s8		; GCN-NEXT: s_add_u32 s0, s0, s8
; GCN-NEXT: s_addc_u32 s1, s1, 0		; GCN-NEXT: s_addc_u32 s1, s1, 0
		; GCN-NEXT: s_ashr_i32 s8, s3, 31
; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12		; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
		; GCN-NEXT: s_lshr_b32 s8, s8, 20
		; GCN-NEXT: s_add_u32 s2, s2, s8
		; GCN-NEXT: s_addc_u32 s3, s3, 0
		; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1		; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2		; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3		; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%r = sdiv <2 x i64> %x, <i64 4096, i64 4096>		%r = sdiv <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {		define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(		; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom(
; CHECK-NEXT: [[R:%.]] = sdiv <2 x i64> [[X:%.]], <i64 4096, i64 4095>		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = sdiv i64 [[TMP1]], 4096
		; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
		; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP5:%.*]] = sdiv i64 [[TMP4]], 4095
		; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: ssdiv_v2i64_mixed_pow2k_denom:		; GCN-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000		; GCN-NEXT: v_mov_b32_e32 v0, 0x457ff000
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000		; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000
		; GCN-NEXT: v_mac_f32_e32 v0, 0, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0		; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: s_movk_i32 s6, 0xf001		; GCN-NEXT: s_movk_i32 s6, 0xf001
; GCN-NEXT: v_mov_b32_e32 v7, 0		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: v_mov_b32_e32 v5, 0		; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0		; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0		; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1		; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1		; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0		; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1		; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd		; GCN-NEXT: s_ashr_i32 s0, s9, 31
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_lshr_b32 s0, s0, 20
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0		; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
; GCN-NEXT: v_mul_lo_u32 v2, v1, s6		; GCN-NEXT: v_mul_lo_u32 v3, v1, s6
; GCN-NEXT: v_mul_lo_u32 v4, v0, s6		; GCN-NEXT: s_add_u32 s2, s8, s0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: s_addc_u32 s3, s9, 0
		; GCN-NEXT: s_ashr_i32 s8, s11, 31
		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
		; GCN-NEXT: v_mul_lo_u32 v3, v0, s6
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2		; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
; GCN-NEXT: v_mul_hi_u32 v3, v0, v4		; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
; GCN-NEXT: v_mul_lo_u32 v6, v0, v2		; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
; GCN-NEXT: v_mul_hi_u32 v8, v0, v2		; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
; GCN-NEXT: v_mul_hi_u32 v9, v1, v2		; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2		; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6		; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc		; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4		; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4		; GCN-NEXT: v_mul_lo_u32 v6, v1, v3
; GCN-NEXT: v_add_i32_e32 v3, vcc, v8, v3		; GCN-NEXT: v_mul_hi_u32 v3, v1, v3
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc		; GCN-NEXT: s_mov_b32 s9, s8
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v4, vcc
; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
; GCN-NEXT: v_mul_lo_u32 v4, v2, s6
; GCN-NEXT: v_mul_hi_u32 v6, s6, v0
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4		; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; GCN-NEXT: v_mul_lo_u32 v6, v0, s6		; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4		; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_mul_lo_u32 v10, v0, v4		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GCN-NEXT: v_mul_hi_u32 v12, v0, v4		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mul_hi_u32 v11, v0, v6		; GCN-NEXT: v_mov_b32_e32 v6, 0
; GCN-NEXT: v_mul_hi_u32 v9, v2, v6		; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2
; GCN-NEXT: v_mul_lo_u32 v6, v2, v6		; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
; GCN-NEXT: v_mul_hi_u32 v8, v2, v4		; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
		; GCN-NEXT: v_mul_lo_u32 v5, v2, s6
		; GCN-NEXT: v_mul_hi_u32 v7, s6, v0
		; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
		; GCN-NEXT: v_mul_lo_u32 v7, v0, s6
		; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5
		; GCN-NEXT: v_mul_lo_u32 v10, v0, v5
		; GCN-NEXT: v_mul_hi_u32 v12, v0, v5
		; GCN-NEXT: v_mul_hi_u32 v11, v0, v7
		; GCN-NEXT: v_mul_hi_u32 v9, v2, v7
		; GCN-NEXT: v_mul_lo_u32 v7, v2, v7
		; GCN-NEXT: v_mul_hi_u32 v8, v2, v5
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10		; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc		; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v2, v4		; GCN-NEXT: v_mul_lo_u32 v2, v2, v5
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10		; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc		; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v6, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3		; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]		; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_add_u32 s0, s10, s8
; GCN-NEXT: s_ashr_i32 s2, s11, 31		; GCN-NEXT: s_addc_u32 s1, s11, s8
; GCN-NEXT: s_add_u32 s0, s10, s2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: s_mov_b32 s3, s2		; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[8:9]
; GCN-NEXT: s_addc_u32 s1, s11, s2
; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s0, v1		; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
; GCN-NEXT: v_mul_hi_u32 v3, s0, v0		; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
; GCN-NEXT: v_mul_hi_u32 v4, s0, v1		; GCN-NEXT: v_mul_hi_u32 v5, s0, v1
; GCN-NEXT: v_mul_hi_u32 v6, s1, v1		; GCN-NEXT: v_mul_hi_u32 v7, s1, v1
; GCN-NEXT: v_mul_lo_u32 v1, s1, v1		; GCN-NEXT: v_mul_lo_u32 v1, s1, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s1, v0		; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
; GCN-NEXT: v_mul_hi_u32 v0, s1, v0		; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
; GCN-NEXT: s_movk_i32 s3, 0xfff		; GCN-NEXT: s_movk_i32 s9, 0xfff
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc		; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v2, v1, s3		; GCN-NEXT: v_mul_lo_u32 v2, v1, s9
; GCN-NEXT: v_mul_hi_u32 v3, s3, v0		; GCN-NEXT: v_mul_hi_u32 v3, s9, v0
; GCN-NEXT: v_mul_lo_u32 v4, v0, s3		; GCN-NEXT: v_mul_lo_u32 v4, v0, s9
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4		; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4
; GCN-NEXT: v_mov_b32_e32 v3, s1		; GCN-NEXT: v_mov_b32_e32 v3, s1
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc		; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc
; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4		; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s9, v4
; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc		; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
; GCN-NEXT: s_movk_i32 s0, 0xffe		; GCN-NEXT: s_movk_i32 s0, 0xffe
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3		; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5		; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc		; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0		; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc		; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc
; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0		; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0
; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4		; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4
; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc		; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2		; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3		; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2		; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2
; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc		; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
; GCN-NEXT: s_ashr_i32 s0, s9, 31		; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc
; GCN-NEXT: s_lshr_b32 s0, s0, 20		; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
; GCN-NEXT: s_add_u32 s0, s8, s0		; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
; GCN-NEXT: s_addc_u32 s1, s9, 0		; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s8, v0
; GCN-NEXT: v_xor_b32_e32 v0, s2, v0		; GCN-NEXT: v_xor_b32_e32 v1, s8, v1
; GCN-NEXT: v_xor_b32_e32 v1, s2, v1		; GCN-NEXT: v_mov_b32_e32 v3, s8
; GCN-NEXT: v_mov_b32_e32 v3, s2
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0
; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc		; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s2
; GCN-NEXT: v_mov_b32_e32 v1, s1		; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%r = sdiv <2 x i64> %x, <i64 4096, i64 4095>		%r = sdiv <2 x i64> %x, <i64 4096, i64 4095>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {		define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(		; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom(
; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]		; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]
; CHECK-NEXT: [[R:%.]] = sdiv <2 x i64> [[X:%.]], [[SHL_Y]]		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
		; CHECK-NEXT: [[TMP3:%.*]] = sdiv i64 [[TMP1]], [[TMP2]]
		; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
		; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
		; CHECK-NEXT: [[TMP7:%.*]] = sdiv i64 [[TMP5]], [[TMP6]]
		; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: sdiv_v2i64_pow2_shl_denom:		; GCN-LABEL: sdiv_v2i64_pow2_shl_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11		; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
; GCN-NEXT: s_mov_b32 s3, 0		; GCN-NEXT: s_mov_b32 s3, 0
; GCN-NEXT: s_movk_i32 s2, 0x1000		; GCN-NEXT: s_movk_i32 s2, 0x1000
; GCN-NEXT: s_mov_b32 s18, 0x4f800000		; GCN-NEXT: s_mov_b32 s18, 0x4f800000
; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc		; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshl_b64 s[12:13], s[2:3], s4		; GCN-NEXT: s_lshl_b64 s[12:13], s[2:3], s6
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6		; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GCN-NEXT: s_ashr_i32 s16, s3, 31		; GCN-NEXT: s_ashr_i32 s16, s3, 31
; GCN-NEXT: s_add_u32 s2, s2, s16		; GCN-NEXT: s_add_u32 s2, s2, s16
; GCN-NEXT: s_mov_b32 s17, s16		; GCN-NEXT: s_mov_b32 s17, s16
; GCN-NEXT: s_addc_u32 s3, s3, s16		; GCN-NEXT: s_addc_u32 s3, s3, s16
; GCN-NEXT: s_xor_b64 s[14:15], s[2:3], s[16:17]		; GCN-NEXT: s_xor_b64 s[14:15], s[2:3], s[16:17]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s14		; GCN-NEXT: v_cvt_f32_u32_e32 v0, s14
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s15		; GCN-NEXT: v_cvt_f32_u32_e32 v1, s15
; GCN-NEXT: s_mov_b32 s20, 0x2f800000		; GCN-NEXT: s_mov_b32 s20, 0x2f800000
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10		; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc		; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3		; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]		; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s2, s11, 31		; GCN-NEXT: s_ashr_i32 s2, s9, 31
; GCN-NEXT: s_add_u32 s0, s10, s2		; GCN-NEXT: s_add_u32 s0, s8, s2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: s_mov_b32 s3, s2		; GCN-NEXT: s_mov_b32 s3, s2
; GCN-NEXT: s_addc_u32 s1, s11, s2		; GCN-NEXT: s_addc_u32 s1, s9, s2
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3]		; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3]
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s10, v1		; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
; GCN-NEXT: v_mul_hi_u32 v3, s10, v0		; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
; GCN-NEXT: v_mul_hi_u32 v5, s10, v1		; GCN-NEXT: v_mul_hi_u32 v5, s8, v1
; GCN-NEXT: v_mul_hi_u32 v7, s11, v1		; GCN-NEXT: v_mul_hi_u32 v7, s9, v1
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1		; GCN-NEXT: v_mul_lo_u32 v1, s9, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0		; GCN-NEXT: v_mul_lo_u32 v5, s9, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0		; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]		; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17]
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc		; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s14, v1		; GCN-NEXT: v_mul_lo_u32 v2, s14, v1
; GCN-NEXT: v_mul_hi_u32 v3, s14, v0		; GCN-NEXT: v_mul_hi_u32 v3, s14, v0
; GCN-NEXT: v_mul_lo_u32 v5, s15, v0		; GCN-NEXT: v_mul_lo_u32 v5, s15, v0
; GCN-NEXT: v_mov_b32_e32 v7, s15		; GCN-NEXT: v_mov_b32_e32 v7, s15
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mul_lo_u32 v3, s14, v0		; GCN-NEXT: v_mul_lo_u32 v3, s14, v0
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; GCN-NEXT: v_sub_i32_e32 v5, vcc, s11, v2		; GCN-NEXT: v_sub_i32_e32 v5, vcc, s9, v2
; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3		; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v3
; GCN-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v7, vcc		; GCN-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v3		; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v3
; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]		; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v5		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v5
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v5		; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v5
; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v7, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v7, s[0:1]
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0		; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]		; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v0		; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v0
; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]		; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
; GCN-NEXT: s_ashr_i32 s10, s13, 31		; GCN-NEXT: s_ashr_i32 s8, s13, 31
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5		; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5
; GCN-NEXT: s_add_u32 s12, s12, s10		; GCN-NEXT: s_add_u32 s12, s12, s8
; GCN-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v8, s11		; GCN-NEXT: v_mov_b32_e32 v8, s9
; GCN-NEXT: s_mov_b32 s11, s10		; GCN-NEXT: s_mov_b32 s9, s8
; GCN-NEXT: s_addc_u32 s13, s13, s10		; GCN-NEXT: s_addc_u32 s13, s13, s8
; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11]		; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[8:9]
; GCN-NEXT: v_cvt_f32_u32_e32 v10, s12		; GCN-NEXT: v_cvt_f32_u32_e32 v10, s12
; GCN-NEXT: v_cvt_f32_u32_e32 v11, s13		; GCN-NEXT: v_cvt_f32_u32_e32 v11, s13
; GCN-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc		; GCN-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s15, v2		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s15, v2
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v3		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v3
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2		; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc		; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc
; GCN-NEXT: v_mul_lo_u32 v3, v3, v8		; GCN-NEXT: v_mul_lo_u32 v3, v3, v8
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12		; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc		; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc		; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7		; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: s_ashr_i32 s14, s9, 31		; GCN-NEXT: s_ashr_i32 s14, s11, 31
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]		; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
; GCN-NEXT: s_add_u32 s0, s8, s14		; GCN-NEXT: s_add_u32 s0, s10, s14
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: s_mov_b32 s15, s14		; GCN-NEXT: s_mov_b32 s15, s14
; GCN-NEXT: s_addc_u32 s1, s9, s14		; GCN-NEXT: s_addc_u32 s1, s11, s14
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15]		; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s8, v3		; GCN-NEXT: v_mul_lo_u32 v5, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s8, v2		; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
; GCN-NEXT: v_mul_hi_u32 v9, s8, v3		; GCN-NEXT: v_mul_hi_u32 v9, s10, v3
; GCN-NEXT: v_mul_hi_u32 v10, s9, v3		; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s9, v3		; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5		; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc		; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v9, s9, v2		; GCN-NEXT: v_mul_lo_u32 v9, s11, v2
; GCN-NEXT: v_mul_hi_u32 v2, s9, v2		; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
; GCN-NEXT: v_mov_b32_e32 v8, s3		; GCN-NEXT: v_mov_b32_e32 v8, s3
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5		; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v3		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v6, s12, v4		; GCN-NEXT: v_mul_lo_u32 v4, s12, v3
; GCN-NEXT: v_mul_hi_u32 v7, s12, v5		; GCN-NEXT: v_mul_hi_u32 v5, s12, v2
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0		; GCN-NEXT: v_mul_lo_u32 v6, s13, v2
; GCN-NEXT: v_mul_lo_u32 v0, s13, v5		; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v8, vcc		; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v7, v6		; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
		; GCN-NEXT: v_mul_lo_u32 v5, s12, v2
		; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
		; GCN-NEXT: v_sub_i32_e32 v6, vcc, s11, v4
; GCN-NEXT: v_mov_b32_e32 v7, s13		; GCN-NEXT: v_mov_b32_e32 v7, s13
; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0		; GCN-NEXT: v_sub_i32_e32 v5, vcc, s10, v5
; GCN-NEXT: v_mul_lo_u32 v1, s12, v5
; GCN-NEXT: v_sub_i32_e32 v6, vcc, s9, v0
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1
; GCN-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc		; GCN-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v1		; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v5
; GCN-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]		; GCN-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6		; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6
; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1]
; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v5		; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2
; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1]		; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v5		; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2
; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1]		; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6		; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v8, s9		; GCN-NEXT: v_mov_b32_e32 v8, s11
; GCN-NEXT: v_subb_u32_e32 v0, vcc, v8, v0, vcc		; GCN-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v0		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v4
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v1		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v5
; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v0		; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v4
; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc		; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0		; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc		; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[10:11]		; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[8:9]
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc		; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
; GCN-NEXT: v_xor_b32_e32 v1, s0, v1		; GCN-NEXT: v_xor_b32_e32 v2, s0, v2
; GCN-NEXT: v_xor_b32_e32 v4, s1, v0		; GCN-NEXT: v_xor_b32_e32 v3, s1, v3
; GCN-NEXT: v_mov_b32_e32 v5, s1		; GCN-NEXT: v_mov_b32_e32 v4, s1
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v1		; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v5, vcc		; GCN-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y		%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = sdiv <2 x i64> %x, %shl.y		%r = sdiv <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

▲ Show 20 Lines • Show All 303 Lines • ▼ Show 20 Lines	; GCN-NEXT: s_endpgm
%shl.y = shl i64 4096, %y		%shl.y = shl i64 4096, %y
%r = srem i64 %x, %shl.y		%r = srem i64 %x, %shl.y
store i64 %r, i64 addrspace(1)* %out		store i64 %r, i64 addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {		define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) {
; CHECK-LABEL: @srem_v2i64_pow2k_denom(		; CHECK-LABEL: @srem_v2i64_pow2k_denom(
; CHECK-NEXT: [[R:%.]] = srem <2 x i64> [[X:%.]], <i64 4096, i64 4096>		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = srem i64 [[TMP1]], 4096
		; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i64 0
		; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP5:%.*]] = srem i64 [[TMP4]], 4096
		; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP3]], i64 [[TMP5]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: srem_v2i64_pow2k_denom:		; GCN-LABEL: srem_v2i64_pow2k_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd
; GCN-NEXT: s_movk_i32 s8, 0xf000		; GCN-NEXT: s_movk_i32 s8, 0xf000
; GCN-NEXT: s_mov_b32 s7, 0xf000		; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s9, s3, 31
; GCN-NEXT: s_lshr_b32 s9, s9, 20
; GCN-NEXT: s_add_u32 s9, s2, s9
; GCN-NEXT: s_addc_u32 s10, s3, 0
; GCN-NEXT: s_and_b32 s9, s9, s8
; GCN-NEXT: s_sub_u32 s2, s2, s9
; GCN-NEXT: s_subb_u32 s3, s3, s10
; GCN-NEXT: s_ashr_i32 s9, s1, 31		; GCN-NEXT: s_ashr_i32 s9, s1, 31
; GCN-NEXT: s_lshr_b32 s9, s9, 20		; GCN-NEXT: s_lshr_b32 s9, s9, 20
; GCN-NEXT: s_add_u32 s9, s0, s9		; GCN-NEXT: s_add_u32 s9, s0, s9
; GCN-NEXT: s_addc_u32 s10, s1, 0		; GCN-NEXT: s_addc_u32 s10, s1, 0
; GCN-NEXT: s_and_b32 s8, s9, s8		; GCN-NEXT: s_and_b32 s9, s9, s8
; GCN-NEXT: s_sub_u32 s0, s0, s8		; GCN-NEXT: s_sub_u32 s0, s0, s9
; GCN-NEXT: s_subb_u32 s1, s1, s10		; GCN-NEXT: s_subb_u32 s1, s1, s10
		; GCN-NEXT: s_ashr_i32 s9, s3, 31
		; GCN-NEXT: s_lshr_b32 s9, s9, 20
		; GCN-NEXT: s_add_u32 s9, s2, s9
		; GCN-NEXT: s_addc_u32 s10, s3, 0
		; GCN-NEXT: s_and_b32 s8, s9, s8
		; GCN-NEXT: s_sub_u32 s2, s2, s8
		; GCN-NEXT: s_subb_u32 s3, s3, s10
; GCN-NEXT: v_mov_b32_e32 v0, s0		; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1		; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: v_mov_b32_e32 v2, s2		; GCN-NEXT: v_mov_b32_e32 v2, s2
; GCN-NEXT: v_mov_b32_e32 v3, s3		; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%r = srem <2 x i64> %x, <i64 4096, i64 4096>		%r = srem <2 x i64> %x, <i64 4096, i64 4096>
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {		define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(		; CHECK-LABEL: @srem_v2i64_pow2_shl_denom(
; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]		; CHECK-NEXT: [[SHL_Y:%.]] = shl <2 x i64> <i64 4096, i64 4096>, [[Y:%.]]
; CHECK-NEXT: [[R:%.]] = srem <2 x i64> [[X:%.]], [[SHL_Y]]		; CHECK-NEXT: [[TMP1:%.]] = extractelement <2 x i64> [[X:%.]], i64 0
; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]]		; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 0
		; CHECK-NEXT: [[TMP3:%.*]] = srem i64 [[TMP1]], [[TMP2]]
		; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i64 0
		; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[X]], i64 1
		; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i64> [[SHL_Y]], i64 1
		; CHECK-NEXT: [[TMP7:%.*]] = srem i64 [[TMP5]], [[TMP6]]
		; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP7]], i64 1
		; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]]
; CHECK-NEXT: ret void		; CHECK-NEXT: ret void
;		;
; GCN-LABEL: srem_v2i64_pow2_shl_denom:		; GCN-LABEL: srem_v2i64_pow2_shl_denom:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11		; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11
; GCN-NEXT: s_mov_b32 s3, 0		; GCN-NEXT: s_mov_b32 s3, 0
; GCN-NEXT: s_movk_i32 s2, 0x1000		; GCN-NEXT: s_movk_i32 s2, 0x1000
; GCN-NEXT: s_mov_b32 s18, 0x4f800000		; GCN-NEXT: s_mov_b32 s18, 0x4f800000
; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc		; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s4		; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s6
; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6		; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
; GCN-NEXT: s_ashr_i32 s4, s3, 31		; GCN-NEXT: s_ashr_i32 s4, s3, 31
; GCN-NEXT: s_add_u32 s2, s2, s4		; GCN-NEXT: s_add_u32 s2, s2, s4
; GCN-NEXT: s_mov_b32 s5, s4		; GCN-NEXT: s_mov_b32 s5, s4
; GCN-NEXT: s_addc_u32 s3, s3, s4		; GCN-NEXT: s_addc_u32 s3, s3, s4
; GCN-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5]		; GCN-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16		; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s17		; GCN-NEXT: v_cvt_f32_u32_e32 v1, s17
; GCN-NEXT: s_mov_b32 s20, 0x2f800000		; GCN-NEXT: s_mov_b32 s20, 0x2f800000
; GCN-NEXT: s_mov_b32 s21, 0xcf800000		; GCN-NEXT: s_mov_b32 s21, 0xcf800000
; GCN-NEXT: s_sub_u32 s6, 0, s16		; GCN-NEXT: s_sub_u32 s6, 0, s16
; GCN-NEXT: v_mac_f32_e32 v0, s18, v1		; GCN-NEXT: v_mac_f32_e32 v0, s18, v1
; GCN-NEXT: v_rcp_f32_e32 v0, v0		; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: s_subb_u32 s7, 0, s17		; GCN-NEXT: s_subb_u32 s7, 0, s17
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9		; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd		; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd
; GCN-NEXT: v_mul_f32_e32 v0, s19, v0		; GCN-NEXT: v_mul_f32_e32 v0, s19, v0
; GCN-NEXT: v_mul_f32_e32 v1, s20, v0		; GCN-NEXT: v_mul_f32_e32 v1, s20, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1		; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mac_f32_e32 v0, s21, v1		; GCN-NEXT: v_mac_f32_e32 v0, s21, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0		; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1		; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)		; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_ashr_i32 s12, s11, 31		; GCN-NEXT: s_ashr_i32 s12, s9, 31
; GCN-NEXT: s_add_u32 s0, s10, s12		; GCN-NEXT: s_add_u32 s0, s8, s12
; GCN-NEXT: v_mul_hi_u32 v3, s6, v0		; GCN-NEXT: v_mul_hi_u32 v3, s6, v0
; GCN-NEXT: v_mul_lo_u32 v2, s6, v1		; GCN-NEXT: v_mul_lo_u32 v2, s6, v1
; GCN-NEXT: v_mul_lo_u32 v4, s7, v0		; GCN-NEXT: v_mul_lo_u32 v4, s7, v0
; GCN-NEXT: v_mul_lo_u32 v5, s6, v0		; GCN-NEXT: v_mul_lo_u32 v5, s6, v0
; GCN-NEXT: s_mov_b32 s13, s12		; GCN-NEXT: s_mov_b32 s13, s12
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GCN-NEXT: v_mul_lo_u32 v3, v0, v2		; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
; GCN-NEXT: v_mul_hi_u32 v4, v0, v5		; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
; GCN-NEXT: v_mul_hi_u32 v6, v0, v2		; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
; GCN-NEXT: v_mul_hi_u32 v7, v1, v2		; GCN-NEXT: v_mul_hi_u32 v7, v1, v2
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2		; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc		; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc
; GCN-NEXT: v_mul_lo_u32 v6, v1, v5		; GCN-NEXT: v_mul_lo_u32 v6, v1, v5
; GCN-NEXT: v_mul_hi_u32 v5, v1, v5		; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
; GCN-NEXT: s_addc_u32 s1, s11, s12		; GCN-NEXT: s_addc_u32 s1, s9, s12
; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[12:13]		; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13]
; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc
; GCN-NEXT: v_mov_b32_e32 v4, 0		; GCN-NEXT: v_mov_b32_e32 v4, 0
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_mov_b32_e32 v6, 0		; GCN-NEXT: v_mov_b32_e32 v6, 0
; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2		; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc
Show All 18 Lines
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc		; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc
; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3		; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]		; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_mul_lo_u32 v2, s10, v1		; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
; GCN-NEXT: v_mul_hi_u32 v3, s10, v0		; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
; GCN-NEXT: v_mul_hi_u32 v5, s10, v1		; GCN-NEXT: v_mul_hi_u32 v5, s8, v1
; GCN-NEXT: v_mul_hi_u32 v7, s11, v1		; GCN-NEXT: v_mul_hi_u32 v7, s9, v1
; GCN-NEXT: v_mul_lo_u32 v1, s11, v1		; GCN-NEXT: v_mul_lo_u32 v1, s9, v1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s11, v0		; GCN-NEXT: v_mul_lo_u32 v5, s9, v0
; GCN-NEXT: v_mul_hi_u32 v0, s11, v0		; GCN-NEXT: v_mul_hi_u32 v0, s9, v0
; GCN-NEXT: s_mov_b32 s6, -1		; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2		; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc		; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc
; GCN-NEXT: v_mul_lo_u32 v1, s16, v1		; GCN-NEXT: v_mul_lo_u32 v1, s16, v1
; GCN-NEXT: v_mul_hi_u32 v2, s16, v0		; GCN-NEXT: v_mul_hi_u32 v2, s16, v0
; GCN-NEXT: v_mul_lo_u32 v3, s17, v0		; GCN-NEXT: v_mul_lo_u32 v3, s17, v0
; GCN-NEXT: v_mul_lo_u32 v0, s16, v0		; GCN-NEXT: v_mul_lo_u32 v0, s16, v0
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1		; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3		; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1		; GCN-NEXT: v_sub_i32_e32 v2, vcc, s9, v1
; GCN-NEXT: v_mov_b32_e32 v3, s17		; GCN-NEXT: v_mov_b32_e32 v3, s17
; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0		; GCN-NEXT: v_sub_i32_e32 v0, vcc, s8, v0
; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc		; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v0		; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v0
; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1]		; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1]
; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]		; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s17, v2		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s17, v2
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s16, v5		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s16, v5
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s17, v2		; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s17, v2
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1]
; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s16, v5		; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s16, v5
; GCN-NEXT: s_ashr_i32 s2, s15, 31		; GCN-NEXT: s_ashr_i32 s2, s15, 31
; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]		; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7		; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GCN-NEXT: s_add_u32 s10, s14, s2		; GCN-NEXT: s_add_u32 s8, s14, s2
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v3, s11		; GCN-NEXT: v_mov_b32_e32 v3, s9
; GCN-NEXT: s_mov_b32 s3, s2		; GCN-NEXT: s_mov_b32 s3, s2
; GCN-NEXT: s_addc_u32 s11, s15, s2		; GCN-NEXT: s_addc_u32 s9, s15, s2
; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[2:3]		; GCN-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
; GCN-NEXT: v_cvt_f32_u32_e32 v7, s10		; GCN-NEXT: v_cvt_f32_u32_e32 v7, s8
; GCN-NEXT: v_cvt_f32_u32_e32 v9, s11		; GCN-NEXT: v_cvt_f32_u32_e32 v9, s9
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc		; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s17, v1		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s17, v1
; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
; GCN-NEXT: v_mac_f32_e32 v7, s18, v9		; GCN-NEXT: v_mac_f32_e32 v7, s18, v9
; GCN-NEXT: v_rcp_f32_e32 v7, v7		; GCN-NEXT: v_rcp_f32_e32 v7, v7
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s16, v0		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s16, v0
; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s17, v1		; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s17, v1
; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc		; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3		; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; GCN-NEXT: v_mul_f32_e32 v3, s19, v7		; GCN-NEXT: v_mul_f32_e32 v3, s19, v7
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc		; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v8, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v8, s[0:1]
; GCN-NEXT: v_mul_f32_e32 v5, s20, v3		; GCN-NEXT: v_mul_f32_e32 v5, s20, v3
; GCN-NEXT: v_trunc_f32_e32 v5, v5		; GCN-NEXT: v_trunc_f32_e32 v5, v5
; GCN-NEXT: v_mac_f32_e32 v3, s21, v5		; GCN-NEXT: v_mac_f32_e32 v3, s21, v5
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3		; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5		; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
; GCN-NEXT: s_sub_u32 s2, 0, s10		; GCN-NEXT: s_sub_u32 s2, 0, s8
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc		; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_mul_hi_u32 v2, s2, v3		; GCN-NEXT: v_mul_hi_u32 v2, s2, v3
; GCN-NEXT: v_mul_lo_u32 v7, s2, v5		; GCN-NEXT: v_mul_lo_u32 v7, s2, v5
; GCN-NEXT: s_subb_u32 s3, 0, s11		; GCN-NEXT: s_subb_u32 s3, 0, s9
; GCN-NEXT: v_mul_lo_u32 v8, s3, v3		; GCN-NEXT: v_mul_lo_u32 v8, s3, v3
; GCN-NEXT: s_ashr_i32 s14, s9, 31		; GCN-NEXT: s_ashr_i32 s14, s11, 31
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GCN-NEXT: v_mul_lo_u32 v7, s2, v3		; GCN-NEXT: v_mul_lo_u32 v7, s2, v3
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GCN-NEXT: v_mul_lo_u32 v8, v3, v2		; GCN-NEXT: v_mul_lo_u32 v8, v3, v2
; GCN-NEXT: v_mul_hi_u32 v10, v3, v2		; GCN-NEXT: v_mul_hi_u32 v10, v3, v2
; GCN-NEXT: v_mul_hi_u32 v9, v3, v7		; GCN-NEXT: v_mul_hi_u32 v9, v3, v7
; GCN-NEXT: v_mul_hi_u32 v11, v5, v2		; GCN-NEXT: v_mul_hi_u32 v11, v5, v2
; GCN-NEXT: v_mul_lo_u32 v2, v5, v2		; GCN-NEXT: v_mul_lo_u32 v2, v5, v2
Show All 28 Lines
; GCN-NEXT: v_mul_lo_u32 v3, v3, v8		; GCN-NEXT: v_mul_lo_u32 v3, v3, v8
; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12		; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc		; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc
; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3		; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc		; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7		; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]		; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
; GCN-NEXT: s_add_u32 s0, s8, s14		; GCN-NEXT: s_add_u32 s0, s10, s14
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: s_addc_u32 s1, s9, s14		; GCN-NEXT: s_addc_u32 s1, s11, s14
; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15]		; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15]
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
; GCN-NEXT: v_mul_lo_u32 v5, s8, v3		; GCN-NEXT: v_mul_lo_u32 v5, s10, v3
; GCN-NEXT: v_mul_hi_u32 v7, s8, v2		; GCN-NEXT: v_mul_hi_u32 v7, s10, v2
; GCN-NEXT: v_mul_hi_u32 v9, s8, v3		; GCN-NEXT: v_mul_hi_u32 v9, s10, v3
; GCN-NEXT: v_mul_hi_u32 v10, s9, v3		; GCN-NEXT: v_mul_hi_u32 v10, s11, v3
; GCN-NEXT: v_mul_lo_u32 v3, s9, v3		; GCN-NEXT: v_mul_lo_u32 v3, s11, v3
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5		; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc		; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
; GCN-NEXT: v_mul_lo_u32 v9, s9, v2		; GCN-NEXT: v_mul_lo_u32 v9, s11, v2
; GCN-NEXT: v_mul_hi_u32 v2, s9, v2		; GCN-NEXT: v_mul_hi_u32 v2, s11, v2
; GCN-NEXT: v_mov_b32_e32 v8, s12		; GCN-NEXT: v_mov_b32_e32 v8, s12
; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5		; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc		; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc
; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v3		; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc		; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc
; GCN-NEXT: v_mul_lo_u32 v4, s10, v2		; GCN-NEXT: v_mul_lo_u32 v3, s8, v3
; GCN-NEXT: v_mul_hi_u32 v6, s10, v5		; GCN-NEXT: v_mul_hi_u32 v4, s8, v2
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s12, v0		; GCN-NEXT: v_mul_lo_u32 v5, s9, v2
; GCN-NEXT: v_mul_lo_u32 v0, s11, v5		; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0
; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v8, vcc		; GCN-NEXT: v_mul_lo_u32 v2, s8, v2
; GCN-NEXT: v_add_i32_e32 v1, vcc, v6, v4		; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0		; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-NEXT: v_mul_lo_u32 v1, s10, v5		; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
; GCN-NEXT: v_sub_i32_e32 v4, vcc, s9, v0		; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v3
; GCN-NEXT: v_mov_b32_e32 v5, s11		; GCN-NEXT: v_mov_b32_e32 v5, s9
; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1		; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2
; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc		; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s10, v1		; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v2
; GCN-NEXT: v_subb_u32_e64 v5, s[2:3], v4, v5, s[0:1]		; GCN-NEXT: v_subb_u32_e64 v5, s[2:3], v4, v5, s[0:1]
; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]		; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6		; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v6
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1]
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4		; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1]
; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s10, v6		; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s8, v6
; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]		; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7		; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v5, s9		; GCN-NEXT: v_mov_b32_e32 v5, s11
; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc		; GCN-NEXT: v_subb_u32_e32 v3, vcc, v5, v3, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v0		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v1		; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v2
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc		; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v0		; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3
; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc		; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5		; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc		; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[0:1]		; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[0:1]
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc		; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_xor_b32_e32 v1, s14, v1		; GCN-NEXT: v_xor_b32_e32 v2, s14, v2
; GCN-NEXT: v_xor_b32_e32 v4, s14, v0		; GCN-NEXT: v_xor_b32_e32 v3, s14, v3
; GCN-NEXT: v_mov_b32_e32 v5, s14		; GCN-NEXT: v_mov_b32_e32 v4, s14
; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s14, v1		; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s14, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v5, vcc		; GCN-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0		; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GCN-NEXT: s_endpgm		; GCN-NEXT: s_endpgm
%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y		%shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
%r = srem <2 x i64> %x, %shl.y		%r = srem <2 x i64> %x, %shl.y
store <2 x i64> %r, <2 x i64> addrspace(1)* %out		store <2 x i64> %r, <2 x i64> addrspace(1)* %out
ret void		ret void
}		}

llvm/test/CodeGen/AMDGPU/sdiv64.ll

	Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
	; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]			; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB1_6			; GCN-IR-NEXT: s_cbranch_execz BB1_6
	; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1			; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
	; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v8			; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v8
	; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, 0, v9, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, 0, v9, vcc
	; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 63, v8			; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 63, v8
	; GCN-IR-NEXT: s_mov_b64 s[8:9], 0			; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
	; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[8:9]			; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[8:9]
	; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[12:13], v10			; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[12:13], v10
	; GCN-IR-NEXT: v_mov_b32_e32 v10, 0			; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v11, 0			; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
	; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc			; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
	; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]			; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB1_5			; GCN-IR-NEXT: s_cbranch_execz BB1_5
	; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader			; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
	; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[12:13], v2			; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[12:13], v2
	; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0			; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
	; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v14, 0			; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v15, 0			; GCN-IR-NEXT: v_mov_b32_e32 v15, 0
	; GCN-IR-NEXT: BB1_3: ; %udiv-do-while			; GCN-IR-NEXT: BB1_3: ; %udiv-do-while
	; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1			; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
	; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1			; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
	; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v9			; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v11
	; GCN-IR-NEXT: v_mov_b32_e32 v11, 0			; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
	; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1			; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
	; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, -1, v2			; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, -1, v2
	; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc
	; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v10			; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v8
	; GCN-IR-NEXT: v_or_b32_e32 v9, v15, v9			; GCN-IR-NEXT: v_or_b32_e32 v11, v15, v11
	; GCN-IR-NEXT: v_or_b32_e32 v8, v14, v8			; GCN-IR-NEXT: v_or_b32_e32 v10, v14, v10
	; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]			; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
	; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v12, v16			; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v12, v16
	; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v13, v17, s[4:5]			; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v13, v17, s[4:5]
	; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]			; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
	; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v10			; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8
	; GCN-IR-NEXT: v_and_b32_e32 v10, 1, v14			; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14
	; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v1			; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v1
	; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v0			; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v0
	; GCN-IR-NEXT: v_sub_i32_e32 v16, vcc, v16, v14			; GCN-IR-NEXT: v_sub_i32_e32 v16, vcc, v16, v14
	; GCN-IR-NEXT: v_subb_u32_e32 v17, vcc, v17, v15, vcc			; GCN-IR-NEXT: v_subb_u32_e32 v17, vcc, v17, v15, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v15, v11			; GCN-IR-NEXT: v_mov_b32_e32 v15, v9
	; GCN-IR-NEXT: v_mov_b32_e32 v14, v10			; GCN-IR-NEXT: v_mov_b32_e32 v14, v8
	; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: s_cbranch_execnz BB1_3			; GCN-IR-NEXT: s_cbranch_execnz BB1_3
	; GCN-IR-NEXT: ; %bb.4: ; %Flow			; GCN-IR-NEXT: ; %bb.4: ; %Flow
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: BB1_5: ; %Flow1			; GCN-IR-NEXT: BB1_5: ; %Flow1
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
	; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[8:9], 1			; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[10:11], 1
	; GCN-IR-NEXT: v_or_b32_e32 v2, v11, v1			; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v1
	; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v0			; GCN-IR-NEXT: v_or_b32_e32 v3, v8, v0
	; GCN-IR-NEXT: BB1_6: ; %Flow2			; GCN-IR-NEXT: BB1_6: ; %Flow2
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
	; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v6			; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v6
	; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4			; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4
	; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v1			; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v1
	; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v0			; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v0
	; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0			; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
	; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc			; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
	▲ Show 20 Lines • Show All 994 Lines • ▼ Show 20 Lines
	; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]			; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB11_6			; GCN-IR-NEXT: s_cbranch_execz BB11_6
	; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1			; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
	; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v6			; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v6
	; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
	; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v6			; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v6
	; GCN-IR-NEXT: s_mov_b64 s[8:9], 0			; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
	; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[6:7]			; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[6:7]
	; GCN-IR-NEXT: v_lshl_b64 v[6:7], 24, v8			; GCN-IR-NEXT: v_lshl_b64 v[8:9], 24, v8
	; GCN-IR-NEXT: v_mov_b32_e32 v8, 0			; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v9, 0			; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
	; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc			; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
	; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]			; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB11_5			; GCN-IR-NEXT: s_cbranch_execz BB11_5
	; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader			; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
	; GCN-IR-NEXT: v_lshr_b64 v[14:15], 24, v4			; GCN-IR-NEXT: v_lshr_b64 v[14:15], 24, v4
	; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, -1, v0			; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, -1, v0
	; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, -1, v1, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, -1, v1, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v12, 0			; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v13, 0			; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
	; GCN-IR-NEXT: BB11_3: ; %udiv-do-while			; GCN-IR-NEXT: BB11_3: ; %udiv-do-while
	; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1			; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
	; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1			; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
	; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v7			; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v9
	; GCN-IR-NEXT: v_mov_b32_e32 v9, 0			; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
	; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1			; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
	; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v4			; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v4
	; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc
	; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8			; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v6
	; GCN-IR-NEXT: v_or_b32_e32 v7, v13, v7			; GCN-IR-NEXT: v_or_b32_e32 v9, v13, v9
	; GCN-IR-NEXT: v_or_b32_e32 v6, v12, v6			; GCN-IR-NEXT: v_or_b32_e32 v8, v12, v8
	; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]			; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
	; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v10, v14			; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v10, v14
	; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v11, v15, s[4:5]			; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v11, v15, s[4:5]
	; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]			; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
	; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8			; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
	; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12			; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
	; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1			; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
	; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0			; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
	; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, v14, v12			; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, v14, v12
	; GCN-IR-NEXT: v_subb_u32_e32 v15, vcc, v15, v13, vcc			; GCN-IR-NEXT: v_subb_u32_e32 v15, vcc, v15, v13, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v13, v9			; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
	; GCN-IR-NEXT: v_mov_b32_e32 v12, v8			; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
	; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: s_cbranch_execnz BB11_3			; GCN-IR-NEXT: s_cbranch_execnz BB11_3
	; GCN-IR-NEXT: ; %bb.4: ; %Flow			; GCN-IR-NEXT: ; %bb.4: ; %Flow
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: BB11_5: ; %Flow1			; GCN-IR-NEXT: BB11_5: ; %Flow1
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
	; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[6:7], 1			; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[8:9], 1
	; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v1			; GCN-IR-NEXT: v_or_b32_e32 v5, v7, v1
	; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v0			; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v0
	; GCN-IR-NEXT: BB11_6: ; %Flow2			; GCN-IR-NEXT: BB11_6: ; %Flow2
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
	; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v3			; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v3
	; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v2			; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v2
	; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2			; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
	; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc			; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
	; GCN-IR-NEXT: s_setpc_b64 s[30:31]			; GCN-IR-NEXT: s_setpc_b64 s[30:31]
	%result = sdiv i64 24, %x			%result = sdiv i64 24, %x
	▲ Show 20 Lines • Show All 554 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

	Show First 20 Lines • Show All 393 Lines • ▼ Show 20 Lines
	; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]			; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB1_6			; GCN-IR-NEXT: s_cbranch_execz BB1_6
	; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1			; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
	; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v8			; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v8
	; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
	; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 63, v8			; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 63, v8
	; GCN-IR-NEXT: s_mov_b64 s[8:9], 0			; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
	; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[8:9]			; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[8:9]
	; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[0:1], v10			; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[0:1], v10
	; GCN-IR-NEXT: v_mov_b32_e32 v10, 0			; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v11, 0			; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
	; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc			; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
	; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]			; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB1_5			; GCN-IR-NEXT: s_cbranch_execz BB1_5
	; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader			; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
	; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[0:1], v6			; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[0:1], v6
	; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2			; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2
	; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v14, 0			; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v15, 0			; GCN-IR-NEXT: v_mov_b32_e32 v15, 0
	; GCN-IR-NEXT: BB1_3: ; %udiv-do-while			; GCN-IR-NEXT: BB1_3: ; %udiv-do-while
	; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1			; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
	; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1			; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1
	; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v9			; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v11
	; GCN-IR-NEXT: v_mov_b32_e32 v11, 0			; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
	; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1			; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
	; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v6			; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v6
	; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v7, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v7, vcc
	; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v10			; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v8
	; GCN-IR-NEXT: v_or_b32_e32 v9, v15, v9			; GCN-IR-NEXT: v_or_b32_e32 v11, v15, v11
	; GCN-IR-NEXT: v_or_b32_e32 v8, v14, v8			; GCN-IR-NEXT: v_or_b32_e32 v10, v14, v10
	; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]			; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
	; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v12, v16			; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v12, v16
	; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v13, v17, s[4:5]			; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v13, v17, s[4:5]
	; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]			; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
	; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v10			; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8
	; GCN-IR-NEXT: v_and_b32_e32 v10, 1, v14			; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14
	; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v3			; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v3
	; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v2			; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v2
	; GCN-IR-NEXT: v_sub_i32_e32 v16, vcc, v16, v14			; GCN-IR-NEXT: v_sub_i32_e32 v16, vcc, v16, v14
	; GCN-IR-NEXT: v_subb_u32_e32 v17, vcc, v17, v15, vcc			; GCN-IR-NEXT: v_subb_u32_e32 v17, vcc, v17, v15, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v15, v11			; GCN-IR-NEXT: v_mov_b32_e32 v15, v9
	; GCN-IR-NEXT: v_mov_b32_e32 v14, v10			; GCN-IR-NEXT: v_mov_b32_e32 v14, v8
	; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: s_cbranch_execnz BB1_3			; GCN-IR-NEXT: s_cbranch_execnz BB1_3
	; GCN-IR-NEXT: ; %bb.4: ; %Flow			; GCN-IR-NEXT: ; %bb.4: ; %Flow
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: BB1_5: ; %Flow1			; GCN-IR-NEXT: BB1_5: ; %Flow1
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
	; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[8:9], 1			; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[10:11], 1
	; GCN-IR-NEXT: v_or_b32_e32 v7, v11, v7			; GCN-IR-NEXT: v_or_b32_e32 v7, v9, v7
	; GCN-IR-NEXT: v_or_b32_e32 v6, v10, v6			; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v6
	; GCN-IR-NEXT: BB1_6: ; %Flow2			; GCN-IR-NEXT: BB1_6: ; %Flow2
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
	; GCN-IR-NEXT: v_mul_lo_u32 v7, v2, v7			; GCN-IR-NEXT: v_mul_lo_u32 v7, v2, v7
	; GCN-IR-NEXT: v_mul_hi_u32 v8, v2, v6			; GCN-IR-NEXT: v_mul_hi_u32 v8, v2, v6
	; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6			; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6
	; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6			; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6
	; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, v8, v7			; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, v8, v7
	; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v6, v3			; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v6, v3
	▲ Show 20 Lines • Show All 1,194 Lines • ▼ Show 20 Lines
	; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]			; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB11_6			; GCN-IR-NEXT: s_cbranch_execz BB11_6
	; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1			; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
	; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v4			; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 1, v4
	; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc
	; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 63, v4			; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 63, v4
	; GCN-IR-NEXT: s_mov_b64 s[8:9], 0			; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
	; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[4:5]			; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[4:5]
	; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v6			; GCN-IR-NEXT: v_lshl_b64 v[6:7], 24, v6
	; GCN-IR-NEXT: v_mov_b32_e32 v6, 0			; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v7, 0			; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
	; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc			; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
	; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]			; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
	; GCN-IR-NEXT: s_cbranch_execz BB11_5			; GCN-IR-NEXT: s_cbranch_execz BB11_5
	; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader			; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
	; GCN-IR-NEXT: v_lshr_b64 v[12:13], 24, v2			; GCN-IR-NEXT: v_lshr_b64 v[12:13], 24, v2
	; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, -1, v0			; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, -1, v0
	; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v1, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v1, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v10, 0			; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
	; GCN-IR-NEXT: v_mov_b32_e32 v11, 0			; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
	; GCN-IR-NEXT: BB11_3: ; %udiv-do-while			; GCN-IR-NEXT: BB11_3: ; %udiv-do-while
	; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1			; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
	; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1			; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
	; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5			; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v7
	; GCN-IR-NEXT: v_mov_b32_e32 v7, 0			; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
	; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1			; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
	; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, -1, v2			; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, -1, v2
	; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc			; GCN-IR-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc
	; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6			; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v4
	; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5			; GCN-IR-NEXT: v_or_b32_e32 v7, v11, v7
	; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4			; GCN-IR-NEXT: v_or_b32_e32 v6, v10, v6
	; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]			; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
	; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v8, v12			; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], v8, v12
	; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v9, v13, s[4:5]			; GCN-IR-NEXT: v_subb_u32_e64 v4, s[4:5], v9, v13, s[4:5]
	; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]			; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
	; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6			; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
	; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10			; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
	; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1			; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
	; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0			; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
	; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v10			; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v10
	; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v11, vcc			; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v11, vcc
	; GCN-IR-NEXT: v_mov_b32_e32 v11, v7			; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
	; GCN-IR-NEXT: v_mov_b32_e32 v10, v6			; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
	; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: s_cbranch_execnz BB11_3			; GCN-IR-NEXT: s_cbranch_execnz BB11_3
	; GCN-IR-NEXT: ; %bb.4: ; %Flow			; GCN-IR-NEXT: ; %bb.4: ; %Flow
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
	; GCN-IR-NEXT: BB11_5: ; %Flow1			; GCN-IR-NEXT: BB11_5: ; %Flow1
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
	; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 1			; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[6:7], 1
	; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3			; GCN-IR-NEXT: v_or_b32_e32 v3, v5, v3
	; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2			; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v2
	; GCN-IR-NEXT: BB11_6: ; %Flow2			; GCN-IR-NEXT: BB11_6: ; %Flow2
	; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]			; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
	; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v3			; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v3
	; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2			; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2
	; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2			; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2
	; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2			; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2
	; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v3			; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v3
	; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1			; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
	▲ Show 20 Lines • Show All 583 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show First 20 Lines • Show All 359 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]		; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_6		; GCN-IR-NEXT: s_cbranch_execz BB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1		; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v6		; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc		; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v6		; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v6
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0		; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[6:7]		; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[0:1], v8		; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[0:1], v8
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0		; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0		; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc		; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]		; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_5		; GCN-IR-NEXT: s_cbranch_execz BB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader		; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v4		; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v4
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, -1, v2		; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc		; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0		; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0		; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while		; GCN-IR-NEXT: BB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1		; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1		; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v7		; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0		; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1		; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v4		; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc		; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc
; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8		; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6
; GCN-IR-NEXT: v_or_b32_e32 v7, v11, v7		; GCN-IR-NEXT: v_or_b32_e32 v9, v11, v9
; GCN-IR-NEXT: v_or_b32_e32 v6, v10, v6		; GCN-IR-NEXT: v_or_b32_e32 v8, v10, v8
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]		; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v12		; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v12
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v13, s[4:5]		; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v13, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]		; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v8		; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v10		; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v3		; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v3
; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v2		; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v2
; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v10		; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v10
; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v11, vcc		; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v11, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, v9		; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: v_mov_b32_e32 v10, v8		; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]		; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB1_3		; GCN-IR-NEXT: s_cbranch_execnz BB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow		; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]		; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: BB1_5: ; %Flow1		; GCN-IR-NEXT: BB1_5: ; %Flow1
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]		; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[6:7], 1		; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[8:9], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v9, v1		; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
; GCN-IR-NEXT: v_or_b32_e32 v5, v8, v0		; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0
; GCN-IR-NEXT: BB1_6: ; %Flow2		; GCN-IR-NEXT: BB1_6: ; %Flow2
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]		; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v0, v5		; GCN-IR-NEXT: v_mov_b32_e32 v0, v5
; GCN-IR-NEXT: v_mov_b32_e32 v1, v4		; GCN-IR-NEXT: v_mov_b32_e32 v1, v4
; GCN-IR-NEXT: s_setpc_b64 s[30:31]		; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 %x, %y		%result = udiv i64 %x, %y
ret i64 %result		ret i64 %result
}		}
▲ Show 20 Lines • Show All 1,509 Lines • ▼ Show 20 Lines	; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = udiv i64 32768, %x.shr		%result = udiv i64 32768, %x.shr
ret i64 %result		ret i64 %result
}		}

define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {		define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:		; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1		; GCN-NEXT: v_lshrrev_b32_e32 v0, 23, v1
; GCN-NEXT: s_mov_b32 s4, 0x47000000
; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v1, 0x38000000, v0
; GCN-NEXT: v_trunc_f32_e32 v1, v1
; GCN-NEXT: v_mad_f32 v0, -v1, s4, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, \|v0\|, s4
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0		; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]		; GCN-NEXT: s_setpc_b64 s[30:31]
;		;
; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:		; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
; GCN-IR: ; %bb.0:		; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1		; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000		; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
Show All 14 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 368 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]		; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_6		; GCN-IR-NEXT: s_cbranch_execz BB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1		; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v6		; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc		; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v6		; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v6
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0		; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[6:7]		; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[0:1], v8		; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[0:1], v8
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0		; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0		; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc		; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]		; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB1_5		; GCN-IR-NEXT: s_cbranch_execz BB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader		; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v4		; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v4
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, -1, v2		; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, -1, v3, vcc		; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0		; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0		; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: BB1_3: ; %udiv-do-while		; GCN-IR-NEXT: BB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1		; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1		; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v7		; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0		; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1		; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v4		; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc		; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v5, vcc
; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8		; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v6
; GCN-IR-NEXT: v_or_b32_e32 v7, v13, v7		; GCN-IR-NEXT: v_or_b32_e32 v9, v13, v9
; GCN-IR-NEXT: v_or_b32_e32 v6, v12, v6		; GCN-IR-NEXT: v_or_b32_e32 v8, v12, v8
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]		; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v10, v14		; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v10, v14
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v11, v15, s[4:5]		; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v11, v15, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]		; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8		; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12		; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3		; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2		; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2
; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, v14, v12		; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, v14, v12
; GCN-IR-NEXT: v_subb_u32_e32 v15, vcc, v15, v13, vcc		; GCN-IR-NEXT: v_subb_u32_e32 v15, vcc, v15, v13, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v13, v9		; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: v_mov_b32_e32 v12, v8		; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]		; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB1_3		; GCN-IR-NEXT: s_cbranch_execnz BB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow		; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]		; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: BB1_5: ; %Flow1		; GCN-IR-NEXT: BB1_5: ; %Flow1
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]		; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 1		; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[8:9], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5		; GCN-IR-NEXT: v_or_b32_e32 v5, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4		; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4
; GCN-IR-NEXT: BB1_6: ; %Flow2		; GCN-IR-NEXT: BB1_6: ; %Flow2
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]		; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v5		; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v5
; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4		; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4		; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4		; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v6, v5		; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v6, v5
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3		; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3
▲ Show 20 Lines • Show All 1,186 Lines • ▼ Show 20 Lines	; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 32768, %x.shr		%result = urem i64 32768, %x.shr
ret i64 %result		ret i64 %result
}		}

define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {		define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_urem24_pow2_k_den_i64:		; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
; GCN: ; %bb.0:		; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1		; GCN-NEXT: v_bfe_u32 v0, v1, 8, 15
; GCN-NEXT: s_mov_b32 s4, 0x47000000
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
; GCN-NEXT: v_mul_f32_e32 v2, 0x38000000, v1
; GCN-NEXT: v_trunc_f32_e32 v2, v2
; GCN-NEXT: v_mad_f32 v1, -v2, s4, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, \|v1\|, s4
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
; GCN-NEXT: v_lshlrev_b32_e32 v1, 15, v1
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0		; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]		; GCN-NEXT: s_setpc_b64 s[30:31]
;		;
; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:		; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
; GCN-IR: ; %bb.0:		; GCN-IR: ; %bb.0:
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1		; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000		; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
Show All 16 Lines