AMDGPU: Don't create weird sized integers

[arsenm]

Summary

There's no reason to introduce a new, unnaturally sized value
here. This has a chance to produce worse code with
legalization. Avoids regression in a future patch.

[rampitec]

LGTM

[arsenm]

e5823bf806ca9fa6f87583065b3898a2edabce57

llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder,
 
   Value *Res = Div;
   if (!IsDiv) {
     // Rem needs compensation, it's easier to recompute it
     Value *Rem = Builder.CreateMul(Div, Den);
     Res = Builder.CreateSub(Num, Rem);
   }
 
-  // Truncate to number of bits this divide really is.
+  // Extend in register from the number of bits this divide really is.
   if (IsSigned) {
-    Res = Builder.CreateTrunc(Res, Builder.getIntNTy(DivBits));
-    Res = Builder.CreateSExt(Res, Ty);
+    Res = Builder.CreateShl(Res, 32 - DivBits);
+    Res = Builder.CreateAShr(Res, 32 - DivBits);
   } else {
     ConstantInt *TruncMask = Builder.getInt32((UINT64_C(1) << DivBits) - 1);
     Res = Builder.CreateAnd(Res, TruncMask);
   }
 
   return Res;
 }
 

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

 ; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
 ; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
 ; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
-; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i16
-; CHECK-NEXT:    [[TMP20:%.*]] = sext i16 [[TMP19]] to i32
+; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 16
+; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 16
 ; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
 ; CHECK-NEXT:    store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = sdiv i16 %x, %y
   store i16 %r, i16 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
 ; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
-; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
-; CHECK-NEXT:    [[TMP22:%.*]] = sext i16 [[TMP21]] to i32
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
+; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
 ; CHECK-NEXT:    store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = srem i16 %x, %y
   store i16 %r, i16 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
 ; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
 ; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
-; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i8
-; CHECK-NEXT:    [[TMP20:%.*]] = sext i8 [[TMP19]] to i32
+; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 24
+; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 24
 ; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
 ; CHECK-NEXT:    store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = sdiv i8 %x, %y
   store i8 %r, i8 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
 ; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
-; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i8
-; CHECK-NEXT:    [[TMP22:%.*]] = sext i8 [[TMP21]] to i32
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 24
+; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 24
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8
 ; CHECK-NEXT:    store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = srem i8 %x, %y
   store i8 %r, i8 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
 ; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
 ; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
 ; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
-; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
-; CHECK-NEXT:    [[TMP22:%.*]] = sext i16 [[TMP21]] to i32
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
+; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
 ; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <4 x i16> undef, i16 [[TMP23]], i64 0
 ; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <4 x i16> [[X]], i64 1
 ; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <4 x i16> [[Y]], i64 1
 ; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
 ; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
 ; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
 ; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
 ; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
 ; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
 ; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
 ; CHECK-NEXT:    [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]]
 ; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
 ; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
 ; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
 ; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
 ; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
 ; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
 ; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
 ; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
 ; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
-; CHECK-NEXT:    [[TMP45:%.*]] = trunc i32 [[TMP44]] to i16
-; CHECK-NEXT:    [[TMP46:%.*]] = sext i16 [[TMP45]] to i32
+; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
+; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
 ; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
 ; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <4 x i16> [[TMP24]], i16 [[TMP47]], i64 1
 ; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <4 x i16> [[X]], i64 2
 ; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <4 x i16> [[Y]], i64 2
 ; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
 ; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
 ; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
 ; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
 ; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
 ; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
 ; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
 ; CHECK-NEXT:    [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]]
 ; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
 ; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
 ; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
 ; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
 ; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
 ; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
 ; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
 ; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
 ; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
 ; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
-; CHECK-NEXT:    [[TMP69:%.*]] = trunc i32 [[TMP68]] to i16
-; CHECK-NEXT:    [[TMP70:%.*]] = sext i16 [[TMP69]] to i32
+; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
+; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
 ; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
 ; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <4 x i16> [[TMP48]], i16 [[TMP71]], i64 2
 ; CHECK-NEXT:    [[TMP73:%.*]] = extractelement <4 x i16> [[X]], i64 3
 ; CHECK-NEXT:    [[TMP74:%.*]] = extractelement <4 x i16> [[Y]], i64 3
 ; CHECK-NEXT:    [[TMP75:%.*]] = sext i16 [[TMP73]] to i32
 ; CHECK-NEXT:    [[TMP76:%.*]] = sext i16 [[TMP74]] to i32
 ; CHECK-NEXT:    [[TMP77:%.*]] = xor i32 [[TMP75]], [[TMP76]]
 ; CHECK-NEXT:    [[TMP78:%.*]] = ashr i32 [[TMP77]], 30
 ; CHECK-NEXT:    [[TMP79:%.*]] = or i32 [[TMP78]], 1
 ; CHECK-NEXT:    [[TMP80:%.*]] = sitofp i32 [[TMP75]] to float
 ; CHECK-NEXT:    [[TMP81:%.*]] = sitofp i32 [[TMP76]] to float
 ; CHECK-NEXT:    [[TMP82:%.*]] = fdiv fast float 1.000000e+00, [[TMP81]]
 ; CHECK-NEXT:    [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]]
 ; CHECK-NEXT:    [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]])
 ; CHECK-NEXT:    [[TMP85:%.*]] = fneg fast float [[TMP84]]
 ; CHECK-NEXT:    [[TMP86:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP85]], float [[TMP81]], float [[TMP80]])
 ; CHECK-NEXT:    [[TMP87:%.*]] = fptosi float [[TMP84]] to i32
 ; CHECK-NEXT:    [[TMP88:%.*]] = call fast float @llvm.fabs.f32(float [[TMP86]])
 ; CHECK-NEXT:    [[TMP89:%.*]] = call fast float @llvm.fabs.f32(float [[TMP81]])
 ; CHECK-NEXT:    [[TMP90:%.*]] = fcmp fast oge float [[TMP88]], [[TMP89]]
 ; CHECK-NEXT:    [[TMP91:%.*]] = select i1 [[TMP90]], i32 [[TMP79]], i32 0
 ; CHECK-NEXT:    [[TMP92:%.*]] = add i32 [[TMP87]], [[TMP91]]
-; CHECK-NEXT:    [[TMP93:%.*]] = trunc i32 [[TMP92]] to i16
-; CHECK-NEXT:    [[TMP94:%.*]] = sext i16 [[TMP93]] to i32
+; CHECK-NEXT:    [[TMP93:%.*]] = shl i32 [[TMP92]], 16
+; CHECK-NEXT:    [[TMP94:%.*]] = ashr i32 [[TMP93]], 16
 ; CHECK-NEXT:    [[TMP95:%.*]] = trunc i32 [[TMP94]] to i16
 ; CHECK-NEXT:    [[TMP96:%.*]] = insertelement <4 x i16> [[TMP72]], i16 [[TMP95]], i64 3
 ; CHECK-NEXT:    store <4 x i16> [[TMP96]], <4 x i16> addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = sdiv <4 x i16> %x, %y
   store <4 x i16> %r, <4 x i16> addrspace(1)* %out
   ret void

 ; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
 ; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
 ; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
 ; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
-; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
-; CHECK-NEXT:    [[TMP24:%.*]] = sext i16 [[TMP23]] to i32
+; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
+; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
 ; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
 ; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <4 x i16> undef, i16 [[TMP25]], i64 0
 ; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <4 x i16> [[X]], i64 1
 ; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <4 x i16> [[Y]], i64 1
 ; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
 ; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
 ; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
 ; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
 ; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
 ; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
 ; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
 ; CHECK-NEXT:    [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]]
 ; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
 ; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
 ; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
 ; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
 ; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
 ; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
 ; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
 ; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
 ; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
 ; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
 ; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
-; CHECK-NEXT:    [[TMP49:%.*]] = trunc i32 [[TMP48]] to i16
-; CHECK-NEXT:    [[TMP50:%.*]] = sext i16 [[TMP49]] to i32
+; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
+; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
 ; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
 ; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <4 x i16> [[TMP26]], i16 [[TMP51]], i64 1
 ; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <4 x i16> [[X]], i64 2
 ; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <4 x i16> [[Y]], i64 2
 ; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
 ; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
 ; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
 ; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
 ; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
 ; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
 ; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
 ; CHECK-NEXT:    [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]]
 ; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
 ; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
 ; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
 ; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
 ; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
 ; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
 ; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
 ; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
 ; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
 ; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
 ; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
-; CHECK-NEXT:    [[TMP75:%.*]] = trunc i32 [[TMP74]] to i16
-; CHECK-NEXT:    [[TMP76:%.*]] = sext i16 [[TMP75]] to i32
+; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
+; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
 ; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
 ; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <4 x i16> [[TMP52]], i16 [[TMP77]], i64 2
 ; CHECK-NEXT:    [[TMP79:%.*]] = extractelement <4 x i16> [[X]], i64 3
 ; CHECK-NEXT:    [[TMP80:%.*]] = extractelement <4 x i16> [[Y]], i64 3
 ; CHECK-NEXT:    [[TMP81:%.*]] = sext i16 [[TMP79]] to i32
 ; CHECK-NEXT:    [[TMP82:%.*]] = sext i16 [[TMP80]] to i32
 ; CHECK-NEXT:    [[TMP83:%.*]] = xor i32 [[TMP81]], [[TMP82]]
 ; CHECK-NEXT:    [[TMP84:%.*]] = ashr i32 [[TMP83]], 30
 ; CHECK-NEXT:    [[TMP85:%.*]] = or i32 [[TMP84]], 1
 ; CHECK-NEXT:    [[TMP86:%.*]] = sitofp i32 [[TMP81]] to float
 ; CHECK-NEXT:    [[TMP87:%.*]] = sitofp i32 [[TMP82]] to float
 ; CHECK-NEXT:    [[TMP88:%.*]] = fdiv fast float 1.000000e+00, [[TMP87]]
 ; CHECK-NEXT:    [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]]
 ; CHECK-NEXT:    [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]])
 ; CHECK-NEXT:    [[TMP91:%.*]] = fneg fast float [[TMP90]]
 ; CHECK-NEXT:    [[TMP92:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP91]], float [[TMP87]], float [[TMP86]])
 ; CHECK-NEXT:    [[TMP93:%.*]] = fptosi float [[TMP90]] to i32
 ; CHECK-NEXT:    [[TMP94:%.*]] = call fast float @llvm.fabs.f32(float [[TMP92]])
 ; CHECK-NEXT:    [[TMP95:%.*]] = call fast float @llvm.fabs.f32(float [[TMP87]])
 ; CHECK-NEXT:    [[TMP96:%.*]] = fcmp fast oge float [[TMP94]], [[TMP95]]
 ; CHECK-NEXT:    [[TMP97:%.*]] = select i1 [[TMP96]], i32 [[TMP85]], i32 0
 ; CHECK-NEXT:    [[TMP98:%.*]] = add i32 [[TMP93]], [[TMP97]]
 ; CHECK-NEXT:    [[TMP99:%.*]] = mul i32 [[TMP98]], [[TMP82]]
 ; CHECK-NEXT:    [[TMP100:%.*]] = sub i32 [[TMP81]], [[TMP99]]
-; CHECK-NEXT:    [[TMP101:%.*]] = trunc i32 [[TMP100]] to i16
-; CHECK-NEXT:    [[TMP102:%.*]] = sext i16 [[TMP101]] to i32
+; CHECK-NEXT:    [[TMP101:%.*]] = shl i32 [[TMP100]], 16
+; CHECK-NEXT:    [[TMP102:%.*]] = ashr i32 [[TMP101]], 16
 ; CHECK-NEXT:    [[TMP103:%.*]] = trunc i32 [[TMP102]] to i16
 ; CHECK-NEXT:    [[TMP104:%.*]] = insertelement <4 x i16> [[TMP78]], i16 [[TMP103]], i64 3
 ; CHECK-NEXT:    store <4 x i16> [[TMP104]], <4 x i16> addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = srem <4 x i16> %x, %y
   store <4 x i16> %r, <4 x i16> addrspace(1)* %out
   ret void

 ; CHECK-NEXT:    [[TMP11:%.*]] = fneg fast float [[TMP10]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP11]], float [[TMP7]], float [[TMP6]])
 ; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
 ; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
-; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i3
-; CHECK-NEXT:    [[TMP20:%.*]] = sext i3 [[TMP19]] to i32
+; CHECK-NEXT:    [[TMP19:%.*]] = shl i32 [[TMP18]], 29
+; CHECK-NEXT:    [[TMP20:%.*]] = ashr i32 [[TMP19]], 29
 ; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i3
 ; CHECK-NEXT:    store i3 [[TMP21]], i3 addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = sdiv i3 %x, %y
   store i3 %r, i3 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    [[TMP13:%.*]] = fptosi float [[TMP10]] to i32
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.fabs.f32(float [[TMP12]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = call fast float @llvm.fabs.f32(float [[TMP7]])
 ; CHECK-NEXT:    [[TMP16:%.*]] = fcmp fast oge float [[TMP14]], [[TMP15]]
 ; CHECK-NEXT:    [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP5]], i32 0
 ; CHECK-NEXT:    [[TMP18:%.*]] = add i32 [[TMP13]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = mul i32 [[TMP18]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP20:%.*]] = sub i32 [[TMP1]], [[TMP19]]
-; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i3
-; CHECK-NEXT:    [[TMP22:%.*]] = sext i3 [[TMP21]] to i32
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 29
+; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 29
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i3
 ; CHECK-NEXT:    store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = srem i3 %x, %y
   store i3 %r, i3 addrspace(1)* %out
   ret void
 }

 ; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
 ; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
 ; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
 ; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
-; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16
-; CHECK-NEXT:    [[TMP22:%.*]] = sext i16 [[TMP21]] to i32
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 16
+; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 16
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
 ; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i16> undef, i16 [[TMP23]], i64 0
 ; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i16> [[X]], i64 1
 ; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i16> [[Y]], i64 1
 ; CHECK-NEXT:    [[TMP27:%.*]] = sext i16 [[TMP25]] to i32
 ; CHECK-NEXT:    [[TMP28:%.*]] = sext i16 [[TMP26]] to i32
 ; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
 ; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
 ; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
 ; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
 ; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
 ; CHECK-NEXT:    [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]]
 ; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
 ; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
 ; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
 ; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
 ; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
 ; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
 ; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
 ; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
 ; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
-; CHECK-NEXT:    [[TMP45:%.*]] = trunc i32 [[TMP44]] to i16
-; CHECK-NEXT:    [[TMP46:%.*]] = sext i16 [[TMP45]] to i32
+; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 16
+; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 16
 ; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i16
 ; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i16> [[TMP24]], i16 [[TMP47]], i64 1
 ; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i16> [[X]], i64 2
 ; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i16> [[Y]], i64 2
 ; CHECK-NEXT:    [[TMP51:%.*]] = sext i16 [[TMP49]] to i32
 ; CHECK-NEXT:    [[TMP52:%.*]] = sext i16 [[TMP50]] to i32
 ; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
 ; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
 ; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
 ; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
 ; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
 ; CHECK-NEXT:    [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]]
 ; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
 ; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
 ; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
 ; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
 ; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
 ; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
 ; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
 ; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
 ; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
 ; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
-; CHECK-NEXT:    [[TMP69:%.*]] = trunc i32 [[TMP68]] to i16
-; CHECK-NEXT:    [[TMP70:%.*]] = sext i16 [[TMP69]] to i32
+; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 16
+; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 16
 ; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i16
 ; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i16> [[TMP48]], i16 [[TMP71]], i64 2
 ; CHECK-NEXT:    store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = sdiv <3 x i16> %x, %y
   store <3 x i16> %r, <3 x i16> addrspace(1)* %out
   ret void

 ; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
 ; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
 ; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
 ; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
-; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i16
-; CHECK-NEXT:    [[TMP24:%.*]] = sext i16 [[TMP23]] to i32
+; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 16
+; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 16
 ; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i16
 ; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i16> undef, i16 [[TMP25]], i64 0
 ; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i16> [[X]], i64 1
 ; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i16> [[Y]], i64 1
 ; CHECK-NEXT:    [[TMP29:%.*]] = sext i16 [[TMP27]] to i32
 ; CHECK-NEXT:    [[TMP30:%.*]] = sext i16 [[TMP28]] to i32
 ; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
 ; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
 ; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
 ; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
 ; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
 ; CHECK-NEXT:    [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]]
 ; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
 ; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
 ; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
 ; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
 ; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
 ; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
 ; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
 ; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
 ; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
 ; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
 ; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
-; CHECK-NEXT:    [[TMP49:%.*]] = trunc i32 [[TMP48]] to i16
-; CHECK-NEXT:    [[TMP50:%.*]] = sext i16 [[TMP49]] to i32
+; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 16
+; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 16
 ; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i16
 ; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i16> [[TMP26]], i16 [[TMP51]], i64 1
 ; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i16> [[X]], i64 2
 ; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i16> [[Y]], i64 2
 ; CHECK-NEXT:    [[TMP55:%.*]] = sext i16 [[TMP53]] to i32
 ; CHECK-NEXT:    [[TMP56:%.*]] = sext i16 [[TMP54]] to i32
 ; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
 ; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
 ; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
 ; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
 ; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
 ; CHECK-NEXT:    [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]]
 ; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
 ; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
 ; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
 ; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
 ; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
 ; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
 ; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
 ; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
 ; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
 ; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
 ; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
-; CHECK-NEXT:    [[TMP75:%.*]] = trunc i32 [[TMP74]] to i16
-; CHECK-NEXT:    [[TMP76:%.*]] = sext i16 [[TMP75]] to i32
+; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 16
+; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 16
 ; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i16
 ; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i16> [[TMP52]], i16 [[TMP77]], i64 2
 ; CHECK-NEXT:    store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = srem <3 x i16> %x, %y
   store <3 x i16> %r, <3 x i16> addrspace(1)* %out
   ret void

 ; CHECK-NEXT:    [[TMP13:%.*]] = fneg fast float [[TMP12]]
 ; CHECK-NEXT:    [[TMP14:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP13]], float [[TMP9]], float [[TMP8]])
 ; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
 ; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
 ; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
 ; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
-; CHECK-NEXT:    [[TMP21:%.*]] = trunc i32 [[TMP20]] to i15
-; CHECK-NEXT:    [[TMP22:%.*]] = sext i15 [[TMP21]] to i32
+; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 17
+; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 17
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i15
 ; CHECK-NEXT:    [[TMP24:%.*]] = insertelement <3 x i15> undef, i15 [[TMP23]], i64 0
 ; CHECK-NEXT:    [[TMP25:%.*]] = extractelement <3 x i15> [[X]], i64 1
 ; CHECK-NEXT:    [[TMP26:%.*]] = extractelement <3 x i15> [[Y]], i64 1
 ; CHECK-NEXT:    [[TMP27:%.*]] = sext i15 [[TMP25]] to i32
 ; CHECK-NEXT:    [[TMP28:%.*]] = sext i15 [[TMP26]] to i32
 ; CHECK-NEXT:    [[TMP29:%.*]] = xor i32 [[TMP27]], [[TMP28]]
 ; CHECK-NEXT:    [[TMP30:%.*]] = ashr i32 [[TMP29]], 30
 ; CHECK-NEXT:    [[TMP31:%.*]] = or i32 [[TMP30]], 1
 ; CHECK-NEXT:    [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float
 ; CHECK-NEXT:    [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float
 ; CHECK-NEXT:    [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]]
 ; CHECK-NEXT:    [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]]
 ; CHECK-NEXT:    [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]])
 ; CHECK-NEXT:    [[TMP37:%.*]] = fneg fast float [[TMP36]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP37]], float [[TMP33]], float [[TMP32]])
 ; CHECK-NEXT:    [[TMP39:%.*]] = fptosi float [[TMP36]] to i32
 ; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.fabs.f32(float [[TMP38]])
 ; CHECK-NEXT:    [[TMP41:%.*]] = call fast float @llvm.fabs.f32(float [[TMP33]])
 ; CHECK-NEXT:    [[TMP42:%.*]] = fcmp fast oge float [[TMP40]], [[TMP41]]
 ; CHECK-NEXT:    [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP31]], i32 0
 ; CHECK-NEXT:    [[TMP44:%.*]] = add i32 [[TMP39]], [[TMP43]]
-; CHECK-NEXT:    [[TMP45:%.*]] = trunc i32 [[TMP44]] to i15
-; CHECK-NEXT:    [[TMP46:%.*]] = sext i15 [[TMP45]] to i32
+; CHECK-NEXT:    [[TMP45:%.*]] = shl i32 [[TMP44]], 17
+; CHECK-NEXT:    [[TMP46:%.*]] = ashr i32 [[TMP45]], 17
 ; CHECK-NEXT:    [[TMP47:%.*]] = trunc i32 [[TMP46]] to i15
 ; CHECK-NEXT:    [[TMP48:%.*]] = insertelement <3 x i15> [[TMP24]], i15 [[TMP47]], i64 1
 ; CHECK-NEXT:    [[TMP49:%.*]] = extractelement <3 x i15> [[X]], i64 2
 ; CHECK-NEXT:    [[TMP50:%.*]] = extractelement <3 x i15> [[Y]], i64 2
 ; CHECK-NEXT:    [[TMP51:%.*]] = sext i15 [[TMP49]] to i32
 ; CHECK-NEXT:    [[TMP52:%.*]] = sext i15 [[TMP50]] to i32
 ; CHECK-NEXT:    [[TMP53:%.*]] = xor i32 [[TMP51]], [[TMP52]]
 ; CHECK-NEXT:    [[TMP54:%.*]] = ashr i32 [[TMP53]], 30
 ; CHECK-NEXT:    [[TMP55:%.*]] = or i32 [[TMP54]], 1
 ; CHECK-NEXT:    [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float
 ; CHECK-NEXT:    [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float
 ; CHECK-NEXT:    [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]]
 ; CHECK-NEXT:    [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]]
 ; CHECK-NEXT:    [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]])
 ; CHECK-NEXT:    [[TMP61:%.*]] = fneg fast float [[TMP60]]
 ; CHECK-NEXT:    [[TMP62:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP61]], float [[TMP57]], float [[TMP56]])
 ; CHECK-NEXT:    [[TMP63:%.*]] = fptosi float [[TMP60]] to i32
 ; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.fabs.f32(float [[TMP62]])
 ; CHECK-NEXT:    [[TMP65:%.*]] = call fast float @llvm.fabs.f32(float [[TMP57]])
 ; CHECK-NEXT:    [[TMP66:%.*]] = fcmp fast oge float [[TMP64]], [[TMP65]]
 ; CHECK-NEXT:    [[TMP67:%.*]] = select i1 [[TMP66]], i32 [[TMP55]], i32 0
 ; CHECK-NEXT:    [[TMP68:%.*]] = add i32 [[TMP63]], [[TMP67]]
-; CHECK-NEXT:    [[TMP69:%.*]] = trunc i32 [[TMP68]] to i15
-; CHECK-NEXT:    [[TMP70:%.*]] = sext i15 [[TMP69]] to i32
+; CHECK-NEXT:    [[TMP69:%.*]] = shl i32 [[TMP68]], 17
+; CHECK-NEXT:    [[TMP70:%.*]] = ashr i32 [[TMP69]], 17
 ; CHECK-NEXT:    [[TMP71:%.*]] = trunc i32 [[TMP70]] to i15
 ; CHECK-NEXT:    [[TMP72:%.*]] = insertelement <3 x i15> [[TMP48]], i15 [[TMP71]], i64 2
 ; CHECK-NEXT:    store <3 x i15> [[TMP72]], <3 x i15> addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = sdiv <3 x i15> %x, %y
   store <3 x i15> %r, <3 x i15> addrspace(1)* %out
   ret void

 ; CHECK-NEXT:    [[TMP15:%.*]] = fptosi float [[TMP12]] to i32
 ; CHECK-NEXT:    [[TMP16:%.*]] = call fast float @llvm.fabs.f32(float [[TMP14]])
 ; CHECK-NEXT:    [[TMP17:%.*]] = call fast float @llvm.fabs.f32(float [[TMP9]])
 ; CHECK-NEXT:    [[TMP18:%.*]] = fcmp fast oge float [[TMP16]], [[TMP17]]
 ; CHECK-NEXT:    [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP7]], i32 0
 ; CHECK-NEXT:    [[TMP20:%.*]] = add i32 [[TMP15]], [[TMP19]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = mul i32 [[TMP20]], [[TMP4]]
 ; CHECK-NEXT:    [[TMP22:%.*]] = sub i32 [[TMP3]], [[TMP21]]
-; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i15
-; CHECK-NEXT:    [[TMP24:%.*]] = sext i15 [[TMP23]] to i32
+; CHECK-NEXT:    [[TMP23:%.*]] = shl i32 [[TMP22]], 17
+; CHECK-NEXT:    [[TMP24:%.*]] = ashr i32 [[TMP23]], 17
 ; CHECK-NEXT:    [[TMP25:%.*]] = trunc i32 [[TMP24]] to i15
 ; CHECK-NEXT:    [[TMP26:%.*]] = insertelement <3 x i15> undef, i15 [[TMP25]], i64 0
 ; CHECK-NEXT:    [[TMP27:%.*]] = extractelement <3 x i15> [[X]], i64 1
 ; CHECK-NEXT:    [[TMP28:%.*]] = extractelement <3 x i15> [[Y]], i64 1
 ; CHECK-NEXT:    [[TMP29:%.*]] = sext i15 [[TMP27]] to i32
 ; CHECK-NEXT:    [[TMP30:%.*]] = sext i15 [[TMP28]] to i32
 ; CHECK-NEXT:    [[TMP31:%.*]] = xor i32 [[TMP29]], [[TMP30]]
 ; CHECK-NEXT:    [[TMP32:%.*]] = ashr i32 [[TMP31]], 30
 ; CHECK-NEXT:    [[TMP33:%.*]] = or i32 [[TMP32]], 1
 ; CHECK-NEXT:    [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float
 ; CHECK-NEXT:    [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float
 ; CHECK-NEXT:    [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]]
 ; CHECK-NEXT:    [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]]
 ; CHECK-NEXT:    [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]])
 ; CHECK-NEXT:    [[TMP39:%.*]] = fneg fast float [[TMP38]]
 ; CHECK-NEXT:    [[TMP40:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP39]], float [[TMP35]], float [[TMP34]])
 ; CHECK-NEXT:    [[TMP41:%.*]] = fptosi float [[TMP38]] to i32
 ; CHECK-NEXT:    [[TMP42:%.*]] = call fast float @llvm.fabs.f32(float [[TMP40]])
 ; CHECK-NEXT:    [[TMP43:%.*]] = call fast float @llvm.fabs.f32(float [[TMP35]])
 ; CHECK-NEXT:    [[TMP44:%.*]] = fcmp fast oge float [[TMP42]], [[TMP43]]
 ; CHECK-NEXT:    [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP33]], i32 0
 ; CHECK-NEXT:    [[TMP46:%.*]] = add i32 [[TMP41]], [[TMP45]]
 ; CHECK-NEXT:    [[TMP47:%.*]] = mul i32 [[TMP46]], [[TMP30]]
 ; CHECK-NEXT:    [[TMP48:%.*]] = sub i32 [[TMP29]], [[TMP47]]
-; CHECK-NEXT:    [[TMP49:%.*]] = trunc i32 [[TMP48]] to i15
-; CHECK-NEXT:    [[TMP50:%.*]] = sext i15 [[TMP49]] to i32
+; CHECK-NEXT:    [[TMP49:%.*]] = shl i32 [[TMP48]], 17
+; CHECK-NEXT:    [[TMP50:%.*]] = ashr i32 [[TMP49]], 17
 ; CHECK-NEXT:    [[TMP51:%.*]] = trunc i32 [[TMP50]] to i15
 ; CHECK-NEXT:    [[TMP52:%.*]] = insertelement <3 x i15> [[TMP26]], i15 [[TMP51]], i64 1
 ; CHECK-NEXT:    [[TMP53:%.*]] = extractelement <3 x i15> [[X]], i64 2
 ; CHECK-NEXT:    [[TMP54:%.*]] = extractelement <3 x i15> [[Y]], i64 2
 ; CHECK-NEXT:    [[TMP55:%.*]] = sext i15 [[TMP53]] to i32
 ; CHECK-NEXT:    [[TMP56:%.*]] = sext i15 [[TMP54]] to i32
 ; CHECK-NEXT:    [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]]
 ; CHECK-NEXT:    [[TMP58:%.*]] = ashr i32 [[TMP57]], 30
 ; CHECK-NEXT:    [[TMP59:%.*]] = or i32 [[TMP58]], 1
 ; CHECK-NEXT:    [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float
 ; CHECK-NEXT:    [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float
 ; CHECK-NEXT:    [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]]
 ; CHECK-NEXT:    [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]]
 ; CHECK-NEXT:    [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]])
 ; CHECK-NEXT:    [[TMP65:%.*]] = fneg fast float [[TMP64]]
 ; CHECK-NEXT:    [[TMP66:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP65]], float [[TMP61]], float [[TMP60]])
 ; CHECK-NEXT:    [[TMP67:%.*]] = fptosi float [[TMP64]] to i32
 ; CHECK-NEXT:    [[TMP68:%.*]] = call fast float @llvm.fabs.f32(float [[TMP66]])
 ; CHECK-NEXT:    [[TMP69:%.*]] = call fast float @llvm.fabs.f32(float [[TMP61]])
 ; CHECK-NEXT:    [[TMP70:%.*]] = fcmp fast oge float [[TMP68]], [[TMP69]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP59]], i32 0
 ; CHECK-NEXT:    [[TMP72:%.*]] = add i32 [[TMP67]], [[TMP71]]
 ; CHECK-NEXT:    [[TMP73:%.*]] = mul i32 [[TMP72]], [[TMP56]]
 ; CHECK-NEXT:    [[TMP74:%.*]] = sub i32 [[TMP55]], [[TMP73]]
-; CHECK-NEXT:    [[TMP75:%.*]] = trunc i32 [[TMP74]] to i15
-; CHECK-NEXT:    [[TMP76:%.*]] = sext i15 [[TMP75]] to i32
+; CHECK-NEXT:    [[TMP75:%.*]] = shl i32 [[TMP74]], 17
+; CHECK-NEXT:    [[TMP76:%.*]] = ashr i32 [[TMP75]], 17
 ; CHECK-NEXT:    [[TMP77:%.*]] = trunc i32 [[TMP76]] to i15
 ; CHECK-NEXT:    [[TMP78:%.*]] = insertelement <3 x i15> [[TMP52]], i15 [[TMP77]], i64 2
 ; CHECK-NEXT:    store <3 x i15> [[TMP78]], <3 x i15> addrspace(1)* [[OUT:%.*]]
 ; CHECK-NEXT:    ret void
 ;
   %r = srem <3 x i15> %x, %y
   store <3 x i15> %r, <3 x i15> addrspace(1)* %out
   ret void
 }