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Differential D72346

AMDGPU/GlobalISel: Add IMMPopCount xform
ClosedPublic

Authored by arsenm on Jan 7 2020, 9:41 AM.

Details

Reviewers
kerbowa
nhaehnle
Summary

Partially fixes BFE pattern import.

Diff Detail

Event Timeline

arsenm created this revision.Jan 7 2020, 9:41 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 7 2020, 9:41 AM
Herald added subscribers: Petar.Avramovic, hiraditya, t-tye and 7 others. · View Herald Transcript
nhaehnle accepted this revision.Jan 9 2020, 6:32 AM

LGTM

This revision is now accepted and ready to land.Jan 9 2020, 6:32 AM
arsenm closed this revision.Jan 9 2020, 7:33 AM

e71af775684a83f0d1d05ab5225d36830d5aa87e

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
3 lines
3 lines
6 lines

Diff 236619

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

Show First 20 Lines • Show All 208 Lines • ▼ Show 20 Lines
def gi_as_i32timm : GICustomOperandRenderer<"renderTruncImm32">, def gi_as_i32timm : GICustomOperandRenderer<"renderTruncImm32">,
GISDNodeXFormEquiv<as_i32timm>; GISDNodeXFormEquiv<as_i32timm>;
def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">, def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">,
GISDNodeXFormEquiv<NegateImm>; GISDNodeXFormEquiv<NegateImm>;
def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">, def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">,
GISDNodeXFormEquiv<bitcast_fpimm_to_i32>; GISDNodeXFormEquiv<bitcast_fpimm_to_i32>;
def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">,
GISDNodeXFormEquiv<IMMPopCount>;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Lines void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &MI) const; const MachineInstr &MI) const;
void renderNegateImm(MachineInstrBuilder &MIB, void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &MI) const; const MachineInstr &MI) const;
void renderBitcastImm(MachineInstrBuilder &MIB, void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &MI) const; const MachineInstr &MI) const;
void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &MI) const;
bool isInlineImmediate16(int64_t Imm) const; bool isInlineImmediate16(int64_t Imm) const;
bool isInlineImmediate32(int64_t Imm) const; bool isInlineImmediate32(int64_t Imm) const;
bool isInlineImmediate64(int64_t Imm) const; bool isInlineImmediate64(int64_t Imm) const;
bool isInlineImmediate(const APFloat &Imm) const; bool isInlineImmediate(const APFloat &Imm) const;
const SIInstrInfo &TII; const SIInstrInfo &TII;
const SIRegisterInfo &TRI; const SIRegisterInfo &TRI;
const AMDGPURegisterBankInfo &RBI; const AMDGPURegisterBankInfo &RBI;
Show All 16 Lines

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 2,122 Lines • ▼ Show 20 Linesvoid AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB,
if (MI.getOpcode() == TargetOpcode::G_FCONSTANT) if (MI.getOpcode() == TargetOpcode::G_FCONSTANT)
MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
else { else {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT"); assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
MIB.addImm(Op.getCImm()->getSExtValue()); MIB.addImm(Op.getCImm()->getSExtValue());
} }
} }
void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &MI) const {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
MIB.addImm(MI.getOperand(1).getCImm()->getValue().countPopulation());
}
bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const { bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const {
return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm()); return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm());
} }
bool AMDGPUInstructionSelector::isInlineImmediate32(int64_t Imm) const { bool AMDGPUInstructionSelector::isInlineImmediate32(int64_t Imm) const {
return AMDGPU::isInlinableLiteral32(Imm, STI.hasInv2PiInlineImm()); return AMDGPU::isInlinableLiteral32(Imm, STI.hasInv2PiInlineImm());
} }
bool AMDGPUInstructionSelector::isInlineImmediate64(int64_t Imm) const { bool AMDGPUInstructionSelector::isInlineImmediate64(int64_t Imm) const {
return AMDGPU::isInlinableLiteral64(Imm, STI.hasInv2PiInlineImm()); return AMDGPU::isInlinableLiteral64(Imm, STI.hasInv2PiInlineImm());
} }
bool AMDGPUInstructionSelector::isInlineImmediate(const APFloat &Imm) const { bool AMDGPUInstructionSelector::isInlineImmediate(const APFloat &Imm) const {
return TII.isInlineConstant(Imm); return TII.isInlineConstant(Imm);
} }