[mlir][spirv] Add lowering for std bit ops.

[mravishankar]

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td

28

Could you make this fit within 80 chars.

[mravishankar]

Could you add some serialization tests as well. Thanks

[denis13]

@mravishankar thanks for review, added serialization tests.

[mravishankar]

Thanks Denis for taking these up and driving them

[antiagainst]

Thanks!

mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.td

 
 def : BinaryOpPattern<SPV_Bool, AndOp, SPV_LogicalAndOp>;
 def : BinaryOpPattern<SPV_Bool, OrOp, SPV_LogicalOrOp>;
+def : BinaryOpPattern<SPV_Integer, AndOp, SPV_BitwiseAndOp>;
+def : BinaryOpPattern<SPV_Integer, OrOp, SPV_BitwiseOrOp>;
+def : BinaryOpPattern<SPV_Integer, ShiftLeftOp, SPV_ShiftLeftLogicalOp>;
+def : BinaryOpPattern<SPV_Integer, SignedShiftRightOp, SPV_ShiftRightArithmeticOp>;
+def : BinaryOpPattern<SPV_Integer, UnsignedShiftRightOp, SPV_ShiftRightLogicalOp>;
+def : BinaryOpPattern<SPV_Integer, XOrOp, SPV_BitwiseXorOp>;
 def : BinaryOpPattern<SPV_Float, AddFOp, SPV_FAddOp>;
 def : BinaryOpPattern<SPV_Float, DivFOp, SPV_FDivOp>;
 def : BinaryOpPattern<SPV_Float, MulFOp, SPV_FMulOp>;

mlir/test/Conversion/StandardToSPIRV/std-to-spirv.mlir

   return
 }
 
+//===----------------------------------------------------------------------===//
+// std bit ops
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @bitwise_scalar
+func @bitwise_scalar(%arg0 : i32, %arg1 : i32) {
+  // CHECK: spv.BitwiseAnd
+  %0 = and %arg0, %arg1 : i32
+  // CHECK: spv.BitwiseOr
+  %1 = or %arg0, %arg1 : i32
+  // CHECK: spv.BitwiseXor
+  %2 = xor %arg0, %arg1 : i32
+  return
+}
+
+// CHECK-LABEL: @bitwise_vector
+func @bitwise_vector(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) {
+  // CHECK: spv.BitwiseAnd
+  %0 = and %arg0, %arg1 : vector<4xi32>
+  // CHECK: spv.BitwiseOr
+  %1 = or %arg0, %arg1 : vector<4xi32>
+  // CHECK: spv.BitwiseXor
+  %2 = xor %arg0, %arg1 : vector<4xi32>
+  return
+}
+
+// CHECK-LABEL: @shift_scalar
+func @shift_scalar(%arg0 : i32, %arg1 : i32) {
+  // CHECK: spv.ShiftLeftLogical
+  %0 = shift_left %arg0, %arg1 : i32
+  // CHECK: spv.ShiftRightArithmetic
+  %1 = shift_right_signed %arg0, %arg1 : i32
+  // CHECK: spv.ShiftRightLogical
+  %2 = shift_right_unsigned %arg0, %arg1 : i32
+  return
+}
+
+// CHECK-LABEL: @shift_vector
+func @shift_vector(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) {
+  // CHECK: spv.ShiftLeftLogical
+  %0 = shift_left %arg0, %arg1 : vector<4xi32>
+  // CHECK: spv.ShiftRightArithmetic
+  %1 = shift_right_signed %arg0, %arg1 : vector<4xi32>
+  // CHECK: spv.ShiftRightLogical
+  %2 = shift_right_unsigned %arg0, %arg1 : vector<4xi32>
+  return
+}
+
 //===----------------------------------------------------------------------===//
 // std.cmpi
 //===----------------------------------------------------------------------===//

   return
 }
 
-// CHECK-LABEL: @logical_scalar_fail
-func @logical_scalar_fail(%arg0 : i32, %arg1 : i32) {
-  // CHECK-NOT: spv.LogicalAnd
-  %0 = and %arg0, %arg1 : i32
-  // CHECK-NOT: spv.LogicalOr
-  %1 = or %arg0, %arg1 : i32
-  return
-}
-
-// CHECK-LABEL: @logical_vector_fail
-func @logical_vector_fail(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) {
-  // CHECK-NOT: spv.LogicalAnd
-  %0 = and %arg0, %arg1 : vector<4xi32>
-  // CHECK-NOT: spv.LogicalOr
-  %1 = or %arg0, %arg1 : vector<4xi32>
-  return
-}
-
 //===----------------------------------------------------------------------===//
 // std.select
 //===----------------------------------------------------------------------===//