[ARM][LowOverheadLoops] Update liveness info

[samparker]

Summary

After expanding the pseudo instructions, update the liveness info. We do this in a post-order traversal of the loop, including its exit blocks and preheader(s). This has been extracted from D71837.

[dmgreen]

Looks interesting. Thanks for splitting it out, it makes it a lot clearer.

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

42

I believe there is already a PostOrderTraversal, but it deals with whole functions?

Maybe call this PostOrderTraversalForLoop, to distinguish it a little?

56

within the block -> within the loop ?

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

132

Is this r7 really dead?

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir

111

Is r4 really dead here? It's "returned" (kind of) right?

llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir

4

It can be good to update these checks in separate NFC patched so the diffs are clearly visible here.

[samparker]

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

132

Yeah, this is a weird one, it definitely doesn't look dead. I'll look more into CFI_INSTRUCTION.

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir

111

I reasoned that it's dead as far as liveness goes for the function... I'll have a look to see if there's some special handling or hooks for return values.

[samparker]

• Rebased.
• Renamed class to PostOrderLoopTraversal.

[samparker]

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

132

So this looks okay to me, just because the input code labels tPUSH as killing its operands even though the CFI pseudo instructions use them. LiveRegs works on MachineInstrs, whereas CFI is some pseudo MC instruction which doesn't even contain MC operands.

[samparker]

MachineBasicBlock has now been modified to iterate through the block to look for a return instruction. This then allows LivePhysRegs to add the callee saved regs for blocks where the return isn't the last instruction, such as when we have a POP in an IT block. This currently has the unwanted effect of meaning we can't remove all the instructions from the loop iteration count, see mve-tail-data-types where a callee saved register is used by the moves, but I think this should be resolved in D71837.

[dmgreen]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

577 ↗

(On Diff #236311)

This doesn't match the description above.

isReturnBlock seems to be used in a number of other places too. Would they all be OK with this change?

The one in addLiveOuts seems to mark the CSR's as live out of the block, with isn't really true. They are live out of POP the instruction. The live out's of the block are not modified. Can we modify recomputeLivenessFlags to consider isReturn instructions instead?

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

132

Perhaps put another way, what does an instruction with a dead def and no side-effects mean? Does it mean we can remove it? What about the frame-setup flag? Does that mean we can't remove it?

The recomputeLivenessFlags seems to already be used in ifcvt. Does this already happen in the same way there? Looking at tADDrSPi, it might have hasSideEffects set, because it otherwise causes miscompiles. Which might suggest that this isn't correct, but that it's a known issue at least.

[samparker]

The remaining instruction aren't actually removed in the next patch... because IsSafeToRemove isn't used for the setup code yet as it needs to operate over multiple blocks. This is something we're probably just going to need to live with for now.

[samparker]

llvm/include/llvm/CodeGen/MachineBasicBlock.h

577 ↗

(On Diff #236311)

The rest of code base seems ok with the change, but yes, trying it in LivePhysRegs sounds better, I'll give it a go.

[samparker]

Modified recomputeLivenessFlags to look at return instructions instead.

[dmgreen]

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

132

I went looking in IfCvt to see if I could get this to produce the same thing (it's the other place that uses this function, and does seem to run it on entry blocks after frame lowering). I couldn't see any examples of it marking registers as dead though.

Then I tried regenerating this function (from the IR above) and it was quite different. I think mostly because the -frame-pointer option has changed. With -frame-pointer=all the code is more similar, but the PUSH above is saving r7 (which kind of makes sense, it's pushed two lines up).

Any chance this file might have been modified to the point that it is not really valid any more?

[samparker]

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

132

I would say that an instruction with dead defs and no side-effects can be removed, so there's definitely an issue with the tADDrSPi... but I also wondered the same thing after not being able to re-generate the test too.

[samparker]

Regenerated the disjoint vcmp test.

[dmgreen]

LGTM then. Thanks.

[samparker]

I had to revert this due to buildbot failures. It seems the print order of liveins is non-deterministic... D72441 hopefully addresses this.

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

 
 using namespace llvm;
 
 #define DEBUG_TYPE "arm-low-overhead-loops"
 #define ARM_LOW_OVERHEAD_LOOPS_NAME "ARM Low Overhead Loops pass"
 
 namespace {
 
+  class PostOrderTraversal {
+    MachineLoop &ML;
+    MachineLoopInfo &MLI;
+    SmallPtrSet<MachineBasicBlock*, 4> Visited;
+    SmallVector<MachineBasicBlock*, 4> Order;
+
+  public:
+    PostOrderTraversal(MachineLoop &ML, MachineLoopInfo &MLI)
+      : ML(ML), MLI(MLI) { }
+
+    const SmallVectorImpl<MachineBasicBlock*> &getOrder() const {
+      return Order;
+    }
+
+    // Visit all the blocks within the block, as well as exit blocks and any
+    // blocks immediately dominating the header.
+    void ProcessLoop() {
+      std::function<void(MachineBasicBlock*)> Search = [this, &Search]
+        (MachineBasicBlock *MBB) -> void {
+        if (Visited.count(MBB))
+          return;
+
+        Visited.insert(MBB);
+        for (auto *Succ : MBB->successors()) {
+          if (!ML.contains(Succ))
+            continue;
+          Search(Succ);
+        }
+        Order.push_back(MBB);
+      };
+
+      // Insert exit blocks.
+      SmallVector<MachineBasicBlock*, 2> ExitBlocks;
+      ML.getExitBlocks(ExitBlocks);
+      for (auto *MBB : ExitBlocks)
+        Order.push_back(MBB);
+
+      // Then add the loop body.
+      Search(ML.getHeader());
+
+      // Then try the preheader and its predecessors.
+      std::function<void(MachineBasicBlock*)> GetPredecessor =
+        [this, &GetPredecessor] (MachineBasicBlock *MBB) -> void {
+        Order.push_back(MBB);
+        if (MBB->pred_size() == 1)
+          GetPredecessor(*MBB->pred_begin());
+      };
+
+      if (auto *Preheader = ML.getLoopPreheader())
+        GetPredecessor(Preheader);
+      else if (auto *Preheader = MLI.findLoopPreheader(&ML, true))
+        GetPredecessor(Preheader);
+    }
+  };
+
   struct PredicatedMI {
     MachineInstr *MI = nullptr;
     SetVector<MachineInstr*> Predicates;
 
   public:
     PredicatedMI(MachineInstr *I, SetVector<MachineInstr*> &Preds) :
     MI(I) {
       Predicates.insert(Preds.begin(), Preds.end());
if (LoLoop.Revert) {
     RemoveDeadBranch(LoLoop.Start);
     LoLoop.End = ExpandLoopEnd(LoLoop);
     RemoveDeadBranch(LoLoop.End);
     if (LoLoop.IsTailPredicationLegal()) {
       RemoveLoopUpdate(LoLoop);
       ConvertVPTBlocks(LoLoop);
     }
   }
+
+  PostOrderTraversal DFS(*LoLoop.ML, *MLI);
+  DFS.ProcessLoop();
+  const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder();
+  for (auto *MBB : PostOrder)
+    recomputeLiveIns(*MBB);
+
+  for (auto *MBB : reverse(PostOrder))
+    recomputeLivenessFlags(*MBB);
 }
 
 bool ARMLowOverheadLoops::RevertNonLoops() {
   LLVM_DEBUG(dbgs() << "ARM Loops: Reverting any remaining pseudos...\n");
   bool Changed = false;
 
   for (auto &MBB : *MF) {
     SmallVector<MachineInstr*, 4> Starts;

llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
 # CHECK-NOT: $lr = tMOVr $r0, 13
 # CHECK: $lr = t2DLS killed $r0
-# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1
+# CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
   entry:
     %scevgep = getelementptr i32, i32* %q, i32 -1

llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir

- { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.bb:
   ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r4, $r6, $lr
+  ; CHECK:   liveins: $r2, $r3, $r0, $r1, $r4, $r6, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 16
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r6, -12
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -16
-  ; CHECK:   $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
+  ; CHECK:   dead $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa $r7, 8
   ; CHECK:   $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
   ; CHECK:   tCBZ $r2, %bb.3
   ; CHECK: bb.1.bb3:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $r2, $r3, $r0, $r1
   ; CHECK:   $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg
   ; CHECK:   renamable $lr = t2ADDri renamable $r2, 3, 14, $noreg, $noreg
   ; CHECK:   $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg
   ; CHECK:   renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
   ; CHECK:   renamable $r12 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
   ; CHECK:   renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
   ; CHECK:   renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
   ; CHECK:   $vpr = VMSR_P0 $r12, 14, $noreg
   ; CHECK:   renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0
   ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
   ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
   ; CHECK:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
   ; CHECK:   $r3 = tMOVr $r0, 14, $noreg
-  ; CHECK:   $lr = t2DLS renamable $lr
+  ; CHECK:   $lr = t2DLS killed renamable $lr
   ; CHECK: bb.2.bb9:
   ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
-  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
+  ; CHECK:   liveins: $lr, $r2, $r12, $r0, $q0, $r1, $r3
   ; CHECK:   renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
   ; CHECK:   MVE_VPST 2, implicit $vpr
   ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
   ; CHECK:   renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
   ; CHECK:   renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
   ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
   ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
   ; CHECK:   renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep8, align 8)
   ; CHECK:   renamable $vpr = MVE_VCMPu32 renamable $q0, killed renamable $q2, 2, 0, $noreg
   ; CHECK:   MVE_VPST 8, implicit $vpr
   ; CHECK:   MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
   ; CHECK:   $r0 = tMOVr $r3, 14, $noreg
-  ; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
   ; CHECK: bb.3.bb27:
   ; CHECK:   $sp = tADDspi $sp, 1, 14, $noreg
   ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
   bb.0.bb:
     successors: %bb.3(0x30000000), %bb.1(0x50000000)
     liveins: $r0, $r1, $r2, $r3, $r4, $r6, $lr
 
     frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 
 # There are 2 SUBS, and the 2nd one is identified as the def.
 # Thus, the 1st is a use, and we shouldn't optimise away the SUBS.
 
 # CHECK:  bb.1.vector.body:
 # CHECK:    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
 # CHECK:    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
-# CHECK:    $lr = MVE_LETP renamable $lr, %bb.1
+# CHECK:    $lr = MVE_LETP killed renamable $lr, %bb.1
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main-arm-unknown-eabi"
 
   define dso_local void @use_before_def(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
   entry:
     %cmp8 = icmp sgt i32 %N, 0

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 
 # The CPSR is not dead:
 #
 #   renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
 #
 # We shouldn't optimise away the SUB.
 
 # CHECK:  bb.1.vector.body:
-# CHECK:    renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
-# CHECK:    $lr = MVE_LETP renamable $lr, %bb.1
+# CHECK:    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
+# CHECK:    $lr = MVE_LETP killed renamable $lr, %bb.1
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main-arm-unknown-eabi"
 
   define dso_local void @CPSR_not_dead(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
   entry:
     %cmp8 = icmp sgt i32 %N, 0

llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update3.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve,+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 
 # Local use after def, this mov is using r3:
 #
 #   $r2 = tMOVr killed $r3, 14, $noreg
 #
 # We should optimise away the SUB
 
 # CHECK:  bb.1.vector.body:
 # CHECK:    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
-# CHECK:    $lr = MVE_LETP renamable $lr, %bb.1
+# CHECK:    $lr = MVE_LETP killed renamable $lr, %bb.1
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main-arm-unknown-eabi"
 
   define dso_local void @local_use_after_def(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32* noalias nocapture readonly %C, i32 %N) local_unnamed_addr #0 {
   entry:
     %cmp8 = icmp sgt i32 %N, 0

llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
 
 # CHECK-NOT: DoLoopStart
 # CHECK-NOT: DLS
 # CHECK: bb.1.for.body:
 # CHECK:      $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
 # CHECK-NOT:  t2CMPri $lr
-# CHECK:      tBcc %bb.3, 1, $cpsr
+# CHECK:      tBcc %bb.3, 1, killed $cpsr
 # CHECK:      tB %bb.2, 14, $noreg
 # CHECK: bb.2.for.cond.cleanup:
 # CHECK: bb.3.for.header:
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   

llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll

 ; CHECK-GLOBAL-NOT: LoopEnd
 
 ; CHECK: ne_and_guard
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
 ; CHECK:   tBcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
-; CHECK:   $lr = t2DLS renamable $lr
+; CHECK:   $lr = t2DLS killed renamable $lr
 ; CHECK: bb.2.while.body:
-; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
 define void @ne_and_guard(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) {
 entry:
   %brmerge.demorgan = and i1 %t1, %t2
   %cmp6 = icmp ne i32 %N, 0
   %or.cond = and i1 %brmerge.demorgan, %cmp6
   br i1 %or.cond, label %while.body, label %if.end
 
 while.body:                                       ; preds = %while.body, %entry

 
 ; TODO: This could generate WLS
 ; CHECK: ne_preheader
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
 ; CHECK:   tBcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
-; CHECK:   $lr = t2DLS renamable $lr
+; CHECK:   $lr = t2DLS killed renamable $lr
 ; CHECK: bb.2.while.body:
-; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
 define void @ne_preheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) {
 entry:
   %brmerge.demorgan = and i1 %t1, %t2
   br i1 %brmerge.demorgan, label %while.preheader, label %if.end
 
 while.preheader:                                  ; preds = %entry
   %cmp = icmp ne i32 %N, 0
   br i1 %cmp, label %while.body, label %if.end

 
 ; TODO: This could generate WLS
 ; CHECK: eq_preheader
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
 ; CHECK:   tBcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
-; CHECK:   $lr = t2DLS renamable $lr
+; CHECK:   $lr = t2DLS killed renamable $lr
 ; CHECK: bb.2.while.body:
-; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
 define void @eq_preheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) {
 entry:
   %brmerge.demorgan = and i1 %t1, %t2
   br i1 %brmerge.demorgan, label %while.preheader, label %if.end
 
 while.preheader:                                  ; preds = %entry
   %cmp = icmp eq i32 %N, 0
   br i1 %cmp, label %if.end, label %while.body

 
 ; TODO: This could generate WLS
 ; CHECK: ne_prepreheader
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   t2CMPri renamable $lr, 0
 ; CHECK:   tBcc %bb.3
 ; CHECK: bb.1.while.body.preheader:
-; CHECK:   $lr = t2DLS renamable $lr
+; CHECK:   $lr = t2DLS killed renamable $lr
 ; CHECK: bb.2.while.body:
-; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
 define void @ne_prepreheader(i1 zeroext %t1, i1 zeroext %t2, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) {
 entry:
   %cmp = icmp ne i32 %N, 0
   br i1 %cmp, label %while.preheader, label %if.end
 
 while.preheader:                                  ; preds = %entry
   %brmerge.demorgan = and i1 %t1, %t2
   br i1 %brmerge.demorgan, label %while.body, label %if.end

 
 if.end:                                           ; preds = %while.body, %while.preheader, %entry
   ret void
 }
 
 ; CHECK: be_ne
 ; CHECK: body:
 ; CHECK: bb.0.entry:
-; CHECK:   $lr = t2DLS renamable $lr
+; CHECK:   $lr = t2DLS killed renamable $lr
 ; CHECK: bb.1.do.body:
-; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.1
+; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.1
 define void @be_ne(i32* nocapture %a, i32* nocapture readonly %b, i32 %N) {
 entry:
   %cmp = icmp ne i32 %N, 0
   %sub = sub i32 %N, 1
   %be = select i1 %cmp, i32 0, i32 %sub
   %cmp.1 = icmp ne i32 %be, 0
   br i1 %cmp.1, label %do.body, label %if.end
 

 ; TODO: Remove the tMOVr in the preheader!
 ; CHECK: ne_trip_count
 ; CHECK: body:
 ; CHECK: bb.0.entry:
 ; CHECK:   $lr = t2WLS $r3, %bb.3
 ; CHECK: bb.1.do.body.preheader:
 ; CHECK:   $lr = tMOVr
 ; CHECK: bb.2.do.body:
-; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
 define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) {
 entry:
   br label %do.body.preheader
 
 do.body.preheader:
   %cmp = icmp ne i32 %N, 0
   br i1 %cmp, label %do.body, label %if.end
 

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
-# CHECK: $lr = t2DLS $r0
+# CHECK: $lr = t2DLS killed $r0
 # CHECK-NOT: $lr = tMOVr $r0
-# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1
+# CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
   entry:
     %scevgep = getelementptr i32, i32* %q, i32 -1

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir

- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: start_before_elems
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r4, $lr
+  ; CHECK:   liveins: $r1, $r0, $r2, $r3, $r4, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
   ; CHECK:   renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
   ; CHECK:   t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
   ; CHECK:   t2IT 0, 8, implicit-def $itstate
-  ; CHECK:   tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
+  ; CHECK:   tPOP_RET 0, killed $cpsr, def dead $r4, def $pc, implicit killed $itstate
   ; CHECK:   renamable $r12 = t2LSRri killed renamable $r3, 1, 14, $noreg, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
   ; CHECK:   $lr = MVE_DLSTP_32 renamable $r12
   ; CHECK: bb.1.vector.body:
   ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
+  ; CHECK:   liveins: $lr, $r0, $r12, $r2, $r3, $r1
   ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
   ; CHECK:   renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
   ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
   ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
   ; CHECK:   renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
   ; CHECK:   renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.1
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
   ; CHECK: bb.2.for.cond.cleanup:
   ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $pc
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1, $r2, $r3, $r4, $lr
 
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8

llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir

- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: start_before_elems
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r4, $lr
+  ; CHECK:   liveins: $r1, $r0, $r2, $r3, $r4, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
   ; CHECK:   renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
   ; CHECK:   t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
   ; CHECK:   t2IT 0, 8, implicit-def $itstate
-  ; CHECK:   tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
+  ; CHECK:   tPOP_RET 0, killed $cpsr, def dead $r4, def $pc, implicit killed $itstate
   ; CHECK:   $r12 = t2MOVr killed $r3, 14, $noreg, $noreg
   ; CHECK:   renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg
   ; CHECK:   $lr = MVE_DLSTP_32 renamable $r12
   ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
   ; CHECK: bb.1.vector.body:
   ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
+  ; CHECK:   liveins: $lr, $r0, $r12, $r2, $r3, $r1
   ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
   ; CHECK:   renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
   ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
   ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
   ; CHECK:   renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
   ; CHECK:   renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.1
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
   ; CHECK: bb.2.for.cond.cleanup:
   ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $pc
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1, $r2, $r3, $r4, $lr
 
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8

llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir

- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: start_before_elems
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r4, $lr
+  ; CHECK:   liveins: $r1, $r0, $r2, $r3, $r4, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
   ; CHECK:   renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
   ; CHECK:   t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
   ; CHECK:   t2IT 0, 8, implicit-def $itstate
-  ; CHECK:   tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
+  ; CHECK:   tPOP_RET 0, killed $cpsr, def dead $r4, def $pc, implicit killed $itstate
   ; CHECK:   $r12 = t2MOVr killed $r3, 14, $noreg, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
   ; CHECK:   renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg
   ; CHECK:   $lr = MVE_DLSTP_32 renamable $r12
   ; CHECK: bb.1.vector.body:
   ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
+  ; CHECK:   liveins: $lr, $r0, $r12, $r2, $r3, $r1
   ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg
   ; CHECK:   renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1)
   ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg
   ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
   ; CHECK:   renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1)
   ; CHECK:   renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.1
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
   ; CHECK: bb.2.for.cond.cleanup:
   ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $pc
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1, $r2, $r3, $r4, $lr
 
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8

llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir

 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK:      body:
 # CHECK:      bb.0.entry:
 # CHECK:        t2CMPri $r3, 0, 14
-# CHECK-NEXT:   t2Bcc %bb.3, 0, $cpsr
+# CHECK-NEXT:   t2Bcc %bb.3, 0, killed $cpsr
 # CHECK-NEXT:   tB %bb.1
 # CHECK:      bb.1.do.body.preheader:
 # CHECK:        $lr = tMOVr killed $r3
 # CHECK:      bb.2.do.body:
 # CHECK:        $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
-# CHECK-NEXT:   t2Bcc %bb.2, 1, $cpsr
+# CHECK-NEXT:   t2Bcc %bb.2, 1, killed $cpsr
 # CHECK-NEXT:   tB %bb.3, 14
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define void @ne_trip_count(i1 zeroext %t1, i32* nocapture %a, i32* nocapture readonly %b, i32 %N) #0 {
   entry:

llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir

 # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
-# CHECK: $lr = t2DLS $r0
+# CHECK: $lr = t2DLS killed $r0
 # CHECK: $lr = tMOVr $r0, 14
-# CHECK: $lr = t2LEUpdate renamable $lr, %bb.2
+# CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
 
 # TODO: Explore the preheader to remove the redundant tMOVr
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {

llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir

 # RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK: entry:
 # CHECK: $lr = t2DLS
 # CHECK: for.body:
-# CHECK: $lr = t2LEUpdate renamable $lr
+# CHECK: $lr = t2LEUpdate killed renamable $lr
 
 --- |
   ; ModuleID = 'size-limit.ll'
   source_filename = "size-limit.ll"
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
   
   define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {

llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir

- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: do_copy
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r7, $lr
+  ; CHECK:   liveins: $r2, $r1, $r7, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
   ; CHECK:   renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
   ; CHECK:   renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
-  ; CHECK:   $lr = tMOVr killed $r0, 14, $noreg
+  ; CHECK:   $lr = tMOVr $r0, 14, $noreg
   ; CHECK: bb.1.while.body:
   ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2
+  ; CHECK:   liveins: $lr, $r0, $r2, $r1
   ; CHECK:   renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
   ; CHECK:   tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
   ; CHECK:   $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg
   ; CHECK:   t2IT 2, 8, implicit-def $itstate
-  ; CHECK:   renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
+  ; CHECK:   renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
   ; CHECK:   early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+  ; CHECK:   renamable $lr = tMOVr killed $lr, 14, $noreg
   ; CHECK:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
-  ; CHECK:   tBcc %bb.1, 1, $cpsr
+  ; CHECK:   tBcc %bb.1, 1, killed $cpsr
   ; CHECK:   tB %bb.2, 14, $noreg
   ; CHECK: bb.2.while.end:
   ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14, $noreg
   ; CHECK:   tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
   bb.0.entry:
     successors: %bb.1(0x80000000)
     liveins: $r0, $r1, $r2, $r7, $lr
 

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir

- { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.bb:
   ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $lr
+  ; CHECK:   liveins: $r1, $r2, $r0, $r3, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   $r7 = frame-setup tMOVr $sp, 14, $noreg
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
   ; CHECK:   $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
   ; CHECK:   tCBZ $r2, %bb.3
   ; CHECK: bb.1.bb3:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $r1, $r2, $r0, $r3
   ; CHECK:   renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg
   ; CHECK:   renamable $lr = t2MOVi 1, 14, $noreg, $noreg
   ; CHECK:   renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg
   ; CHECK:   $vpr = VMSR_P0 killed $r3, 14, $noreg
   ; CHECK:   renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
   ; CHECK:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
   ; CHECK:   $r3 = tMOVr $r0, 14, $noreg
   ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg
-  ; CHECK:   $lr = t2DLS renamable $lr
+  ; CHECK:   $lr = t2DLS killed renamable $lr
   ; CHECK: bb.2.bb9:
   ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $lr, $r2, $r3, $r0, $r1
   ; CHECK:   renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
   ; CHECK:   MVE_VPST 4, implicit $vpr
   ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
   ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4, !tbaa !3)
   ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
   ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
   ; CHECK:   MVE_VPST 4, implicit $vpr
   ; CHECK:   renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr
   ; CHECK:   renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4, !tbaa !3)
   ; CHECK:   renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   MVE_VPST 8, implicit $vpr
   ; CHECK:   MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4, !tbaa !3)
   ; CHECK:   $r0 = tMOVr $r3, 14, $noreg
-  ; CHECK:   $lr = t2LEUpdate renamable $lr, %bb.2
+  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
   ; CHECK: bb.3.bb27:
   ; CHECK:   $sp = tADDspi $sp, 1, 14, $noreg
   ; CHECK:   tPOP_RET 14, $noreg, def $r7, def $pc
   bb.0.bb:
     successors: %bb.3(0x30000000), %bb.1(0x50000000)
     liveins: $r0, $r1, $r2, $r3, $lr
 
     frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir

- { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: test
   ; CHECK: bb.0.bb:
   ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $lr
+  ; CHECK:   liveins: $r0, $r2, $r1, $r3, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   $r7 = frame-setup tMOVr $sp, 14, $noreg
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_register $r7
   ; CHECK:   $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
   ; CHECK:   tCBZ $r2, %bb.3
   ; CHECK: bb.1.bb3:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $r0, $r2, $r1, $r3
   ; CHECK:   $vpr = VMSR_P0 killed $r3, 14, $noreg
   ; CHECK:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
   ; CHECK:   $r3 = tMOVr $r0, 14, $noreg
-  ; CHECK:   $lr = MVE_DLSTP_32 renamable $r2
+  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
   ; CHECK: bb.2.bb9:
   ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $lr, $r3, $r1, $r0
   ; CHECK:   renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
   ; CHECK:   MVE_VPST 4, implicit $vpr
   ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4, !tbaa !3)
   ; CHECK:   renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4, !tbaa !3)
   ; CHECK:   renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   MVE_VPST 8, implicit $vpr
   ; CHECK:   MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4, !tbaa !3)
   ; CHECK:   $r0 = tMOVr $r3, 14, $noreg
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.2
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
   ; CHECK: bb.3.bb27:
   ; CHECK:   $sp = tADDspi $sp, 1, 14, $noreg
   ; CHECK:   tPOP_RET 14, $noreg, def $r7, def $pc
   bb.0.bb:
     successors: %bb.3(0x30000000), %bb.1(0x50000000)
     liveins: $r0, $r1, $r2, $r3, $lr
 
     frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp

llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - | FileCheck %s
-
 # TODO: Remove the lr = tMOVr
-# CHECK: body:
-# CHECK: entry:
-# CHECK:   $lr = t2WLS $r2, [[EXIT:%bb[.0-9]+]]
-# CHECK: [[PREHEADER:bb[.0-9a-z]+]]:
-# CHECK:   $lr = tMOVr killed $r2
-# CHECK: [[BODY:bb[.0-9a-z]+]]:
-# CHECK:   $lr = t2LEUpdate renamable $lr
 
 --- |
   target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
   target triple = "thumbv8.1m.main"
-  
   define dso_local arm_aapcscc void @copy(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
   entry:
     %0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
     br i1 %0, label %while.body.preheader, label %while.end
-  
   while.body.preheader:                             ; preds = %entry
     %scevgep = getelementptr i16, i16* %a, i32 -1
     %scevgep3 = getelementptr i16, i16* %b, i32 -1
     br label %while.body
-  
   while.body:                                       ; preds = %while.body, %while.body.preheader
     %lsr.iv4 = phi i16* [ %scevgep3, %while.body.preheader ], [ %scevgep5, %while.body ]
     %lsr.iv = phi i16* [ %scevgep, %while.body.preheader ], [ %scevgep1, %while.body ]
     %1 = phi i32 [ %3, %while.body ], [ %N, %while.body.preheader ]
     %scevgep7 = getelementptr i16, i16* %lsr.iv, i32 1
     %scevgep4 = getelementptr i16, i16* %lsr.iv4, i32 1
     %2 = load i16, i16* %scevgep4, align 2
     store i16 %2, i16* %scevgep7, align 2
     %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %1, i32 1)
     %4 = icmp ne i32 %3, 0
     %scevgep1 = getelementptr i16, i16* %lsr.iv, i32 1
     %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 1
     br i1 %4, label %while.body, label %while.end
-  
   while.end:                                        ; preds = %while.body, %entry
     ret void
   }
-  
   declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
   declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
-  
   attributes #0 = { noduplicate nounwind }
   attributes #1 = { nounwind }
 
 ...
 ---
 name:            copy
 alignment:       2
 exposesReturnsTwice: false
frameInfo:
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
   localFrameSize:  0
   savePoint:       ''
   restorePoint:    ''
 fixedStack:      []
 stack:
-  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
-  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
-      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
+  ; CHECK-LABEL: name: copy
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
+  ; CHECK:   liveins: $r0, $r2, $r1, $r7, $lr
+  ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
+  ; CHECK:   dead $lr = t2WLS $r2, %bb.3
+  ; CHECK: bb.1.while.body.preheader:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   liveins: $r0, $r2, $r1
+  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
+  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
+  ; CHECK:   $lr = tMOVr killed $r2, 14, $noreg
+  ; CHECK: bb.2.while.body:
+  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+  ; CHECK:   liveins: $lr, $r0, $r1
+  ; CHECK:   renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
+  ; CHECK:   early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
+  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
+  ; CHECK: bb.3.while.end:
+  ; CHECK:   tPOP_RET 14, $noreg, def $r7, def $pc
   bb.0.entry:
     successors: %bb.1(0x40000000), %bb.3(0x40000000)
     liveins: $r0, $r1, $r2, $r7, $lr
-  
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r7, -8
     t2WhileLoopStart $r2, %bb.3, implicit-def dead $cpsr
     tB %bb.1, 14, $noreg
-  
   bb.1.while.body.preheader:
     successors: %bb.2(0x80000000)
     liveins: $r0, $r1, $r2
-  
     renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg
     renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg
     $lr = tMOVr killed $r2, 14, $noreg
-  
   bb.2.while.body:
     successors: %bb.2(0x7c000000), %bb.3(0x04000000)
     liveins: $lr, $r0, $r1
-  
     renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4)
     early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7)
     renamable $lr = t2LoopDec killed renamable $lr, 1
     t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
     tB %bb.3, 14, $noreg
-  
   bb.3.while.end:
     tPOP_RET 14, $noreg, def $r7, def $pc
 
 ...

llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir

body:             |
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
   ; CHECK:   $lr = MVE_WLSTP_8 renamable $r3, %bb.1
   ; CHECK:   tB %bb.3, 14, $noreg
   ; CHECK: bb.1.vector.ph:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $lr, $r1, $r2, $r3, $r0
   ; CHECK:   renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
   ; CHECK: bb.2.vector.body:
   ; CHECK:   successors: %bb.3(0x04000000), %bb.2(0x7c000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
+  ; CHECK:   liveins: $lr, $r12, $r2, $r3, $r0, $r1
   ; CHECK:   renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg
   ; CHECK:   renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep45, align 1)
   ; CHECK:   renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg
   ; CHECK:   renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep23, align 1)
   ; CHECK:   renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg
   ; CHECK:   renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
   ; CHECK:   renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg :: (store 16 into %ir.scevgep1, align 1)
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.2
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
   ; CHECK: bb.3.for.cond.cleanup:
   ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $pc
   bb.0.entry:
     successors: %bb.3(0x40000000), %bb.1(0x40000000)
     liveins: $r0, $r1, $r2, $r3, $r4, $lr
 
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: test_wlstp16
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r7, $lr
+  ; CHECK:   liveins: $r1, $r3, $r0, $r2, $r7, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   $lr = MVE_WLSTP_16 renamable $r3, %bb.1
   ; CHECK:   tB %bb.2, 14, $noreg
   ; CHECK: bb.1.vector.body:
   ; CHECK:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
+  ; CHECK:   liveins: $lr, $r3, $r0, $r2, $r1
   ; CHECK:   renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg :: (load 16 from %ir.lsr.iv57, align 2)
   ; CHECK:   renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 2)
   ; CHECK:   renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
   ; CHECK:   MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 2)
   ; CHECK:   renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg
   ; CHECK:   renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg
   ; CHECK:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg
   ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14, $noreg
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.1
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
   ; CHECK: bb.2.for.cond.cleanup:
   ; CHECK:   tPOP_RET 14, $noreg, def $r7, def $pc
   bb.0.entry:
     successors: %bb.2(0x40000000), %bb.1(0x40000000)
     liveins: $r0, $r1, $r2, $r3, $r7, $lr
 
     frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   ; CHECK-LABEL: name: test_wlstp32
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.4(0x40000000), %bb.1(0x40000000)
-  ; CHECK:   liveins: $r0, $r1, $r2, $r7, $lr
+  ; CHECK:   liveins: $r1, $r2, $r0, $r7, $lr
   ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
   ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
   ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
   ; CHECK:   renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
   ; CHECK:   $lr = MVE_WLSTP_32 $r2, %bb.1
   ; CHECK:   tB %bb.4, 14, $noreg
   ; CHECK: bb.1.vector.ph:
   ; CHECK:   successors: %bb.2(0x80000000)
-  ; CHECK:   liveins: $lr, $r0, $r1, $r2
+  ; CHECK:   liveins: $r2, $r0, $lr, $r1
   ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
   ; CHECK: bb.2.vector.body:
   ; CHECK:   successors: %bb.3(0x04000000), %bb.2(0x7c000000)
-  ; CHECK:   liveins: $lr, $q1, $r0, $r1, $r2
-  ; CHECK:   $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0
+  ; CHECK:   liveins: $r2, $r0, $lr, $r1, $q1
+  ; CHECK:   $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
   ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 4)
   ; CHECK:   renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 0, killed $noreg :: (load 16 from %ir.lsr.iv1, align 4)
   ; CHECK:   $r3 = tMOVr $r2, 14, $noreg
   ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
   ; CHECK:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg
   ; CHECK:   renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg
   ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg
   ; CHECK:   renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
-  ; CHECK:   $lr = MVE_LETP renamable $lr, %bb.2
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
   ; CHECK: bb.3.middle.block:
   ; CHECK:   successors: %bb.4(0x80000000)
-  ; CHECK:   liveins: $q0, $q1, $r3
+  ; CHECK:   liveins: $q1, $q0, $r3
   ; CHECK:   renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg
   ; CHECK:   renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr
   ; CHECK:   renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
   ; CHECK: bb.4.for.cond.cleanup:
   ; CHECK:   liveins: $r12
   ; CHECK:   $r0 = tMOVr killed $r12, 14, $noreg
   ; CHECK:   tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
   bb.0.entry: