[ARM][MVE] Tail predicate bottom/top muls.

[samparker]

Summary

Add VMULL and VQDMULL variants to our tail predication white list. These instructions just access different parts of their operands so tail predication shouldn't cause us a problem.

[SjoerdMeijer]

Looks reasonable

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
   let Inst{28} = bit_28;
   let Inst{21-20} = bits_21_20;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b1;
   let Inst{12} = T;
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VMULL_m<MVEVectorVTInfo VTI,
                        SDNode unpred_op, Intrinsic pred_int,
                        bit Top, string cstr=""> {
   def "" : MVE_VMULL<"vmull" # !if(Top, "t", "b"), VTI.Suffix, VTI.Unsigned,
                      VTI.Size, Top, cstr>;
 
class MVE_VQDMULL<string iname, string suffix, bit size, bit T,
   let Inst{28} = size;
   let Inst{21-20} = 0b11;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = T;
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b1;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VQDMULL_halves<string suffix, bit size, string cstr=""> {
   def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0, cstr>;
   def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1, cstr>;
 }
 
 defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
class MVE_VQDMULL_qr<string iname, string suffix, bit size,
   : MVE_qDest_rSrc<iname, suffix, cstr, pattern> {
 
   let Inst{28} = size;
   let Inst{21-20} = 0b11;
   let Inst{16} = 0b0;
   let Inst{12} = T;
   let Inst{8} = 0b1;
   let Inst{5} = 0b1;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VQDMULL_qr_halves<string suffix, bit size, string cstr=""> {
   def bh : MVE_VQDMULL_qr<"vqdmullb", suffix, size, 0b0, cstr>;
   def th : MVE_VQDMULL_qr<"vqdmullt", suffix, size, 0b1, cstr>;
 }
 
 defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<"s16", 0b0>;

llvm/unittests/Target/ARM/MachineInstrTest.cpp

 
 using namespace llvm;
 
 // Test for instructions that aren't immediately obviously valid within a
 // tail-predicated loop. This should be marked up in their tablegen
 // descriptions. Currently we, conservatively, disallow:
 // - cross beat carries.
 // - narrowing of results.
-// - top/bottom operations.
 // - complex operations.
 // - horizontal operations.
 // - byte swapping.
 // - interleaved memory instructions.
 // TODO: Add to this list once we can handle them safely.
 TEST(MachineInstrValidTailPredication, IsCorrect) {
 
   using namespace ARM;
auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VLDRWU32_qi_pre:
     case MVE_VLDRWU32_rq:
     case MVE_VLDRWU32_rq_u:
     case MVE_VMOVimmf32:
     case MVE_VMOVimmi16:
     case MVE_VMOVimmi32:  
     case MVE_VMOVimmi64:
     case MVE_VMOVimmi8: 
+    case MVE_VMULLBp16:
+    case MVE_VMULLBp8:
+    case MVE_VMULLBs16:
+    case MVE_VMULLBs32:
+    case MVE_VMULLBs8:
+    case MVE_VMULLBu16:
+    case MVE_VMULLBu32:
+    case MVE_VMULLBu8:
+    case MVE_VMULLTp16:
+    case MVE_VMULLTp8:
+    case MVE_VMULLTs16:
+    case MVE_VMULLTs32:
+    case MVE_VMULLTs8:
+    case MVE_VMULLTu16:
+    case MVE_VMULLTu32:
+    case MVE_VMULLTu8:  
     case MVE_VMUL_qr_f16:
     case MVE_VMUL_qr_f32:
     case MVE_VMUL_qr_i16:
     case MVE_VMUL_qr_i32:
     case MVE_VMUL_qr_i8:
     case MVE_VMULf16:
     case MVE_VMULf32:
     case MVE_VMULi16:
auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VQADD_qr_u32:
     case MVE_VQADD_qr_u8:
     case MVE_VQADDs16:
     case MVE_VQADDs32:
     case MVE_VQADDs8:
     case MVE_VQADDu16:
     case MVE_VQADDu32:
     case MVE_VQADDu8:
+    case MVE_VQDMULL_qr_s16bh:
+    case MVE_VQDMULL_qr_s16th:
+    case MVE_VQDMULL_qr_s32bh:
+    case MVE_VQDMULL_qr_s32th:
+    case MVE_VQDMULLs16bh:
+    case MVE_VQDMULLs16th:
+    case MVE_VQDMULLs32bh:
+    case MVE_VQDMULLs32th:
     case MVE_VQNEGs16:
     case MVE_VQNEGs32:
     case MVE_VQNEGs8:
     case MVE_VQRSHL_by_vecs16:
     case MVE_VQRSHL_by_vecs32:
     case MVE_VQRSHL_by_vecs8:
     case MVE_VQRSHL_by_vecu16:
     case MVE_VQRSHL_by_vecu32: