[ARM][MVE] Make VPT invalid for tail predication

[samparker]

Summary

We've been marking VPT incompatible instructions as invalid for tail predication too, though this may not strictly be true. VPT are incompatible and, unless its the first predicate def in a loop, they shouldn't be compatible for tail predication either. D71107 is currently getting around this with an explicit check.

[SjoerdMeijer]

Can we test this?

D71107 is currently getting around this with an explicit check.

Are you removing the check, and is it it tested there?

[samparker]

In D71410#1781684, @SjoerdMeijer wrote:

Can we test this?

Most of this is a test change!

[SjoerdMeijer]

Most of this is a test change!

Ha, yep, after adding that comment, I noticed that too, but thought to wait for your reply anyway, I was perhaps thinking about codegen tests.

Anyway, looks like a simple fix, LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   let Inst{16} = 0b1;
   let Inst{15-13} = Mk{2-0};
   let Inst{12} = fc{2};
   let Inst{11-8} = 0b1111;
   let Inst{7} = fc{0};
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
-  let validForTailPredication = 1;
 }
 
 class MVE_VPTt1<string suffix, bits<2> size, dag iops>
   : MVE_VPT<suffix, size, iops, "$fc, $Qn, $Qm"> {
   bits<4> Qm;
   bits<4> Mk;
 
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = fc{1};
-  let validForTailPredication = 1;
 }
 
 class MVE_VPTt1i<string suffix, bits<2> size>
  : MVE_VPTt1<suffix, size,
            (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_i:$fc)> {
   let Inst{12} = 0b0;
   let Inst{0} = 0b0;
 }
class MVE_VPTf<string suffix, bit size, dag iops, string asm, list<dag> pattern=[]>
   let Inst{15-13} = Mk{2-0};
   let Inst{12} = fc{2};
   let Inst{11-8} = 0b1111;
   let Inst{7} = fc{0};
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
   let Predicates = [HasMVEFloat];
-  let validForTailPredication = 1;
 }
 
 class MVE_VPTft1<string suffix, bit size>
   : MVE_VPTf<suffix, size, (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_fp:$fc),
           "$fc, $Qn, $Qm"> {
   bits<3> fc;
   bits<4> Qm;
 

llvm/unittests/Target/ARM/MachineInstrTest.cpp

auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VORRIZ0v8i16:
     case MVE_VORRIZ16v4i32:
     case MVE_VORRIZ24v4i32:
     case MVE_VORRIZ8v4i32:
     case MVE_VORRIZ8v8i16:
     case MVE_VPNOT:
     case MVE_VPSEL:
     case MVE_VPST:  
-    case MVE_VPTv16i8:
-    case MVE_VPTv16i8r:
-    case MVE_VPTv16s8:
-    case MVE_VPTv16s8r:
-    case MVE_VPTv16u8:  
-    case MVE_VPTv16u8r:
-    case MVE_VPTv4f32:
-    case MVE_VPTv4f32r:
-    case MVE_VPTv4i32:
-    case MVE_VPTv4i32r:
-    case MVE_VPTv4s32:
-    case MVE_VPTv4s32r:
-    case MVE_VPTv4u32:
-    case MVE_VPTv4u32r:
-    case MVE_VPTv8f16:
-    case MVE_VPTv8f16r:
-    case MVE_VPTv8i16:
-    case MVE_VPTv8i16r:
-    case MVE_VPTv8s16:
-    case MVE_VPTv8s16r:
-    case MVE_VPTv8u16:
-    case MVE_VPTv8u16r:
     case MVE_VQABSs16:
     case MVE_VQABSs32:
     case MVE_VQABSs8:
     case MVE_VQADD_qr_s16:
     case MVE_VQADD_qr_s32:
     case MVE_VQADD_qr_s8:
     case MVE_VQADD_qr_u16:
     case MVE_VQADD_qr_u32: