AMDGPU: Split denormal mode tracking bits

[arsenm]

Summary

Prepare to accurately track the future denormal-fp-math attribute
changes. The way to actually set these separately is not wired in yet.

This is just a mechanical change, and mostly still assumes the input
and output mode match. This should be refined for some cases. For
example, fcanonicalize lowering should use the flushing variant if
either input or output flushing is enabled

[rampitec]

LGTM

[arsenm]

1024b73ef5930148bf8016150aa5660f5bb9d153

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 using namespace llvm::AMDGPU::HSAMD;
 
-// TODO: This should get the default rounding mode from the kernel. We just set
-// the default here, but this could change if the OpenCL rounding mode pragmas
-// are used.
+// This should get the default rounding mode from the kernel. We just set the
+// default here, but this could change if the OpenCL rounding mode pragmas are
+// used.
 //
 // The denormal mode here should match what is reported by the OpenCL runtime
 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
 //
 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
 // precision, and leaves single precision to flush all and does not report
 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
 // CL_FP_DENORM for both.
 //
 // FIXME: It seems some instructions do not support single precision denormals
 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
 // and sin_f32, cos_f32 on most parts).
 
 // We want to use these instructions, and using fp32 denormals also causes
 // instructions to run at the double precision rate for the device so it's
 // probably best to just report no single precision denormals.
 static uint32_t getFPMode(AMDGPU::SIModeRegisterDefaults Mode) {
-
-  // TODO: Is there any real use for the flush in only / flush out only modes?
-  uint32_t FP32Denormals =
-    Mode.FP32Denormals ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
-
-  uint32_t FP64Denormals =
-    Mode.FP64FP16Denormals ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
-
   return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
          FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
-         FP_DENORM_MODE_SP(FP32Denormals) |
-         FP_DENORM_MODE_DP(FP64Denormals);
+         FP_DENORM_MODE_SP(Mode.fpDenormModeSPValue()) |
+         FP_DENORM_MODE_DP(Mode.fpDenormModeDPValue());
 }
 
 static AsmPrinter *
 createAMDGPUAsmPrinterPass(TargetMachine &tm,
                            std::unique_ptr<MCStreamer> &&Streamer) {
   return new AMDGPUAsmPrinter(tm, std::move(Streamer));
 }
 

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

void AMDGPUDAGToDAGISel::SelectFMAD_FMA(SDNode *N) {
   unsigned Src0Mods, Src1Mods, Src2Mods;
 
   // Avoid using v_mad_mix_f32/v_fma_mix_f32 unless there is actually an operand
   // using the conversion from f16.
   bool Sel0 = SelectVOP3PMadMixModsImpl(Src0, Src0, Src0Mods);
   bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods);
   bool Sel2 = SelectVOP3PMadMixModsImpl(Src2, Src2, Src2Mods);
 
-  assert((IsFMA || !Mode.FP32Denormals) &&
+  assert((IsFMA || !Mode.allFP32Denormals()) &&
          "fmad selected with denormals enabled");
   // TODO: We can select this with f32 denormals enabled if all the sources are
   // converted from f16 (in which case fmad isn't legal).
 
   if (Sel0 || Sel1 || Sel2) {
     // For dummy operands.
     SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32);
     SDValue Ops[] = {

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
 
   // float fqneg = -fq;
   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
 
   MachineFunction &MF = DAG.getMachineFunction();
   const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
 
   // float fr = mad(fqneg, fb, fa);
-  unsigned OpCode = MFI->getMode().FP32Denormals ?
+  unsigned OpCode = MFI->getMode().allFP32Denormals() ?
                     (unsigned)AMDGPUISD::FMAD_FTZ :
                     (unsigned)ISD::FMAD;
   SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
 
   // int iq = (int)fq;
   SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
 
   // fr = fabs(fr);
if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
     return;
   }
 
   if (isTypeLegal(MVT::i64)) {
     MachineFunction &MF = DAG.getMachineFunction();
     const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
     // Compute denominator reciprocal.
-    unsigned FMAD = MFI->getMode().FP32Denormals ?
+    unsigned FMAD = MFI->getMode().allFP32Denormals() ?
                     (unsigned)AMDGPUISD::FMAD_FTZ :
                     (unsigned)ISD::FMAD;
 
     SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
     SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
     SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
       DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
       Cvt_Lo);

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

list<Predicate> Predicates = PredConcat<
                                             AssemblerPredicate>.ret,
                                  WaveSizePredicate>.ret;
 }
 
 class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
       PredicateControl;
 
 let RecomputePerFunction = 1 in {
-def FP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals">;
-def FP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals">;
-def FP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals">;
-def NoFP16Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals">;
-def NoFP32Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals">;
-def NoFP64Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals">;
+def FP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
+def FP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP32Denormals()">;
+def FP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
+def NoFP16Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
+def NoFP32Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP32Denormals()">;
+def NoFP64Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
 }
 
 def FMA : Predicate<"Subtarget->hasFMA()">;
 
 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
 
 def u16ImmTarget : AsmOperandClass {

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

bool AMDGPULegalizerInfo::legalizeFMad(
   MachineIRBuilder &B) const {
   LLT Ty = MRI.getType(MI.getOperand(0).getReg());
   assert(Ty.isScalar());
 
   MachineFunction &MF = B.getMF();
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
   // TODO: Always legal with future ftz flag.
-  if (Ty == LLT::scalar(32) && !MFI->getMode().FP32Denormals)
+  // FIXME: Do we need just output?
+  if (Ty == LLT::scalar(32) && !MFI->getMode().allFP32Denormals())
     return true;
-  if (Ty == LLT::scalar(16) && !MFI->getMode().FP64FP16Denormals)
+  if (Ty == LLT::scalar(16) && !MFI->getMode().allFP64FP16Denormals())
     return true;
 
-
   MachineIRBuilder HelperBuilder(MI);
   GISelObserverWrapper DummyObserver;
   LegalizerHelper Helper(MF, DummyObserver, HelperBuilder);
   HelperBuilder.setMBB(*MI.getParent());
   return Helper.lowerFMad(MI) == LegalizerHelper::Legalized;
 }
 
 bool AMDGPULegalizerInfo::legalizeAtomicCmpXChg(
bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(MachineInstr &MI,
   const MachineFunction &MF = B.getMF();
   bool Unsafe =
     MF.getTarget().Options.UnsafeFPMath || MI.getFlag(MachineInstr::FmArcp);
 
   if (!MF.getTarget().Options.UnsafeFPMath && ResTy == S64)
     return false;
 
   if (!Unsafe && ResTy == S32 &&
-      MF.getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals)
+      MF.getInfo<SIMachineFunctionInfo>()->getMode().allFP32Denormals())
     return false;
 
   if (auto CLHS = getConstantFPVRegVal(LHS, MRI)) {
     // 1 / x -> RCP(x)
     if (CLHS->isExactlyValue(1.0)) {
       B.buildIntrinsic(Intrinsic::amdgcn_rcp, Res, false)
         .addUse(RHS)
         .setMIFlags(Flags);

 // Enable or disable FP32 denorm mode. When 'Enable' is true, emit instructions
 // to enable denorm mode. When 'Enable' is false, disable denorm mode.
 static void toggleSPDenormMode(bool Enable,
                                MachineIRBuilder &B,
                                const GCNSubtarget &ST,
                                AMDGPU::SIModeRegisterDefaults Mode) {
   // Set SP denorm mode to this value.
   unsigned SPDenormMode =
-    Enable ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
+    Enable ? FP_DENORM_FLUSH_NONE : Mode.fpDenormModeSPValue();
 
   if (ST.hasDenormModeInst()) {
     // Preserve default FP64FP16 denorm mode while updating FP32 mode.
-    unsigned DPDenormModeDefault = Mode.FP64FP16Denormals
-                                   ? FP_DENORM_FLUSH_NONE
-                                   : FP_DENORM_FLUSH_IN_FLUSH_OUT;
+    uint32_t DPDenormModeDefault = Mode.fpDenormModeDPValue();
 
-    unsigned NewDenormModeValue = SPDenormMode | (DPDenormModeDefault << 2);
+    uint32_t NewDenormModeValue = SPDenormMode | (DPDenormModeDefault << 2);
     B.buildInstr(AMDGPU::S_DENORM_MODE)
       .addImm(NewDenormModeValue);
 
   } else {
     // Select FP32 bit field in mode register.
     unsigned SPDenormModeBitField = AMDGPU::Hwreg::ID_MODE |
                                     (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) |
                                     (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_);
bool AMDGPULegalizerInfo::legalizeFDIV32(MachineInstr &MI,
 
   auto ApproxRcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false)
     .addUse(DenominatorScaled.getReg(0))
     .setMIFlags(Flags);
   auto NegDivScale0 = B.buildFNeg(S32, DenominatorScaled, Flags);
 
   // FIXME: Doesn't correctly model the FP mode switch, and the FP operations
   // aren't modeled as reading it.
-  if (!Mode.FP32Denormals)
+  if (!Mode.allFP32Denormals())
     toggleSPDenormMode(true, B, ST, Mode);
 
   auto Fma0 = B.buildFMA(S32, NegDivScale0, ApproxRcp, One, Flags);
   auto Fma1 = B.buildFMA(S32, Fma0, ApproxRcp, ApproxRcp, Flags);
   auto Mul = B.buildFMul(S32, NumeratorScaled, Fma1, Flags);
   auto Fma2 = B.buildFMA(S32, NegDivScale0, Mul, NumeratorScaled, Flags);
   auto Fma3 = B.buildFMA(S32, Fma2, Fma1, Mul, Flags);
   auto Fma4 = B.buildFMA(S32, NegDivScale0, Fma3, NumeratorScaled, Flags);
 
-  if (!Mode.FP32Denormals)
+  if (!Mode.allFP32Denormals())
     toggleSPDenormMode(false, B, ST, Mode);
 
   auto Fmas = B.buildIntrinsic(Intrinsic::amdgcn_div_fmas, {S32}, false)
     .addUse(Fma4.getReg(0))
     .addUse(Fma1.getReg(0))
     .addUse(Fma3.getReg(0))
     .addUse(NumeratorScaled.getReg(1))
     .setMIFlags(Flags);

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

if (YamlMFI.ArgInfo &&
                              MFI->ArgInfo.WorkItemIDY, 0, 0) ||
        parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
                              AMDGPU::VGPR_32RegClass,
                              MFI->ArgInfo.WorkItemIDZ, 0, 0)))
     return true;
 
   MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
   MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
-  MFI->Mode.FP32Denormals = YamlMFI.Mode.FP32Denormals;
-  MFI->Mode.FP64FP16Denormals = YamlMFI.Mode.FP64FP16Denormals;
+  MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
+  MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
+  MFI->Mode.FP64FP16InputDenormals = YamlMFI.Mode.FP64FP16InputDenormals;
+  MFI->Mode.FP64FP16OutputDenormals = YamlMFI.Mode.FP64FP16OutputDenormals;
 
   return false;
 }

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

 // handled, so will anything other than that break?
 std::pair<const MachineOperand *, int>
 SIFoldOperands::isOMod(const MachineInstr &MI) const {
   unsigned Op = MI.getOpcode();
   switch (Op) {
   case AMDGPU::V_MUL_F32_e64:
   case AMDGPU::V_MUL_F16_e64: {
     // If output denormals are enabled, omod is ignored.
-    if ((Op == AMDGPU::V_MUL_F32_e64 && MFI->getMode().FP32Denormals) ||
-        (Op == AMDGPU::V_MUL_F16_e64 && MFI->getMode().FP64FP16Denormals))
+    if ((Op == AMDGPU::V_MUL_F32_e64 && MFI->getMode().FP32OutputDenormals) ||
+        (Op == AMDGPU::V_MUL_F16_e64 && MFI->getMode().FP64FP16OutputDenormals))
       return std::make_pair(nullptr, SIOutMods::NONE);
 
     const MachineOperand *RegOp = nullptr;
     const MachineOperand *ImmOp = nullptr;
     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
     if (Src0->isImm()) {
       ImmOp = Src0;
if (OMod == SIOutMods::NONE ||
         TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
       return std::make_pair(nullptr, SIOutMods::NONE);
 
     return std::make_pair(RegOp, OMod);
   }
   case AMDGPU::V_ADD_F32_e64:
   case AMDGPU::V_ADD_F16_e64: {
     // If output denormals are enabled, omod is ignored.
-    if ((Op == AMDGPU::V_ADD_F32_e64 && MFI->getMode().FP32Denormals) ||
-        (Op == AMDGPU::V_ADD_F16_e64 && MFI->getMode().FP64FP16Denormals))
+    if ((Op == AMDGPU::V_ADD_F32_e64 && MFI->getMode().FP32OutputDenormals) ||
+        (Op == AMDGPU::V_ADD_F16_e64 && MFI->getMode().FP64FP16OutputDenormals))
       return std::make_pair(nullptr, SIOutMods::NONE);
 
     // Look through the DAGCombiner canonicalization fmul x, 2 -> fadd x, x
     const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
     const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
 
     if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
         Src0->getSubReg() == Src1->getSubReg() &&

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 
 static cl::opt<bool> DisableLoopAlignment(
   "amdgpu-disable-loop-alignment",
   cl::desc("Do not align and prefetch loops"),
   cl::init(false));
 
 static bool hasFP32Denormals(const MachineFunction &MF) {
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
-  return Info->getMode().FP32Denormals;
+  return Info->getMode().allFP32Denormals();
 }
 
 static bool hasFP64FP16Denormals(const MachineFunction &MF) {
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
-  return Info->getMode().FP64FP16Denormals;
+  return Info->getMode().allFP64FP16Denormals();
 }
 
 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
   unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
   for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
     if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
       return AMDGPU::SGPR0 + Reg;
     }

 // There is only one special case when denormals are enabled we don't currently,
 // where this is OK to use.
 bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
                                        EVT DestVT, EVT SrcVT) const {
   return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
           (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
     DestVT.getScalarType() == MVT::f32 &&
     SrcVT.getScalarType() == MVT::f16 &&
+    // TODO: This probably only requires no input flushing?
     !hasFP32Denormals(DAG.getMachineFunction());
 }
 
 bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
   // SI has some legal vector types, but no legal vector operations. Say no
   // shuffles are legal in order to prefer scalarizing some vector operations.
   return false;
 }

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

static void mapping(IO &YamlIO, SIArgumentInfo &AI) {
     YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ);
   }
 };
 
 // Default to default mode for default calling convention.
 struct SIMode {
   bool IEEE = true;
   bool DX10Clamp = true;
-  bool FP32Denormals = true;
-  bool FP64FP16Denormals = true;
+  bool FP32InputDenormals = true;
+  bool FP32OutputDenormals = true;
+  bool FP64FP16InputDenormals = true;
+  bool FP64FP16OutputDenormals = true;
 
   SIMode() = default;
 
   SIMode(const AMDGPU::SIModeRegisterDefaults &Mode) {
     IEEE = Mode.IEEE;
     DX10Clamp = Mode.DX10Clamp;
-    FP32Denormals = Mode.FP32Denormals;
-    FP64FP16Denormals = Mode.FP64FP16Denormals;
+    FP32InputDenormals = Mode.FP32InputDenormals;
+    FP32OutputDenormals = Mode.FP32OutputDenormals;
+    FP64FP16InputDenormals = Mode.FP64FP16InputDenormals;
+    FP64FP16OutputDenormals = Mode.FP64FP16OutputDenormals;
   }
 
   bool operator ==(const SIMode Other) const {
     return IEEE == Other.IEEE &&
            DX10Clamp == Other.DX10Clamp &&
-           FP32Denormals == Other.FP32Denormals &&
-           FP64FP16Denormals == Other.FP64FP16Denormals;
+           FP32InputDenormals == Other.FP32InputDenormals &&
+           FP32OutputDenormals == Other.FP32OutputDenormals &&
+           FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
+           FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
   }
 };
 
 template <> struct MappingTraits<SIMode> {
   static void mapping(IO &YamlIO, SIMode &Mode) {
     YamlIO.mapOptional("ieee", Mode.IEEE, true);
     YamlIO.mapOptional("dx10-clamp", Mode.DX10Clamp, true);
-    YamlIO.mapOptional("fp32-denormals", Mode.FP32Denormals, true);
-    YamlIO.mapOptional("fp64-fp16-denormals", Mode.FP64FP16Denormals, true);
+    YamlIO.mapOptional("fp32-input-denormals", Mode.FP32InputDenormals, true);
+    YamlIO.mapOptional("fp32-output-denormals", Mode.FP32OutputDenormals, true);
+    YamlIO.mapOptional("fp64-fp16-input-denormals", Mode.FP64FP16InputDenormals, true);
+    YamlIO.mapOptional("fp64-fp16-output-denormals", Mode.FP64FP16OutputDenormals, true);
   }
 };
 
 struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
   uint64_t ExplicitKernArgSize = 0;
   unsigned MaxKernArgAlign = 0;
   unsigned LDSSize = 0;
   bool IsEntryFunction = false;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

struct SIModeRegisterDefaults {
   bool IEEE : 1;
 
   /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
   /// clamp NaN to zero; otherwise, pass NaN through.
   bool DX10Clamp : 1;
 
   /// If this is set, neither input or output denormals are flushed for most f32
   /// instructions.
-  ///
-  /// TODO: Split into separate input and output fields if necessary like the
-  /// control bits really provide?
-  bool FP32Denormals : 1;
+  bool FP32InputDenormals : 1;
+  bool FP32OutputDenormals : 1;
 
   /// If this is set, neither input or output denormals are flushed for both f64
   /// and f16/v2f16 instructions.
-  bool FP64FP16Denormals : 1;
+  bool FP64FP16InputDenormals : 1;
+  bool FP64FP16OutputDenormals : 1;
 
   SIModeRegisterDefaults() :
     IEEE(true),
     DX10Clamp(true),
-    FP32Denormals(true),
-    FP64FP16Denormals(true) {}
+    FP32InputDenormals(true),
+    FP32OutputDenormals(true),
+    FP64FP16InputDenormals(true),
+    FP64FP16OutputDenormals(true) {}
 
   // FIXME: Should not depend on the subtarget
   SIModeRegisterDefaults(const Function &F, const GCNSubtarget &ST);
 
   static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
     const bool IsCompute = AMDGPU::isCompute(CC);
 
     SIModeRegisterDefaults Mode;
     Mode.DX10Clamp = true;
     Mode.IEEE = IsCompute;
-    Mode.FP32Denormals = false; // FIXME: Should be on by default.
-    Mode.FP64FP16Denormals = true;
+    Mode.FP32InputDenormals = false; // FIXME: Should be on by default.
+    Mode.FP32OutputDenormals = false; // FIXME: Should be on by default.
+    Mode.FP64FP16InputDenormals = true;
+    Mode.FP64FP16OutputDenormals = true;
     return Mode;
   }
 
   bool operator ==(const SIModeRegisterDefaults Other) const {
     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
-           FP32Denormals == Other.FP32Denormals &&
-           FP64FP16Denormals == Other.FP64FP16Denormals;
+           FP32InputDenormals == Other.FP32InputDenormals &&
+           FP32OutputDenormals == Other.FP32OutputDenormals &&
+           FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
+           FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
+  }
+
+  bool allFP32Denormals() const {
+    return FP32InputDenormals && FP32OutputDenormals;
+  }
+
+  bool allFP64FP16Denormals() const {
+    return FP64FP16InputDenormals && FP64FP16OutputDenormals;
+  }
+
+  /// Get the encoding value for the FP_DENORM bits of the mode register for the
+  /// FP32 denormal mode.
+  uint32_t fpDenormModeSPValue() const {
+    if (FP32InputDenormals && FP32OutputDenormals)
+      return FP_DENORM_FLUSH_NONE;
+    if (FP32InputDenormals)
+      return FP_DENORM_FLUSH_OUT;
+    if (FP32OutputDenormals)
+      return FP_DENORM_FLUSH_IN;
+    return FP_DENORM_FLUSH_IN_FLUSH_OUT;
+  }
+
+  /// Get the encoding value for the FP_DENORM bits of the mode register for the
+  /// FP64/FP16 denormal mode.
+  uint32_t fpDenormModeDPValue() const {
+    if (FP64FP16InputDenormals && FP64FP16OutputDenormals)
+      return FP_DENORM_FLUSH_NONE;
+    if (FP64FP16InputDenormals)
+      return FP_DENORM_FLUSH_OUT;
+    if (FP64FP16OutputDenormals)
+      return FP_DENORM_FLUSH_IN;
+    return FP_DENORM_FLUSH_IN_FLUSH_OUT;
   }
 
   /// Returns true if a flag is compatible if it's enabled in the callee, but
   /// disabled in the caller.
   static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
     return CallerMode == CalleeMode || (CallerMode && !CalleeMode);
   }
 
   // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
   // be able to override.
   bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
     if (DX10Clamp != CalleeMode.DX10Clamp)
       return false;
     if (IEEE != CalleeMode.IEEE)
       return false;
 
     // Allow inlining denormals enabled into denormals flushed functions.
-    return oneWayCompatible(FP64FP16Denormals, CalleeMode.FP64FP16Denormals) &&
-           oneWayCompatible(FP32Denormals, CalleeMode.FP32Denormals);
+    return oneWayCompatible(FP64FP16InputDenormals, CalleeMode.FP64FP16InputDenormals) &&
+           oneWayCompatible(FP64FP16OutputDenormals, CalleeMode.FP64FP16OutputDenormals) &&
+           oneWayCompatible(FP32InputDenormals, CalleeMode.FP32InputDenormals) &&
+           oneWayCompatible(FP32OutputDenormals, CalleeMode.FP32OutputDenormals);
   }
 };
 
 } // end namespace AMDGPU
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

SIModeRegisterDefaults::SIModeRegisterDefaults(const Function &F,
   if (!IEEEAttr.empty())
     IEEE = IEEEAttr == "true";
 
   StringRef DX10ClampAttr
     = F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
   if (!DX10ClampAttr.empty())
     DX10Clamp = DX10ClampAttr == "true";
 
-  FP32Denormals = ST.hasFP32Denormals(F);
-  FP64FP16Denormals = ST.hasFP64FP16Denormals(F);
+  // FIXME: Split this when denormal-fp-math is used
+  FP32InputDenormals = ST.hasFP32Denormals(F);
+  FP32OutputDenormals = FP32InputDenormals;
+  FP64FP16InputDenormals = ST.hasFP64FP16Denormals(F);
+  FP64FP16OutputDenormals = FP64FP16InputDenormals;
 }
 
 namespace {
 
 struct SourceOfDivergence {
   unsigned Intr;
 };
 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
 
 ---
 
 name:            fcanonicalize_f16_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_f16_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FCANONICALIZE %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 
 name:            fcanonicalize_f16_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_f16_flush
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, 15360, 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FCANONICALIZE %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 
 name:            fcanonicalize_f32_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX9-LABEL: name: fcanonicalize_f32_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FCANONICALIZE %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 name:            fcanonicalize_f32_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX9-LABEL: name: fcanonicalize_f32_flush
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FCANONICALIZE %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 name:            fcanonicalize_v2f16_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX9-LABEL: name: fcanonicalize_v2f16_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
     ; GFX9: [[FCANONICALIZE:%[0-9]+]]:vgpr(<2 x s16>) = G_FCANONICALIZE [[COPY]]
     ; GFX9: S_ENDPGM 0, implicit [[FCANONICALIZE]](<2 x s16>)
     %0:vgpr(<2 x s16>) = COPY $vgpr0
     %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 name:            fcanonicalize_v2f16_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GFX9-LABEL: name: fcanonicalize_v2f16_flush
     ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
     ; GFX9: [[FCANONICALIZE:%[0-9]+]]:vgpr(<2 x s16>) = G_FCANONICALIZE [[COPY]]
     ; GFX9: S_ENDPGM 0, implicit [[FCANONICALIZE]](<2 x s16>)
     %0:vgpr(<2 x s16>) = COPY $vgpr0
     %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 name:            fcanonicalize_f64_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; GFX9-LABEL: name: fcanonicalize_f64_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
     ; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]]
     %0:vgpr(s64) = COPY $vgpr0_vgpr1
     %1:vgpr(s64) = G_FCANONICALIZE %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 name:            fcanonicalize_f64_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; GFX9-LABEL: name: fcanonicalize_f64_flush
     ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
     ; GFX9: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, 4607182418800017408, 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MUL_F64_]]
     %0:vgpr(s64) = COPY $vgpr0_vgpr1
     %1:vgpr(s64) = G_FCANONICALIZE %0
     S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 name:            fcanonicalize_fabs_f32_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_fabs_f32_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FABS %0
     %2:vgpr(s32) = G_FCANONICALIZE %1
     S_ENDPGM 0, implicit %2
 ...
 
 
 ---
 
 name:            fcanonicalize_fabs_f32_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_fabs_f32_flush
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FABS %0
     %2:vgpr(s32) = G_FCANONICALIZE %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 
 name:            fcanonicalize_fneg_f32_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_fneg_f32_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FNEG %0
     %2:vgpr(s32) = G_FCANONICALIZE %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 
 name:            fcanonicalize_fneg_f32_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_fneg_f32_flush
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FNEG %0
     %2:vgpr(s32) = G_FCANONICALIZE %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 
 name:            fcanonicalize_fneg_fabs_f32_denorm
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
     ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
     ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FNEG %0
     %2:vgpr(s32) = G_FABS %1
     %3:vgpr(s32) = G_FCANONICALIZE %2
     S_ENDPGM 0, implicit %3
 ...
 
 ---
 
 name:            fcanonicalize_fneg_fabs_f32_flush
 legalized:       true
 regBankSelected: true
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0
     ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_flush
     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
     ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
     ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
     ; GFX9: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
     ; GFX9: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s32) = G_FNEG %0
     %2:vgpr(s32) = G_FABS %1
     %3:vgpr(s32) = G_FCANONICALIZE %2
     S_ENDPGM 0, implicit %3
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer  %s -o - | FileCheck -check-prefix=SI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer  %s -o - | FileCheck -check-prefix=VI  %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -enable-unsafe-fp-math -o - %s | FileCheck -check-prefix=GFX9-UNSAFE %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: test_fdiv_s16
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
-    fp64-fp16-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; SI-LABEL: name: test_fdiv_s16
     ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %5:_(s32) = G_ANYEXT %4
     $vgpr0 = COPY %5
 ...
 
 ---
 name: test_fdiv_s32_denorms_on
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
-    fp64-fp16-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; SI-LABEL: name: test_fdiv_s32_denorms_on
     ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %2:_(s32) = G_FDIV %0, %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: test_fdiv_s32_denorms_off
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-    fp64-fp16-denormals: true
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; SI-LABEL: name: test_fdiv_s32_denorms_off
     ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %2:_(s32) = G_FDIV %0, %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: test_fdiv_s32_denorms_off_arcp
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-    fp64-fp16-denormals: true
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
     ; SI-LABEL: name: test_fdiv_s32_denorms_off_arcp
     ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %2:_(s32) = arcp G_FDIV %0, %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: test_fdiv_s64
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-    fp64-fp16-denormals: true
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     ; SI-LABEL: name: test_fdiv_s64
     ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
bb.0:
     %2:_(s64) = G_FDIV %0, %1
     $vgpr0_vgpr1 = COPY %2
 ...
 
 ---
 name: test_fdiv_v2s32
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-    fp64-fp16-denormals: true
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 
     ; SI-LABEL: name: test_fdiv_v2s32
     ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
bb.0:
     %2:_(s32) = G_FDIV %0, %1
     $vgpr0 = COPY %2
 ...
 
 ---
 name: test_fdiv_s64_constant_one_rcp
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-    fp64-fp16-denormals: true
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-output-denormals: true
+    fp64-fp16-input-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; SI-LABEL: name: test_fdiv_s64_constant_one_rcp
     ; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
     ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
bb.0:
     %2:_(s64) = G_FDIV %0, %1
     $vgpr0_vgpr1 = COPY %2
 ...
 
 ---
 name: test_fdiv_s64_constant_negative_one_rcp
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
-    fp64-fp16-denormals: true
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; SI-LABEL: name: test_fdiv_s64_constant_negative_one_rcp
     ; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double -1.000000e+00
     ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: test_fmad_s16_flush
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s16_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %7:_(s32) = G_ANYEXT %6
     $vgpr0 = COPY %7
 ...
 
 ---
 name: test_fmad_v2s16_flush
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_v2s16_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
bb.0:
     %3:_(<2 x s16>) = G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_v4s16_flush
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
 
     ; GFX6-LABEL: name: test_fmad_v4s16_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
     ; GFX6: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
bb.0:
     $vgpr0_vgpr1 = COPY %3
 ...
 
 
 ---
 name: test_fmad_s16_denorm
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s16_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %7:_(s32) = G_ANYEXT %6
     $vgpr0 = COPY %7
 ...
 
 ---
 name: test_fmad_s16_denorm_flags
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s16_denorm_flags
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %7:_(s32) = G_ANYEXT %6
     $vgpr0 = COPY %7
 ...
 
 ---
 name: test_fmad_v2s16_denorm
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_v2s16_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
bb.0:
     %3:_(<2 x s16>) = G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_v2s16_denorm_flags
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_v2s16_denorm_flags
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
bb.0:
     %3:_(<2 x s16>) = nnan G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_v4s16_denorm
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
 
     ; GFX6-LABEL: name: test_fmad_v4s16_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
     ; GFX6: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
bb.0:
     $vgpr0_vgpr1 = COPY %3
 ...
 
 
 ---
 name: test_fmad_v4s16_denorm_flags
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
 
     ; GFX6-LABEL: name: test_fmad_v4s16_denorm_flags
     ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
     ; GFX6: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX6 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX7 %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX10 %s
 
 ---
 name: test_fmad_s32_flush
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s32_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %3:_(s32) = G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_s32_flags_flush
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s32_flags_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %3:_(s32) = nnan G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_v2s32_flush
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
 
     ; GFX6-LABEL: name: test_fmad_v2s32_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
bb.0:
     %3:_(<2 x s32>) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1 = COPY %3
 ...
 
 ---
 name: test_fmad_v3s32_flush
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
 
     ; GFX6-LABEL: name: test_fmad_v3s32_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; GFX6: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
bb.0:
     %3:_(<3 x s32>) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1_vgpr2 = COPY %3
 ...
 
 ---
 name: test_fmad_v4s32_flush
 machineFunctionInfo:
   mode:
-    fp32-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 
     ; GFX6-LABEL: name: test_fmad_v4s32_flush
     ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; GFX6: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
bb.0:
     %3:_(<4 x s32>) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
 ...
 
 ---
 name: test_fmad_s32_denorm
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s32_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %3:_(s32) = G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_s32_flags_denorm
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0, $vgpr1, $vgpr2
 
     ; GFX6-LABEL: name: test_fmad_s32_flags_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
bb.0:
     %3:_(s32) = nnan G_FMAD %0, %1, %2
     $vgpr0 = COPY %3
 ...
 
 ---
 name: test_fmad_v2s32_denorm
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
 
     ; GFX6-LABEL: name: test_fmad_v2s32_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
     ; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
bb.0:
     %3:_(<2 x s32>) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1 = COPY %3
 ...
 
 ---
 name: test_fmad_v3s32_denorm
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4_vgpr5, $vgpr6_vgpr7_vgpr8
 
     ; GFX6-LABEL: name: test_fmad_v3s32_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
     ; GFX6: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
bb.0:
     %3:_(<3 x s32>) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1_vgpr2 = COPY %3
 ...
 
 ---
 name: test_fmad_v4s32_denorm
 machineFunctionInfo:
   mode:
-    fp32-denormals: true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 
     ; GFX6-LABEL: name: test_fmad_v4s32_denorm
     ; GFX6: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; GFX6: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
 name: test_fmad_s64_flush
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-output-denormals: false
+    fp64-fp16-input-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3,  $vgpr4_vgpr5
 
     ; CHECK-LABEL: name: test_fmad_s64_flush
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
     ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
     ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
     ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
     ; CHECK: $vgpr0_vgpr1 = COPY [[FADD]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s64) = COPY $vgpr2_vgpr3
     %2:_(s64) = COPY $vgpr4_vgpr5
     %3:_(s64) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1 = COPY %3
 ...
 
 ---
 name: test_fmad_v2s64_flush
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 
     ; CHECK-LABEL: name: test_fmad_v2s64_flush
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7
bb.0:
     %3:_(<2 x s64>) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
 ...
 
 ---
 name: test_fmad_s64_denorm
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3,  $vgpr4_vgpr5
 
     ; CHECK-LABEL: name: test_fmad_s64_denorm
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
     ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr4_vgpr5
     ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY1]]
     ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[COPY2]]
     ; CHECK: $vgpr0_vgpr1 = COPY [[FADD]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s64) = COPY $vgpr2_vgpr3
     %2:_(s64) = COPY $vgpr4_vgpr5
     %3:_(s64) = G_FMAD %0, %1, %2
     $vgpr0_vgpr1 = COPY %3
 ...
 
 ---
 name: test_fmad_v2s64_denorm
 machineFunctionInfo:
   mode:
-    fp64-fp16-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
 
     ; CHECK-LABEL: name: test_fmad_v2s64_denorm
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr4_vgpr5_vgpr6_vgpr7

llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir

 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands  %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
 
 # FIXME: Is it OK to fold omod for this?
 # GCN-LABEL: name: omod_inst_flag_nsz_src
 # GCN: %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
 # GCN-NEXT: %1:vgpr_32 = V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
 # GCN-NEXT: S_ENDPGM 0, implicit %1
 name: omod_inst_flag_nsz_src
 tracksRegLiveness: true
 machineFunctionInfo:
   mode:
     ieee: false
-    fp32-denormals: false
+    fp32-output-denormals: false
 
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
   %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
   %1:vgpr_32 = V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
   S_ENDPGM 0, implicit %1
 
 ...
 ---
 
 # GCN-LABEL: name: omod_inst_flag_nsz_result
 # GCN: %0:vgpr_32 = V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $exec
 # GCN-NEXT: S_ENDPGM 0, implicit %0
 
 name: omod_inst_flag_nsz_result
 tracksRegLiveness: true
 machineFunctionInfo:
   mode:
     ieee: false
-    fp32-denormals: false
+    fp32-output-denormals: false
 
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
   %0:vgpr_32 = V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
   %1:vgpr_32 = nsz V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
   S_ENDPGM 0, implicit %1
 ...
 
 ---
 
 # GCN-LABEL: name: omod_inst_flag_nsz_both
 # GCN: %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $exec
 # GCN-NEXT: S_ENDPGM 0, implicit %0
 
 name: omod_inst_flag_nsz_both
 tracksRegLiveness: true
 machineFunctionInfo:
   mode:
     ieee: false
-    fp32-denormals: false
+    fp32-output-denormals: false
 
 body:             |
   bb.0:
     liveins: $vgpr0, $vgpr1
 
   %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
   %1:vgpr_32 = nsz V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
   S_ENDPGM 0, implicit %1
 ...

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir

 # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 # FULL-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
 # FULL-NEXT: workGroupIDX: { reg: '$sgpr6' }
 # FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
 # FULL-NEXT: workItemIDX: { reg: '$vgpr0' }
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
-# FULL-NEXT: fp32-denormals: true
-# FULL-NEXT: fp64-fp16-denormals: true
+# FULL-NEXT: fp32-input-denormals: true
+# FULL-NEXT: fp32-output-denormals: true
+# FULL-NEXT: fp64-fp16-input-denormals: true
+# FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0
 # FULL-NEXT: body:
 
 # SIMPLE: machineFunctionInfo:
 # SIMPLE-NEXT: explicitKernArgSize: 128
 # SIMPLE-NEXT: maxKernArgAlign: 64
 # SIMPLE-NEXT: ldsSize: 2048
 # SIMPLE-NEXT: isEntryFunction: true

 # FULL-NEXT: frameOffsetReg:  '$fp_reg'
 # FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'
 # FULL-NEXT: argumentInfo:
 # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 # FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
-# FULL-NEXT: fp32-denormals: true
-# FULL-NEXT: fp64-fp16-denormals: true
+# FULL-NEXT: fp32-input-denormals: true
+# FULL-NEXT: fp32-output-denormals: true
+# FULL-NEXT: fp64-fp16-input-denormals: true
+# FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0
 # FULL-NEXT: body:
 
 # SIMPLE: machineFunctionInfo:
 # SIMPLE-NEXT: maxKernArgAlign: 1
 # SIMPLE-NEXT: argumentInfo:
 # SIMPLE-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 # SIMPLE-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }

 # FULL-NEXT: frameOffsetReg:  '$fp_reg'
 # FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'
 # FULL-NEXT: argumentInfo:
 # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 # FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
-# FULL-NEXT: fp32-denormals: true
-# FULL-NEXT: fp64-fp16-denormals: true
+# FULL-NEXT: fp32-input-denormals: true
+# FULL-NEXT: fp32-output-denormals: true
+# FULL-NEXT: fp64-fp16-input-denormals: true
+# FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0
 # FULL-NEXT: body:
 
 # SIMPLE: machineFunctionInfo:
 # SIMPLE-NEXT: maxKernArgAlign: 1
 # SIMPLE-NEXT: argumentInfo:
 # SIMPLE-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 # SIMPLE-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }

 # FULL-NEXT: frameOffsetReg:  '$fp_reg'
 # FULL-NEXT: stackPtrOffsetReg:  '$sp_reg'
 # FULL-NEXT: argumentInfo:
 # FULL-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 # FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
-# FULL-NEXT: fp32-denormals: true
-# FULL-NEXT: fp64-fp16-denormals: true
+# FULL-NEXT: fp32-input-denormals: true
+# FULL-NEXT: fp32-output-denormals: true
+# FULL-NEXT: fp64-fp16-input-denormals: true
+# FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0
 # FULL-NEXT: body:
 
 # SIMPLE: machineFunctionInfo:
 # SIMPLE-NEXT: maxKernArgAlign: 1
 # SIMPLE-NEXT: isEntryFunction: true
 # SIMPLE-NEXT: argumentInfo:
 # SIMPLE-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }

 
 ...
 
 ---
 # ALL-LABEL: name: parse_mode
 # ALL: mode:
 # ALL-NEXT: ieee: false
 # ALL-NEXT: dx10-clamp: false
-# ALL-NEXT: fp32-denormals: false
-# ALL-NEXT: fp64-fp16-denormals: false
+# ALL-NEXT: fp32-input-denormals: false
+# ALL-NEXT: fp32-output-denormals: false
+# ALL-NEXT: fp64-fp16-input-denormals: false
+# ALL-NEXT: fp64-fp16-output-denormals: false
 
 name: parse_mode
 machineFunctionInfo:
   mode:
     ieee: false
     dx10-clamp: false
-    fp32-denormals: false
-    fp64-fp16-denormals: false
+    fp32-input-denormals: false
+    fp32-output-denormals: false
+    fp64-fp16-input-denormals: false
+    fp64-fp16-output-denormals: false
 
 body:             |
   bb.0:
     S_ENDPGM 0
 
 ...

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll

 ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 ; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
 ; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
 ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: true
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0
 ; CHECK-NEXT: body:
 define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
   %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
   store float 0.0, float addrspace(3)* %gep, align 4
   ret void
 }
 

 ; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
 ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
 ; CHECK-NEXT: argumentInfo:
 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
 ; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: false
 ; CHECK-NEXT: dx10-clamp: true
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0
 ; CHECK-NEXT: body:
 define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: function
 ; CHECK: machineFunctionInfo:

 ; CHECK-NEXT: frameOffsetReg: '$sgpr34'
 ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
 ; CHECK-NEXT: argumentInfo:
 ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: true
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0
 ; CHECK-NEXT: body:
 define void @function() {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: function_nsz
 ; CHECK: machineFunctionInfo:

 ; CHECK-NEXT: frameOffsetReg: '$sgpr34'
 ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
 ; CHECK-NEXT: argumentInfo:
 ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: true
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0
 ; CHECK-NEXT: body:
 define void @function_nsz() #0 {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: function_dx10_clamp_off
 ; CHECK: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: false
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 define void @function_dx10_clamp_off() #1 {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: function_ieee_off
 ; CHECK: mode:
 ; CHECK-NEXT: ieee: false
 ; CHECK-NEXT: dx10-clamp: true
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 define void @function_ieee_off() #2 {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off
 ; CHECK: mode:
 ; CHECK-NEXT: ieee: false
 ; CHECK-NEXT: dx10-clamp: false
-; CHECK-NEXT: fp32-denormals: false
-; CHECK-NEXT: fp64-fp16-denormals: true
+; CHECK-NEXT: fp32-input-denormals: false
+; CHECK-NEXT: fp32-output-denormals: false
+; CHECK-NEXT: fp64-fp16-input-denormals: true
+; CHECK-NEXT: fp64-fp16-output-denormals: true
 define void @function_ieee_off_dx10_clamp_off() #3 {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: high_address_bits
 ; CHECK: machineFunctionInfo:
 ; CHECK: highBitsOf32BitAddress: 4294934528
 define amdgpu_ps void @high_address_bits() #4 {
   ret void
 }
 
 attributes #0 = { "no-signed-zeros-fp-math" = "true" }
 attributes #1 = { "amdgpu-dx10-clamp" = "false" }
 attributes #2 = { "amdgpu-ieee" = "false" }
 attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
 attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }