[ARM] Generate CMSE instructions from CMSE intrinsics

[chill]

Summary

This patch adds instruction selection patterns for the TT, TTT, TTA, and TTAT
instructions and tests for llvm.arm.cmse.tt, llvm.arm.cmse.ttt,
llvm.arm.cmse.tta, and llvm.arm.cmse.ttat intrinsics (added in a previous
patch).

Patch by Javed Absar.

[chill]

In D62394#1672551, @sigvartmh wrote:

Maybe I'm doing something wrong tried to apply these patches but when trying to build code which uses cmse I get

Cannot select: intrinsic %llvm.arm.cmse.tt
fatal error: error in backend: Cannot select: intrinsic %llvm.arm.cmse.tt
clang-10: error: clang frontend command failed with exit code 70 (use -v to see invocation)

@sigvartmh FYI, this patch enables selection of the LLVM CMSE intrinsics.

[dmgreen]

LGTM, with a few nits about formatting.

llvm/lib/Target/ARM/ARMInstrThumb2.td

4554

The Requires might be better on the next line.

llvm/test/CodeGen/ARM/intrinsics-cmse.ll

7

Remove the #0

63

Remove this line.

64

Remove the #1

[snidertm]

Was the "error in backend" issue mentioned in the comment above resolved?

llvm/lib/Target/ARM/ARMInstrThumb2.td

4554

Agree.

llvm/test/CodeGen/ARM/intrinsics-cmse.ll

2

Should we also add a RUN with -mcpu=cortex-m33?

[dmgreen]

llvm/test/CodeGen/ARM/intrinsics-cmse.ll

2

Oh, I hadn't noticed that. Good point

It may be better to also not explicitly use a cpu. It likely doesn't matter too much for this test, but for some of the other tests with more code using the architecture only will produce less scheduling artifacts. (I guess you could argue that both should be tested too, but that can be quite verbose).

[sigvartmh]

Awesome I'll test it out with my use case and report back if it works :) and thank you so much for your work.

[dmgreen]

Yep. Still LGTM.

I have just added a lot of little formatting suggestions. You are free to ignore any or all of them if you disagree. Whatever you think is best. No need for a re-review.

Oh, and @sigvartmh, I believe this is something like step 4 out of 8 or so. It will not yet do the register clearing that you would expect from a CMSE implementation, for example. That will be the interesting part.

llvm/lib/Target/ARM/ARMInstrThumb2.td

4533

I would make it look something like this, which I think is pretty standard for the arm backend. Maybe something like:

def t2TT : T2TT<0b00, "tt",
                [(set rGPR:$Rt, (int_arm_cmse_tt   GPRnopc:$Rn))]>,
           Requires<[IsThumb,Has8MSecExt]>;

llvm/test/CodeGen/ARM/intrinsics-cmse.ll

4

I don't think you actually need a datalayout for llc tests, so long as a triple is given.

6

These can be removed.

7

dso_local and local_unnamed_addr can be removed.

12

I would move this to just below the function definition, to place them where the update_llc_test_checks lines would go.

For something like this, is might make sense to use the script just to be sure about registers and whatnot.

[sigvartmh]

@dmgreen That's fine by me. I do understand that this can take some time to add everything which is needed. As always thank you so much for working on this :)

Question: Is this sufficient to generate code which sets the processor into non-secure handler/thread mode? I'm fine with not having everything clean up all the registeres etc. I'm just going to use it for testing purposes at the moment to prepare a build system to handle llvm as a back-end for ARMv8-m.

[chill]

In D70407#1754833, @sigvartmh wrote:

Question: Is this sufficient to generate code which sets the processor into non-secure handler/thread mode? I'm fine with not having everything clean up all the registeres etc. I'm just going to use it for testing purposes at the moment to prepare a build system to handle llvm as a back-end for ARMv8-m.

No, this is not enough. In the incoming patches, the only mode-change relevant things would be CMSE entry functions returning via BXNS, and calling
non-secure functions via BLXNS, other than that, I would think setting the execution mode is out of the scope of the compiler.

The assembly support should be compete already, though.

[chill]

Will commit next week, since we're on the move and might not be able to promptly react to breakage.

llvm/lib/Target/ARM/ARMInstrThumb2.td

def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>,
   let Unpredictable{2-0} = 0b111;
 }
 
 //===----------------------------------------------------------------------===//
 // ARMv8-M Security Extensions instructions
 //
 
 let hasSideEffects = 1 in
 def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>,
            Requires<[Has8MSecExt]> {
   let Inst = 0xe97fe97f;
 }
 
 class T2TT<bits<2> at, string asm, list<dag> pattern>
   : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn",
         pattern> {
   bits<4> Rn;
   bits<4> Rt;
 
   let Inst{31-20} = 0b111010000100;
   let Inst{19-16} = Rn;
   let Inst{15-12} = 0b1111;
   let Inst{11-8} = Rt;
   let Inst{7-6} = at;
   let Inst{5-0} = 0b000000;
 
   let Unpredictable{5-0} = 0b111111;
 }
 
-def t2TT   : T2TT<0b00, "tt",   []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTT  : T2TT<0b01, "ttt",  []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTA  : T2TT<0b10, "tta",  []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TT   : T2TT<0b00, "tt",   [(set rGPR:$Rt, (int_arm_cmse_tt   GPRnopc:$Rn))]>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TTT  : T2TT<0b01, "ttt",  [(set rGPR:$Rt, (int_arm_cmse_ttt  GPRnopc:$Rn))]>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TTA  : T2TT<0b10, "tta",  [(set rGPR:$Rt, (int_arm_cmse_tta  GPRnopc:$Rn))]>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TTAT : T2TT<0b11, "ttat", [(set rGPR:$Rt, (int_arm_cmse_ttat GPRnopc:$Rn))]>, Requires<[IsThumb,Has8MSecExt]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //
 
 // SXT/UXT with no rotate
 let AddedComplexity = 16 in {
 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,

llvm/test/CodeGen/ARM/intrinsics-cmse.ll

+; RUN: llc < %s -mtriple=thumbv8m.base -mcpu=cortex-m23 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbebv8m.base -mcpu=cortex-m23 | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv8-arm-none-eabi"
+
+define i32 @check_tt(i8* %p) #0 {
+entry:
+; CHECK: check_tt:
+  %p.addr = alloca i8*, align 4
+  %tmp = alloca i32, align 4
+  store i8* %p, i8** %p.addr, align 4
+  %0 = load i8*, i8** %p.addr, align 4
+  %1 = call i32 @llvm.arm.cmse.tt(i8* %0)
+; CHECK: tt r{{[0-9]+}}, r{{[0-9]+}}
+  store i32 %1, i32* %tmp, align 4
+  %2 = load i32, i32* %tmp, align 4
+  ret i32 %2
+}
+
+define i32 @check_ttt(i8* %p) #0 {
+entry:
+; CHECK: check_ttt:
+  %p.addr = alloca i8*, align 4
+  %tmp = alloca i32, align 4
+  store i8* %p, i8** %p.addr, align 4
+  %0 = load i8*, i8** %p.addr, align 4
+  %1 = call i32 @llvm.arm.cmse.ttt(i8* %0)
+; CHECK: ttt r{{[0-9]+}}, r{{[0-9]+}}
+  store i32 %1, i32* %tmp, align 4
+  %2 = load i32, i32* %tmp, align 4
+  ret i32 %2
+}
+
+define i32 @check_tta(i8* %p) #0 {
+entry:
+; CHECK: check_tta:
+  %p.addr = alloca i8*, align 4
+  %tmp = alloca i32, align 4
+  store i8* %p, i8** %p.addr, align 4
+  %0 = load i8*, i8** %p.addr, align 4
+  %1 = call i32 @llvm.arm.cmse.tta(i8* %0)
+; CHECK: tta r{{[0-9]+}}, r{{[0-9]+}}
+  store i32 %1, i32* %tmp, align 4
+  %2 = load i32, i32* %tmp, align 4
+  ret i32 %2
+}
+
+define i32 @check_ttat(i8* %p) #0 {
+entry:
+; CHECK: check_ttat:
+  %p.addr = alloca i8*, align 4
+  %tmp = alloca i32, align 4
+  store i8* %p, i8** %p.addr, align 4
+  %0 = load i8*, i8** %p.addr, align 4
+  %1 = call i32 @llvm.arm.cmse.ttat(i8* %0)
+; CHECK: ttat r{{[0-9]+}}, r{{[0-9]+}}
+  store i32 %1, i32* %tmp, align 4
+  %2 = load i32, i32* %tmp, align 4
+  ret i32 %2
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.arm.cmse.tt(i8*) #1
+declare i32 @llvm.arm.cmse.ttt(i8*) #1
+declare i32 @llvm.arm.cmse.tta(i8*) #1
+declare i32 @llvm.arm.cmse.ttat(i8*) #1