[MIPS GlobalISel] Select andi, ori and xori

[Petar.Avramovic]

Summary

Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates.
Change immZExt16 with imm32ZExt16 for andi, ori and xori.
This keeps same behavior for SDAG and allows for GlobalISel selectImpl
to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi,
respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero
extending 16 low bits of imm is equal to imm.
Large number of test changes comes from zero extending of small types
which is transformed into 'and' with bitmask in legalizer.

[atanasyan]

LGTM

llvm/lib/Target/Mips/MipsInstrInfo.td

 // immediate are caught.
 // e.g. addiu, sltiu
 def immZExt16  : PatLeaf<(imm), [{
   if (N->getValueType(0) == MVT::i32)
     return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
   else
     return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 }], LO16>;
+def imm32ZExt16  : IntImmLeaf<i32, [{
+  return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
+}]>;
 
 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
 def immSExt32Low16Zero : PatLeaf<(imm), [{
   int64_t Val = N->getSExtValue();
   return isInt<32>(Val) && !(Val & 0xffff);
 }]>;
 
 // Zero-extended 32-bit unsigned int with lower 16-bit cleared.

 
 /// Arithmetic Instructions (ALU Immediate)
 let AdditionalPredicates = [NotInMicroMips] in {
   def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
                                              II_ADDIU, imm32SExt16, add>,
               ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1;
 
   def ANDi : MMRel, StdMMR6Rel,
-             ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
+             ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, imm32ZExt16, and>,
              ADDI_FM<0xc>, ISA_MIPS1;
   def ORi  : MMRel, StdMMR6Rel,
-             ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
+             ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, imm32ZExt16, or>,
              ADDI_FM<0xd>, ISA_MIPS1;
   def XORi : MMRel, StdMMR6Rel,
-             ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
+             ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, imm32ZExt16, xor>,
              ADDI_FM<0xe>, ISA_MIPS1;
   def ADDi  : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>,
               ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6;
   def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
               SLTI_FM<0xa>, ISA_MIPS1;
   def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
               SLTI_FM<0xb>, ISA_MIPS1;
 

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
   define void @and_i32() {entry: ret void}
+  define void @and_imm() {entry: ret void}
+  define void @and_not_imm32ZExt16() {entry: ret void}
   define void @or_i32() {entry: ret void}
+  define void @or_imm() {entry: ret void}
+  define void @or_not_imm32ZExt16() {entry: ret void}
   define void @xor_i32() {entry: ret void}
+  define void @xor_imm() {entry: ret void}
+  define void @xor_not_imm32ZExt16() {entry: ret void}
   define void @shl(i32) {entry: ret void}
   define void @ashr(i32) {entry: ret void}
   define void @lshr(i32) {entry: ret void}
   define void @shlv(i32, i32) {entry: ret void}
   define void @ashrv(i32, i32) {entry: ret void}
   define void @lshrv(i32, i32) {entry: ret void}
 
 ...
bb.1.entry:
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = G_AND %1, %0
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
 ...
 ---
+name:            and_imm
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: and_imm
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 255
+    ; MIPS32: $v0 = COPY [[ANDi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 255
+    %2:gprb(s32) = G_AND %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            and_not_imm32ZExt16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: and_not_imm32ZExt16
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65280
+    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ADDiu]]
+    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 -256
+    %2:gprb(s32) = G_AND %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
 name:            or_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: or_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY1]], [[COPY]]
     ; MIPS32: $v0 = COPY [[OR]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = G_OR %1, %0
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
 ...
 ---
+name:            or_imm
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: or_imm
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[COPY]], 65535
+    ; MIPS32: $v0 = COPY [[ORi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 65535
+    %2:gprb(s32) = G_OR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            or_not_imm32ZExt16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: or_not_imm32ZExt16
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 1
+    ; MIPS32: [[OR:%[0-9]+]]:gpr32 = OR [[COPY]], [[LUi]]
+    ; MIPS32: $v0 = COPY [[OR]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 65536
+    %2:gprb(s32) = G_OR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
 name:            xor_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
     ; MIPS32-LABEL: name: xor_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY1]], [[COPY]]
     ; MIPS32: $v0 = COPY [[XOR]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = G_XOR %1, %0
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
 ...
 ---
+name:            xor_imm
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: xor_imm
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[COPY]], 1
+    ; MIPS32: $v0 = COPY [[XORi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 1
+    %2:gprb(s32) = G_XOR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            xor_not_imm32ZExt16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: xor_not_imm32ZExt16
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero
+    ; MIPS32: $v0 = COPY [[NOR]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 -1
+    %2:gprb(s32) = G_XOR %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
 name:            shl
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir

 body:             |
   ; MIPS32-LABEL: name: Conditional_branch
   ; MIPS32: bb.0 (%ir-block.0):
   ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32:   liveins: $a0, $a1, $a2
   ; MIPS32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
   ; MIPS32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32:   J %bb.2, implicit-def $at
   ; MIPS32: bb.1.if.then:
   ; MIPS32:   $v0 = COPY [[COPY1]]
   ; MIPS32:   RetRA implicit $v0
   ; MIPS32: bb.2.if.else:
   ; MIPS32:   $v0 = COPY [[COPY2]]
   ; MIPS32:   RetRA implicit $v0
   bb.1 (%ir-block.0):

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir

body:             |
   ; MIPS32:   [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
   ; MIPS32:   [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
   ; MIPS32:   [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
   ; MIPS32:   [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
   ; MIPS32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
   ; MIPS32:   [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
   ; MIPS32:   [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
   ; MIPS32:   [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
-  ; MIPS32:   [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi3]]
-  ; MIPS32:   BNE [[AND]], $zero, %bb.6, implicit-def $at
+  ; MIPS32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
+  ; MIPS32:   BNE [[ANDi]], $zero, %bb.6, implicit-def $at
   ; MIPS32: bb.1.entry:
   ; MIPS32:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
   ; MIPS32:   [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
   ; MIPS32:   [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
   ; MIPS32:   [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
   ; MIPS32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load 4)
   ; MIPS32:   PseudoIndirectBranch [[LW]]
   ; MIPS32: bb.2.sw.bb:
body:             |
   ; MIPS32:   RetRA implicit $v0
   ; MIPS32: bb.6.sw.default:
   ; MIPS32:   successors: %bb.7(0x80000000)
   ; MIPS32: bb.7.sw.epilog:
   ; MIPS32:   successors: %bb.13(0x40000000), %bb.8(0x40000000)
   ; MIPS32:   [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
   ; MIPS32:   [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
   ; MIPS32:   [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
-  ; MIPS32:   [[ORi7:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32:   [[AND1:%[0-9]+]]:gpr32 = AND [[SLTu1]], [[ORi7]]
-  ; MIPS32:   BNE [[AND1]], $zero, %bb.13, implicit-def $at
+  ; MIPS32:   [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
+  ; MIPS32:   BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
   ; MIPS32: bb.8.sw.epilog:
   ; MIPS32:   successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
   ; MIPS32:   [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
   ; MIPS32:   [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
   ; MIPS32:   [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
   ; MIPS32:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load 4)
   ; MIPS32:   PseudoIndirectBranch [[LW1]]
   ; MIPS32: bb.9.sw.bb4:
body:             |
   ; MIPS32_PIC:   [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
   ; MIPS32_PIC:   [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
   ; MIPS32_PIC:   [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
   ; MIPS32_PIC:   [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
   ; MIPS32_PIC:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
   ; MIPS32_PIC:   [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
   ; MIPS32_PIC:   [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
   ; MIPS32_PIC:   [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
-  ; MIPS32_PIC:   [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi3]]
-  ; MIPS32_PIC:   BNE [[AND]], $zero, %bb.6, implicit-def $at
+  ; MIPS32_PIC:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
+  ; MIPS32_PIC:   BNE [[ANDi]], $zero, %bb.6, implicit-def $at
   ; MIPS32_PIC: bb.1.entry:
   ; MIPS32_PIC:   successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
   ; MIPS32_PIC:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load 4 from got)
   ; MIPS32_PIC:   [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
   ; MIPS32_PIC:   [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
   ; MIPS32_PIC:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load 4)
   ; MIPS32_PIC:   [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
   ; MIPS32_PIC:   PseudoIndirectBranch [[ADDu2]]
body:             |
   ; MIPS32_PIC:   RetRA implicit $v0
   ; MIPS32_PIC: bb.6.sw.default:
   ; MIPS32_PIC:   successors: %bb.7(0x80000000)
   ; MIPS32_PIC: bb.7.sw.epilog:
   ; MIPS32_PIC:   successors: %bb.13(0x40000000), %bb.8(0x40000000)
   ; MIPS32_PIC:   [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
   ; MIPS32_PIC:   [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
   ; MIPS32_PIC:   [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
-  ; MIPS32_PIC:   [[ORi7:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32_PIC:   [[AND1:%[0-9]+]]:gpr32 = AND [[SLTu1]], [[ORi7]]
-  ; MIPS32_PIC:   BNE [[AND1]], $zero, %bb.13, implicit-def $at
+  ; MIPS32_PIC:   [[ANDi1:%[0-9]+]]:gpr32 = ANDi [[SLTu1]], 1
+  ; MIPS32_PIC:   BNE [[ANDi1]], $zero, %bb.13, implicit-def $at
   ; MIPS32_PIC: bb.8.sw.epilog:
   ; MIPS32_PIC:   successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
   ; MIPS32_PIC:   [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load 4 from got)
   ; MIPS32_PIC:   [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
   ; MIPS32_PIC:   [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
   ; MIPS32_PIC:   [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load 4)
   ; MIPS32_PIC:   [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
   ; MIPS32_PIC:   PseudoIndirectBranch [[ADDu4]]

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir

bb.1 (%ir-block.0):
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
     ; MIPS32: [[COPY3:%[0-9]+]]:gpr32 = COPY $a3
     ; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
     ; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
     ; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[PseudoMFHI]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
+    ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTu]], 1
+    ; MIPS32: SB [[ANDi]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
     ; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
     ; MIPS32: RetRA
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(p0) = COPY $a2
     %3:gprb(p0) = COPY $a3
     %4:gprb(s32) = G_MUL %0, %1
     %7:gprb(s32) = G_UMULH %0, %1

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir

 body:             |
   ; MIPS32FP32-LABEL: name: phi_i32
   ; MIPS32FP32: bb.0.entry:
   ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP32:   liveins: $a0, $a1, $a2
   ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
   ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP32:   J %bb.2, implicit-def $at
   ; MIPS32FP32: bb.1.cond.true:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32:   J %bb.3, implicit-def $at
   ; MIPS32FP32: bb.2.cond.false:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32: bb.3.cond.end:
   ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
   ; MIPS32FP32:   $v0 = COPY [[PHI]]
   ; MIPS32FP32:   RetRA implicit $v0
   ; MIPS32FP64-LABEL: name: phi_i32
   ; MIPS32FP64: bb.0.entry:
   ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP64:   liveins: $a0, $a1, $a2
   ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
   ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP64:   J %bb.2, implicit-def $at
   ; MIPS32FP64: bb.1.cond.true:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64:   J %bb.3, implicit-def $at
   ; MIPS32FP64: bb.2.cond.false:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64: bb.3.cond.end:
   ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
body:             |
   ; MIPS32FP32:   liveins: $a0, $a2, $a3
   ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
   ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
   ; MIPS32FP32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
   ; MIPS32FP32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
   ; MIPS32FP32:   [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
   ; MIPS32FP32:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
-  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP32:   J %bb.2, implicit-def $at
   ; MIPS32FP32: bb.1.cond.true:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32:   J %bb.3, implicit-def $at
   ; MIPS32FP32: bb.2.cond.false:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32: bb.3.cond.end:
   ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
   ; MIPS32FP32:   [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
   ; MIPS32FP32:   $v0 = COPY [[PHI]]
   ; MIPS32FP32:   $v1 = COPY [[PHI1]]
   ; MIPS32FP32:   RetRA implicit $v0, implicit $v1
   ; MIPS32FP64-LABEL: name: phi_i64
   ; MIPS32FP64: bb.0.entry:
   ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP64:   liveins: $a0, $a2, $a3
   ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
   ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
   ; MIPS32FP64:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
   ; MIPS32FP64:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
   ; MIPS32FP64:   [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
   ; MIPS32FP64:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
-  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP64:   J %bb.2, implicit-def $at
   ; MIPS32FP64: bb.1.cond.true:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64:   J %bb.3, implicit-def $at
   ; MIPS32FP64: bb.2.cond.false:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64: bb.3.cond.end:
   ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2

 body:             |
   ; MIPS32FP32-LABEL: name: phi_float
   ; MIPS32FP32: bb.0.entry:
   ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP32:   liveins: $a0, $a1, $a2
   ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32FP32:   [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
   ; MIPS32FP32:   [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
-  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP32:   J %bb.2, implicit-def $at
   ; MIPS32FP32: bb.1.cond.true:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32:   J %bb.3, implicit-def $at
   ; MIPS32FP32: bb.2.cond.false:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32: bb.3.cond.end:
   ; MIPS32FP32:   [[PHI:%[0-9]+]]:fgr32 = PHI [[MTC1_]], %bb.1, [[MTC1_1]], %bb.2
   ; MIPS32FP32:   $f0 = COPY [[PHI]]
   ; MIPS32FP32:   RetRA implicit $f0
   ; MIPS32FP64-LABEL: name: phi_float
   ; MIPS32FP64: bb.0.entry:
   ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP64:   liveins: $a0, $a1, $a2
   ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
   ; MIPS32FP64:   [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
   ; MIPS32FP64:   [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
-  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP64:   J %bb.2, implicit-def $at
   ; MIPS32FP64: bb.1.cond.true:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64:   J %bb.3, implicit-def $at
   ; MIPS32FP64: bb.2.cond.false:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64: bb.3.cond.end:
   ; MIPS32FP64:   [[PHI:%[0-9]+]]:fgr32 = PHI [[MTC1_]], %bb.1, [[MTC1_1]], %bb.2
body:             |
   ; MIPS32FP32-LABEL: name: phi_double
   ; MIPS32FP32: bb.0.entry:
   ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP32:   liveins: $d6, $d7
   ; MIPS32FP32:   [[COPY:%[0-9]+]]:afgr64 = COPY $d6
   ; MIPS32FP32:   [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
   ; MIPS32FP32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
   ; MIPS32FP32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
-  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
-  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
+  ; MIPS32FP32:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP32:   J %bb.2, implicit-def $at
   ; MIPS32FP32: bb.1.cond.true:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32:   J %bb.3, implicit-def $at
   ; MIPS32FP32: bb.2.cond.false:
   ; MIPS32FP32:   successors: %bb.3(0x80000000)
   ; MIPS32FP32: bb.3.cond.end:
   ; MIPS32FP32:   [[PHI:%[0-9]+]]:afgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
   ; MIPS32FP32:   $d0 = COPY [[PHI]]
   ; MIPS32FP32:   RetRA implicit $d0
   ; MIPS32FP64-LABEL: name: phi_double
   ; MIPS32FP64: bb.0.entry:
   ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; MIPS32FP64:   liveins: $d6, $d7
   ; MIPS32FP64:   [[COPY:%[0-9]+]]:fgr64 = COPY $d6
   ; MIPS32FP64:   [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
   ; MIPS32FP64:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
   ; MIPS32FP64:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
-  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
-  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
+  ; MIPS32FP64:   BNE [[ANDi]], $zero, %bb.1, implicit-def $at
   ; MIPS32FP64:   J %bb.2, implicit-def $at
   ; MIPS32FP64: bb.1.cond.true:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64:   J %bb.3, implicit-def $at
   ; MIPS32FP64: bb.2.cond.false:
   ; MIPS32FP64:   successors: %bb.3(0x80000000)
   ; MIPS32FP64: bb.3.cond.end:
   ; MIPS32FP64:   [[PHI:%[0-9]+]]:fgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir

body:             |
   bb.1.entry:
     liveins: $a0, $a1, $a2
 
     ; MIPS32FP32-LABEL: name: select_i32
     ; MIPS32FP32: liveins: $a0, $a1, $a2
     ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-    ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-    ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
+    ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+    ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
     ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
     ; MIPS32FP32: RetRA implicit $v0
     ; MIPS32FP64-LABEL: name: select_i32
     ; MIPS32FP64: liveins: $a0, $a1, $a2
     ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-    ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-    ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
+    ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+    ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
     ; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
     ; MIPS32FP64: RetRA implicit $v0
     %3:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = COPY $a2
     %6:gprb(s32) = G_CONSTANT i32 1
     %7:gprb(s32) = COPY %3(s32)
     %5:gprb(s32) = G_AND %7, %6
body:             |
   bb.1.entry:
     liveins: $a0, $a1, $a2
 
     ; MIPS32FP32-LABEL: name: select_ptr
     ; MIPS32FP32: liveins: $a0, $a1, $a2
     ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-    ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-    ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
+    ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+    ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
     ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
     ; MIPS32FP32: RetRA implicit $v0
     ; MIPS32FP64-LABEL: name: select_ptr
     ; MIPS32FP64: liveins: $a0, $a1, $a2
     ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32FP64: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-    ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-    ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]]
+    ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+    ; MIPS32FP64: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[ANDi]], [[COPY2]]
     ; MIPS32FP64: $v0 = COPY [[MOVN_I_I]]
     ; MIPS32FP64: RetRA implicit $v0
     %3:gprb(s32) = COPY $a0
     %1:gprb(p0) = COPY $a1
     %2:gprb(p0) = COPY $a2
     %6:gprb(s32) = G_CONSTANT i32 1
     %7:gprb(s32) = COPY %3(s32)
     %5:gprb(s32) = G_AND %7, %6
body:             |
   bb.1.entry:
     liveins: $a0, $a1, $a2
 
     ; MIPS32FP32-LABEL: name: select_float
     ; MIPS32FP32: liveins: $a0, $a1, $a2
     ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
     ; MIPS32FP32: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
-    ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-    ; MIPS32FP32: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]]
+    ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+    ; MIPS32FP32: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[ANDi]], [[MTC1_1]]
     ; MIPS32FP32: $f0 = COPY [[MOVN_I_S]]
     ; MIPS32FP32: RetRA implicit $f0
     ; MIPS32FP64-LABEL: name: select_float
     ; MIPS32FP64: liveins: $a0, $a1, $a2
     ; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
     ; MIPS32FP64: [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
-    ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-    ; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[AND]], [[MTC1_1]]
+    ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[COPY]], 1
+    ; MIPS32FP64: [[MOVN_I_S:%[0-9]+]]:fgr32 = MOVN_I_S [[MTC1_]], [[ANDi]], [[MTC1_1]]
     ; MIPS32FP64: $f0 = COPY [[MOVN_I_S]]
     ; MIPS32FP64: RetRA implicit $f0
     %3:gprb(s32) = COPY $a0
     %1:fgr32(s32) = MTC1 $a1
     %2:fgr32(s32) = MTC1 $a2
     %6:gprb(s32) = G_CONSTANT i32 1
     %7:gprb(s32) = COPY %3(s32)
     %5:gprb(s32) = G_AND %7, %6
bb.1.entry:
     liveins: $d6, $d7
 
     ; MIPS32FP32-LABEL: name: select_double
     ; MIPS32FP32: liveins: $d6, $d7
     ; MIPS32FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
     ; MIPS32FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
     ; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
     ; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
-    ; MIPS32FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP32: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
-    ; MIPS32FP32: [[MOVN_I_D32_:%[0-9]+]]:afgr64 = MOVN_I_D32 [[COPY]], [[AND]], [[COPY1]]
+    ; MIPS32FP32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
+    ; MIPS32FP32: [[MOVN_I_D32_:%[0-9]+]]:afgr64 = MOVN_I_D32 [[COPY]], [[ANDi]], [[COPY1]]
     ; MIPS32FP32: $d0 = COPY [[MOVN_I_D32_]]
     ; MIPS32FP32: RetRA implicit $d0
     ; MIPS32FP64-LABEL: name: select_double
     ; MIPS32FP64: liveins: $d6, $d7
     ; MIPS32FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
     ; MIPS32FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
     ; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
     ; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
-    ; MIPS32FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32FP64: [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
-    ; MIPS32FP64: [[MOVN_I_D64_:%[0-9]+]]:fgr64 = MOVN_I_D64 [[COPY]], [[AND]], [[COPY1]]
+    ; MIPS32FP64: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[LW]], 1
+    ; MIPS32FP64: [[MOVN_I_D64_:%[0-9]+]]:fgr64 = MOVN_I_D64 [[COPY]], [[ANDi]], [[COPY1]]
     ; MIPS32FP64: $d0 = COPY [[MOVN_I_D64_]]
     ; MIPS32FP64: RetRA implicit $d0
     %0:fprb(s64) = COPY $d6
     %1:fprb(s64) = COPY $d7
     %4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
     %3:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
     %7:gprb(s32) = G_CONSTANT i32 1
     %8:gprb(s32) = COPY %3(s32)
     %6:gprb(s32) = G_AND %8, %7
     %5:fprb(s64) = G_SELECT %6(s32), %0, %1
     $d0 = COPY %5(s64)
     RetRA implicit $d0
 
 ...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

entry:
   %add = add i8 %b, %a
   ret i8 %add
 }
 
 define zeroext i8 @add_i8_zext(i8 zeroext %a, i8 zeroext %b) {
 ; MIPS32-LABEL: add_i8_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 255
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 255
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i8 %b, %a
   ret i8 %add
 }
 
 define i8 @add_i8_aext(i8 %a, i8 %b) {
entry:
   %add = add i16 %b, %a
   ret i16 %add
 }
 
 define zeroext i16 @add_i16_zext(i16 zeroext %a, i16 zeroext %b) {
 ; MIPS32-LABEL: add_i16_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 65535
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 65535
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i16 %b, %a
   ret i16 %add
 }
 
 define i16 @add_i16_aext(i16 %a, i16 %b) {
 ; MIPS32-LABEL: add_i16_aext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i16 %b, %a
   ret i16 %add
 }
 
 define i64 @add_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: add_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addu $1, $6, $4
 ; MIPS32-NEXT:    sltu $2, $1, $4
 ; MIPS32-NEXT:    addu $3, $7, $5
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    addu $3, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }

 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 32
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    addiu $8, $sp, 36
 ; MIPS32-NEXT:    lw $8, 0($8)
 ; MIPS32-NEXT:    addu $1, $1, $4
 ; MIPS32-NEXT:    sltu $4, $1, $4
 ; MIPS32-NEXT:    addu $5, $2, $5
-; MIPS32-NEXT:    ori $9, $zero, 1
-; MIPS32-NEXT:    and $4, $4, $9
+; MIPS32-NEXT:    andi $4, $4, 1
 ; MIPS32-NEXT:    addu $4, $5, $4
 ; MIPS32-NEXT:    sltu $2, $4, $2
 ; MIPS32-NEXT:    addu $5, $3, $6
-; MIPS32-NEXT:    and $2, $2, $9
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    addu $2, $5, $2
 ; MIPS32-NEXT:    sltu $3, $2, $3
 ; MIPS32-NEXT:    addu $5, $8, $7
-; MIPS32-NEXT:    and $3, $3, $9
+; MIPS32-NEXT:    andi $3, $3, 1
 ; MIPS32-NEXT:    addu $5, $5, $3
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    move $3, $4
 ; MIPS32-NEXT:    lw $4, 4($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    addiu $sp, $sp, 8
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop

 }
 
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
 define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) {
 ; MIPS32-LABEL: uadd_with_overflow:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    addu $1, $4, $5
 ; MIPS32-NEXT:    sltu $2, $1, $5
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $3
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    sb $2, 0($7)
 ; MIPS32-NEXT:    sw $1, 0($6)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
   %res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs)
   %carry_flag = extractvalue { i32, i1 } %res, 1
   %add = extractvalue { i32, i1 } %res, 0
   store i1 %carry_flag, i1* %pcarry_flag
   store i32 %add, i32* %padd
   ret void
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll

 ; MIPS32-NEXT:    and $3, $7, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
 
+define i32 @and_imm(i32 %a) {
+; MIPS32-LABEL: and_imm:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    andi $2, $4, 255
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %and = and i32 %a, 255
+  ret i32 %and
+}
+
+define i32 @and_not_imm32ZExt16(i32 %a) {
+; MIPS32-LABEL: and_not_imm32ZExt16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $1, $zero, 65280
+; MIPS32-NEXT:    and $2, $4, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %and = and i32 %a, -256
+  ret i32 %and
+}
+
 define i1 @or_i1(i1 %a, i1 %b) {
 ; MIPS32-LABEL: or_i1:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    or $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %or = or i1 %b, %a

 ; MIPS32-NEXT:    or $3, $7, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
 
+define i32 @or_imm(i32 %a) {
+; MIPS32-LABEL: or_imm:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    ori $2, $4, 65535
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %or = or i32 %a, 65535
+  ret i32 %or
+}
+
+define i32 @or_not_imm32ZExt16(i32 %a) {
+; MIPS32-LABEL: or_not_imm32ZExt16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    lui $1, 1
+; MIPS32-NEXT:    or $2, $4, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %or = or i32 %a, 65536
+  ret i32 %or
+}
+
 define i1 @xor_i1(i1 %a, i1 %b) {
 ; MIPS32-LABEL: xor_i1:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %xor = xor i1 %b, %a

 ; MIPS32-NEXT:    xor $3, $7, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
 
+define i32 @xor_imm(i32 %a) {
+; MIPS32-LABEL: xor_imm:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xori $2, $4, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %xor = xor i32 %a, 1
+  ret i32 %xor
+}
+
+define i32 @xor_not_imm32ZExt16(i32 %a) {
+; MIPS32-LABEL: xor_not_imm32ZExt16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    not $2, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %xor = xor i32 %a, -1
+  ret i32 %xor
+}
+
 define i32 @shl(i32 %a) {
 ; MIPS32-LABEL: shl:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sll $2, $4, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %shl = shl i32 %a, 1
entry:
   %shr = lshr i32 %a, %b
   ret i32 %shr
 }
 
 define  i16 @shl_i16(i16 %a) {
 ; MIPS32-LABEL: shl_i16:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    ori $1, $zero, 2
-; MIPS32-NEXT:    ori $2, $zero, 65535
-; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    andi $1, $1, 65535
 ; MIPS32-NEXT:    sllv $2, $4, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %shl = shl i16 %a, 2
   ret i16 %shl
 }
 
 define i8 @ashr_i8(i8 %a) {
 ; MIPS32-LABEL: ashr_i8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    ori $1, $zero, 2
-; MIPS32-NEXT:    ori $2, $zero, 255
-; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    andi $1, $1, 255
 ; MIPS32-NEXT:    sll $2, $4, 24
 ; MIPS32-NEXT:    sra $2, $2, 24
 ; MIPS32-NEXT:    srav $2, $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = ashr i8 %a, 2
   ret i8 %0
 }
 
 define i16 @lshr_i16(i16 %a) {
 ; MIPS32-LABEL: lshr_i16:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    ori $1, $zero, 2
-; MIPS32-NEXT:    ori $2, $zero, 65535
-; MIPS32-NEXT:    and $1, $1, $2
-; MIPS32-NEXT:    and $2, $4, $2
+; MIPS32-NEXT:    andi $1, $1, 65535
+; MIPS32-NEXT:    andi $2, $4, 65535
 ; MIPS32-NEXT:    srlv $2, $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = lshr i16 %a, 2
   ret i16 %0
 }
 
 define i64 @shl_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: shl_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -8
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 8
 ; MIPS32-NEXT:    ori $1, $zero, 32
 ; MIPS32-NEXT:    subu $2, $6, $1
 ; MIPS32-NEXT:    subu $3, $1, $6
 ; MIPS32-NEXT:    ori $8, $zero, 0
 ; MIPS32-NEXT:    sltu $1, $6, $1
 ; MIPS32-NEXT:    sltiu $9, $6, 1
 ; MIPS32-NEXT:    sllv $10, $4, $6
 ; MIPS32-NEXT:    srlv $3, $4, $3
 ; MIPS32-NEXT:    sllv $6, $5, $6
 ; MIPS32-NEXT:    or $3, $3, $6
 ; MIPS32-NEXT:    sllv $2, $4, $2
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $6, $1, $4
-; MIPS32-NEXT:    movn $8, $10, $6
-; MIPS32-NEXT:    and $1, $1, $4
+; MIPS32-NEXT:    andi $4, $1, 1
+; MIPS32-NEXT:    movn $8, $10, $4
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    movn $2, $3, $1
-; MIPS32-NEXT:    and $1, $9, $4
+; MIPS32-NEXT:    andi $1, $9, 1
 ; MIPS32-NEXT:    movn $2, $5, $1
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    move $2, $8
 ; MIPS32-NEXT:    lw $3, 4($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    addiu $sp, $sp, 8
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:

 ; MIPS32-NEXT:    sltu $1, $6, $1
 ; MIPS32-NEXT:    sltiu $8, $6, 1
 ; MIPS32-NEXT:    srav $9, $5, $6
 ; MIPS32-NEXT:    srlv $6, $4, $6
 ; MIPS32-NEXT:    sllv $3, $5, $3
 ; MIPS32-NEXT:    or $3, $6, $3
 ; MIPS32-NEXT:    sra $6, $5, 31
 ; MIPS32-NEXT:    srav $2, $5, $2
-; MIPS32-NEXT:    ori $5, $zero, 1
-; MIPS32-NEXT:    and $10, $1, $5
-; MIPS32-NEXT:    movn $2, $3, $10
-; MIPS32-NEXT:    and $3, $8, $5
+; MIPS32-NEXT:    andi $5, $1, 1
+; MIPS32-NEXT:    movn $2, $3, $5
+; MIPS32-NEXT:    andi $3, $8, 1
 ; MIPS32-NEXT:    movn $2, $4, $3
-; MIPS32-NEXT:    and $1, $1, $5
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    movn $6, $9, $1
 ; MIPS32-NEXT:    move $3, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %shr = ashr i64 %a, %b
   ret i64 %shr
 }
 
 define i64 @lshr_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: lshr_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    ori $1, $zero, 32
 ; MIPS32-NEXT:    subu $2, $6, $1
 ; MIPS32-NEXT:    subu $3, $1, $6
 ; MIPS32-NEXT:    ori $8, $zero, 0
 ; MIPS32-NEXT:    sltu $1, $6, $1
 ; MIPS32-NEXT:    sltiu $9, $6, 1
 ; MIPS32-NEXT:    srlv $10, $5, $6
 ; MIPS32-NEXT:    srlv $6, $4, $6
 ; MIPS32-NEXT:    sllv $3, $5, $3
 ; MIPS32-NEXT:    or $3, $6, $3
 ; MIPS32-NEXT:    srlv $2, $5, $2
-; MIPS32-NEXT:    ori $5, $zero, 1
-; MIPS32-NEXT:    and $6, $1, $5
-; MIPS32-NEXT:    movn $2, $3, $6
-; MIPS32-NEXT:    and $3, $9, $5
+; MIPS32-NEXT:    andi $5, $1, 1
+; MIPS32-NEXT:    movn $2, $3, $5
+; MIPS32-NEXT:    andi $3, $9, 1
 ; MIPS32-NEXT:    movn $2, $4, $3
-; MIPS32-NEXT:    and $1, $1, $5
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    movn $8, $10, $1
 ; MIPS32-NEXT:    move $3, $8
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %shr = lshr i64 %a, %b
   ret i64 %shr
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll

block:
   br label %end
 }
 
 define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
 ; MIPS32-LABEL: Conditional_branch:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    addiu $sp, $sp, -8
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 8
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    sw $5, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB1_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1:
 ; MIPS32-NEXT:    j $BB1_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_2: # %if.then

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll

 entry:
   ret i8 -128
 }
 
 define zeroext i16 @unsigned_i16() {
 ; MIPS32-LABEL: unsigned_i16:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $1, $zero, 32768
-; MIPS32-NEXT:    ori $2, $zero, 65535
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 65535
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i16 -32768
 }
 
 define zeroext i8 @unsigned_i8() {
 ; MIPS32-LABEL: unsigned_i8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $1, $zero, 65408
-; MIPS32-NEXT:    ori $2, $zero, 255
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 255
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i8 -128
 }
 
 define zeroext i1 @i1_true() {
 ; MIPS32-LABEL: i1_true:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $1, $zero, 65535
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i1 true
 }
 
 define zeroext i1 @i1_false() {
 ; MIPS32-LABEL: i1_false:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    ori $1, $zero, 0
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   ret i1 false
 }
 
 define i32 @_0xABCD0000() {
 ; MIPS32-LABEL: _0xABCD0000:

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll

 ; MIPS32-NEXT:    trunc.w.s $f1, $f1
 ; MIPS32-NEXT:    mfc1 $2, $f1
 ; MIPS32-NEXT:    lui $3, 32768
 ; MIPS32-NEXT:    xor $2, $2, $3
 ; MIPS32-NEXT:    addiu $3, $zero, 1
 ; MIPS32-NEXT:    c.ult.s $f12, $f0
 ; MIPS32-NEXT:    movf $3, $zero, $fcc0
 ; MIPS32-NEXT:    movn $2, $1, $3
-; MIPS32-NEXT:    ori $1, $zero, 65535
-; MIPS32-NEXT:    and $2, $2, $1
+; MIPS32-NEXT:    andi $2, $2, 65535
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %conv = fptoui float %a to i16
   ret i16 %conv
 }
 
 define zeroext i8 @f32tou8(float %a) {
 ; MIPS32-LABEL: f32tou8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    trunc.w.s $f0, $f12
 ; MIPS32-NEXT:    mfc1 $1, $f0
 ; MIPS32-NEXT:    lui $2, 20224
 ; MIPS32-NEXT:    mtc1 $2, $f0
 ; MIPS32-NEXT:    sub.s $f1, $f12, $f0
 ; MIPS32-NEXT:    trunc.w.s $f1, $f1
 ; MIPS32-NEXT:    mfc1 $2, $f1
 ; MIPS32-NEXT:    lui $3, 32768
 ; MIPS32-NEXT:    xor $2, $2, $3
 ; MIPS32-NEXT:    addiu $3, $zero, 1
 ; MIPS32-NEXT:    c.ult.s $f12, $f0
 ; MIPS32-NEXT:    movf $3, $zero, $fcc0
 ; MIPS32-NEXT:    movn $2, $1, $3
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    and $2, $2, $1
+; MIPS32-NEXT:    andi $2, $2, 255
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %conv = fptoui float %a to i8
   ret i8 %conv
 }
 
 define i64 @f64tou64(double %a) {

 ; FP32-NEXT:    trunc.w.d $f0, $f4
 ; FP32-NEXT:    mfc1 $2, $f0
 ; FP32-NEXT:    lui $3, 32768
 ; FP32-NEXT:    xor $2, $2, $3
 ; FP32-NEXT:    addiu $3, $zero, 1
 ; FP32-NEXT:    c.ult.d $f12, $f2
 ; FP32-NEXT:    movf $3, $zero, $fcc0
 ; FP32-NEXT:    movn $2, $1, $3
-; FP32-NEXT:    ori $1, $zero, 65535
-; FP32-NEXT:    and $2, $2, $1
+; FP32-NEXT:    andi $2, $2, 65535
 ; FP32-NEXT:    jr $ra
 ; FP32-NEXT:    nop
 ;
 ; FP64-LABEL: f64tou16:
 ; FP64:       # %bb.0: # %entry
 ; FP64-NEXT:    trunc.w.d $f0, $f12
 ; FP64-NEXT:    mfc1 $1, $f0
 ; FP64-NEXT:    lui $2, 16864
 ; FP64-NEXT:    ori $3, $zero, 0
 ; FP64-NEXT:    mtc1 $3, $f1
 ; FP64-NEXT:    mthc1 $2, $f1
 ; FP64-NEXT:    sub.d $f2, $f12, $f1
 ; FP64-NEXT:    trunc.w.d $f0, $f2
 ; FP64-NEXT:    mfc1 $2, $f0
 ; FP64-NEXT:    lui $3, 32768
 ; FP64-NEXT:    xor $2, $2, $3
 ; FP64-NEXT:    addiu $3, $zero, 1
 ; FP64-NEXT:    c.ult.d $f12, $f1
 ; FP64-NEXT:    movf $3, $zero, $fcc0
 ; FP64-NEXT:    movn $2, $1, $3
-; FP64-NEXT:    ori $1, $zero, 65535
-; FP64-NEXT:    and $2, $2, $1
+; FP64-NEXT:    andi $2, $2, 65535
 ; FP64-NEXT:    jr $ra
 ; FP64-NEXT:    nop
 entry:
   %conv = fptoui double %a to i16
   ret i16 %conv
 }
 
 define zeroext i8 @f64tou8(double %a) {

 ; FP32-NEXT:    trunc.w.d $f0, $f4
 ; FP32-NEXT:    mfc1 $2, $f0
 ; FP32-NEXT:    lui $3, 32768
 ; FP32-NEXT:    xor $2, $2, $3
 ; FP32-NEXT:    addiu $3, $zero, 1
 ; FP32-NEXT:    c.ult.d $f12, $f2
 ; FP32-NEXT:    movf $3, $zero, $fcc0
 ; FP32-NEXT:    movn $2, $1, $3
-; FP32-NEXT:    ori $1, $zero, 255
-; FP32-NEXT:    and $2, $2, $1
+; FP32-NEXT:    andi $2, $2, 255
 ; FP32-NEXT:    jr $ra
 ; FP32-NEXT:    nop
 ;
 ; FP64-LABEL: f64tou8:
 ; FP64:       # %bb.0: # %entry
 ; FP64-NEXT:    trunc.w.d $f0, $f12
 ; FP64-NEXT:    mfc1 $1, $f0
 ; FP64-NEXT:    lui $2, 16864
 ; FP64-NEXT:    ori $3, $zero, 0
 ; FP64-NEXT:    mtc1 $3, $f1
 ; FP64-NEXT:    mthc1 $2, $f1
 ; FP64-NEXT:    sub.d $f2, $f12, $f1
 ; FP64-NEXT:    trunc.w.d $f0, $f2
 ; FP64-NEXT:    mfc1 $2, $f0
 ; FP64-NEXT:    lui $3, 32768
 ; FP64-NEXT:    xor $2, $2, $3
 ; FP64-NEXT:    addiu $3, $zero, 1
 ; FP64-NEXT:    c.ult.d $f12, $f1
 ; FP64-NEXT:    movf $3, $zero, $fcc0
 ; FP64-NEXT:    movn $2, $1, $3
-; FP64-NEXT:    ori $1, $zero, 255
-; FP64-NEXT:    and $2, $2, $1
+; FP64-NEXT:    andi $2, $2, 255
 ; FP64-NEXT:    jr $ra
 ; FP64-NEXT:    nop
 entry:
   %conv = fptoui double %a to i8
   ret i8 %conv
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll

 entry:
   %cmp = icmp eq i32* %a, %b
   ret i1 %cmp
 }
 
 define i1 @ult_i8(i8 %a, i8 %b) {
 ; MIPS32-LABEL: ult_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    and $2, $4, $1
-; MIPS32-NEXT:    and $1, $5, $1
-; MIPS32-NEXT:    sltu $2, $2, $1
+; MIPS32-NEXT:    andi $1, $4, 255
+; MIPS32-NEXT:    andi $2, $5, 255
+; MIPS32-NEXT:    sltu $2, $1, $2
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ult i8 %a, %b
   ret i1 %cmp
 }
 
 define i1 @slt_i16(i16 %a, i16 %b) {

 
 define i1 @sgt_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: sgt_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $7, $5
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $6, $4
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sgt i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @sge_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: sge_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $5, $7
 ; MIPS32-NEXT:    xori $1, $1, 1
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $4, $6
 ; MIPS32-NEXT:    xori $3, $3, 1
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sge i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @slt_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: slt_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $5, $7
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $4, $6
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp slt i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @sle_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: sle_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $7, $5
 ; MIPS32-NEXT:    xori $1, $1, 1
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $6, $4
 ; MIPS32-NEXT:    xori $3, $3, 1
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sle i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @ugt_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: ugt_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $7, $5
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $6, $4
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ugt i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @uge_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: uge_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $5, $7
 ; MIPS32-NEXT:    xori $1, $1, 1
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $4, $6
 ; MIPS32-NEXT:    xori $3, $3, 1
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp uge i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @ult_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: ult_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $5, $7
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $4, $6
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ult i64 %a, %b
   ret i1 %cmp
 }
 
 define i1 @ule_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: ule_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $7, $5
 ; MIPS32-NEXT:    xori $1, $1, 1
 ; MIPS32-NEXT:    xor $2, $5, $7
 ; MIPS32-NEXT:    sltiu $2, $2, 1
 ; MIPS32-NEXT:    sltu $3, $6, $4
 ; MIPS32-NEXT:    xori $3, $3, 1
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    movn $1, $3, $2
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ule i64 %a, %b
   ret i1 %cmp
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -relocation-model=pic -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32_PIC
 
 define i32 @mod4_0_to_11(i32 %a) {
 ; MIPS32-LABEL: mod4_0_to_11:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -32
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 32
 ; MIPS32-NEXT:    ori $1, $zero, 7
 ; MIPS32-NEXT:    ori $2, $zero, 3
 ; MIPS32-NEXT:    ori $3, $zero, 2
 ; MIPS32-NEXT:    ori $5, $zero, 1
 ; MIPS32-NEXT:    ori $6, $zero, 0
 ; MIPS32-NEXT:    addiu $7, $zero, 65535
 ; MIPS32-NEXT:    ori $8, $zero, 0
 ; MIPS32-NEXT:    subu $8, $4, $8
 ; MIPS32-NEXT:    sltu $1, $1, $8
-; MIPS32-NEXT:    and $1, $1, $5
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    sw $4, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $8, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB0_6

 ; MIPS32-NEXT:  $BB0_6: # %sw.default
 ; MIPS32-NEXT:    .insn
 ; MIPS32-NEXT:  # %bb.7: # %sw.epilog
 ; MIPS32-NEXT:    ori $1, $zero, 8
 ; MIPS32-NEXT:    lw $2, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    subu $1, $2, $1
 ; MIPS32-NEXT:    lw $3, 24($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sltu $4, $3, $1
-; MIPS32-NEXT:    ori $5, $zero, 1
-; MIPS32-NEXT:    and $4, $4, $5
+; MIPS32-NEXT:    andi $4, $4, 1
 ; MIPS32-NEXT:    sw $1, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $4, $BB0_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_8: # %sw.epilog
 ; MIPS32-NEXT:    lui $1, %hi($JTI0_1)
 ; MIPS32-NEXT:    lw $2, 0($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sll $3, $2, 2
 ; MIPS32-NEXT:    addu $1, $1, $3

 ; MIPS32_PIC-NEXT:    ori $3, $zero, 3
 ; MIPS32_PIC-NEXT:    ori $5, $zero, 2
 ; MIPS32_PIC-NEXT:    ori $6, $zero, 1
 ; MIPS32_PIC-NEXT:    ori $7, $zero, 0
 ; MIPS32_PIC-NEXT:    addiu $8, $zero, 65535
 ; MIPS32_PIC-NEXT:    ori $9, $zero, 0
 ; MIPS32_PIC-NEXT:    subu $9, $4, $9
 ; MIPS32_PIC-NEXT:    sltu $2, $2, $9
-; MIPS32_PIC-NEXT:    and $2, $2, $6
+; MIPS32_PIC-NEXT:    andi $2, $2, 1
 ; MIPS32_PIC-NEXT:    sw $1, 36($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $4, 32($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $3, 28($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $5, 24($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $6, 20($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $7, 16($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $8, 12($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    sw $9, 8($sp) # 4-byte Folded Spill

 ; MIPS32_PIC-NEXT:  $BB0_6: # %sw.default
 ; MIPS32_PIC-NEXT:    .insn
 ; MIPS32_PIC-NEXT:  # %bb.7: # %sw.epilog
 ; MIPS32_PIC-NEXT:    ori $1, $zero, 8
 ; MIPS32_PIC-NEXT:    lw $2, 32($sp) # 4-byte Folded Reload
 ; MIPS32_PIC-NEXT:    subu $1, $2, $1
 ; MIPS32_PIC-NEXT:    lw $3, 28($sp) # 4-byte Folded Reload
 ; MIPS32_PIC-NEXT:    sltu $4, $3, $1
-; MIPS32_PIC-NEXT:    ori $5, $zero, 1
-; MIPS32_PIC-NEXT:    and $4, $4, $5
+; MIPS32_PIC-NEXT:    andi $4, $4, 1
 ; MIPS32_PIC-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32_PIC-NEXT:    bnez $4, $BB0_13
 ; MIPS32_PIC-NEXT:    nop
 ; MIPS32_PIC-NEXT:  $BB0_8: # %sw.epilog
 ; MIPS32_PIC-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
 ; MIPS32_PIC-NEXT:    lw $2, %got($JTI0_1)($1)
 ; MIPS32_PIC-NEXT:    lw $3, 4($sp) # 4-byte Folded Reload
 ; MIPS32_PIC-NEXT:    sll $4, $3, 2

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* %b, i32* %c, i32* %result) {
 ; MIPS32-LABEL: long_chain_ambiguous_i32_in_gpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -48
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 48
 ; MIPS32-NEXT:    addiu $1, $sp, 64
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 68
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 72
 ; MIPS32-NEXT:    lw $3, 0($3)
-; MIPS32-NEXT:    ori $8, $zero, 1
-; MIPS32-NEXT:    and $8, $4, $8
+; MIPS32-NEXT:    andi $8, $4, 1
 ; MIPS32-NEXT:    sw $1, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 40($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 36($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 32($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $8, $BB0_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 36($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB0_4
+; MIPS32-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB0_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 32($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB0_5
+; MIPS32-NEXT:    lw $1, 32($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB0_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB0_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB0_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 24($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB0_6: # %b.PHI.1
 ; MIPS32-NEXT:    lw $1, 16($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    lw $3, 32($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    lw $2, 32($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $2, $BB0_8
+; MIPS32-NEXT:    bnez $3, $BB0_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB0_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 48
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB0_11
+; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB0_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB0_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB0_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB0_13: # %b.PHI.2
 ; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    lw $3, 36($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    lw $2, 36($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    sw $1, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $2, $BB0_15
+; MIPS32-NEXT:    bnez $3, $BB0_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    lw $1, 0($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 48
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_15: # %b.PHI.3
 ; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 8($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    lw $4, 32($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $5, $4, $3
-; MIPS32-NEXT:    movn $1, $2, $5
-; MIPS32-NEXT:    lw $5, 36($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $5, $3
+; MIPS32-NEXT:    lw $3, 32($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $4, $3, 1
+; MIPS32-NEXT:    movn $1, $2, $4
+; MIPS32-NEXT:    lw $4, 36($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $5, $4, 1
 ; MIPS32-NEXT:    move $6, $2
-; MIPS32-NEXT:    movn $6, $1, $3
+; MIPS32-NEXT:    movn $6, $1, $5
 ; MIPS32-NEXT:    lw $1, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $6, 0($1)
 ; MIPS32-NEXT:    sw $2, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 48
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

 ; MIPS32-NEXT:    .cfi_def_cfa_offset 56
 ; MIPS32-NEXT:    addiu $1, $sp, 72
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 76
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 80
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    ori $8, $zero, 0
-; MIPS32-NEXT:    ori $9, $zero, 1
-; MIPS32-NEXT:    and $9, $4, $9
+; MIPS32-NEXT:    andi $9, $4, 1
 ; MIPS32-NEXT:    sw $1, 52($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 48($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 40($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 36($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 32($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $8, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $9, $BB1_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB1_4
+; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB1_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB1_5
+; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB1_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB1_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB1_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 32($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB1_6: # %b.PHI.1
 ; MIPS32-NEXT:    lw $1, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    lw $3, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    lw $5, 24($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $2, $BB1_8
+; MIPS32-NEXT:    bnez $3, $BB1_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB1_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    lw $1, 16($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 56
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 48($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB1_11
+; MIPS32-NEXT:    lw $1, 48($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB1_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB1_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB1_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB1_13: # %b.PHI.2
 ; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    lw $3, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    lw $2, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    move $5, $1
 ; MIPS32-NEXT:    sw $1, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $2, $BB1_15
+; MIPS32-NEXT:    bnez $3, $BB1_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    lw $1, 0($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 56
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_15: # %b.PHI.3
 ; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    lw $4, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $5, $4, $3
-; MIPS32-NEXT:    movn $1, $2, $5
-; MIPS32-NEXT:    lw $5, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $5, $3
+; MIPS32-NEXT:    lw $3, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $4, $3, 1
+; MIPS32-NEXT:    movn $1, $2, $4
+; MIPS32-NEXT:    lw $4, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $5, $4, 1
 ; MIPS32-NEXT:    move $6, $2
-; MIPS32-NEXT:    movn $6, $1, $3
+; MIPS32-NEXT:    movn $6, $1, $5
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $6, 0($1)
 ; MIPS32-NEXT:    sw $2, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 56
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

 ; MIPS32-NEXT:    addiu $sp, $sp, -48
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 48
 ; MIPS32-NEXT:    addiu $1, $sp, 64
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 68
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 72
 ; MIPS32-NEXT:    lw $3, 0($3)
-; MIPS32-NEXT:    ori $8, $zero, 1
-; MIPS32-NEXT:    and $8, $4, $8
+; MIPS32-NEXT:    andi $8, $4, 1
 ; MIPS32-NEXT:    sw $1, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 40($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 36($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 32($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $8, $BB2_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 36($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB2_4
+; MIPS32-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB2_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 32($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB2_5
+; MIPS32-NEXT:    lw $1, 32($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB2_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB2_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB2_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 24($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB2_6: # %b.PHI.1
 ; MIPS32-NEXT:    lw $1, 16($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    lw $3, 32($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    lw $2, 32($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $2, $BB2_8
+; MIPS32-NEXT:    bnez $3, $BB2_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB2_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    lw $1, 12($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 48
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB2_11
+; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB2_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB2_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB2_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB2_13: # %b.PHI.2
 ; MIPS32-NEXT:    lw $1, 4($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    lw $3, 36($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $2, $3, $2
+; MIPS32-NEXT:    lw $2, 36($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    sw $1, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $2, $BB2_15
+; MIPS32-NEXT:    bnez $3, $BB2_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    lw $1, 0($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 48
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_15: # %b.PHI.3
 ; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 8($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    lw $4, 32($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $5, $4, $3
-; MIPS32-NEXT:    movn $1, $2, $5
-; MIPS32-NEXT:    lw $5, 36($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $5, $3
+; MIPS32-NEXT:    lw $3, 32($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $4, $3, 1
+; MIPS32-NEXT:    movn $1, $2, $4
+; MIPS32-NEXT:    lw $4, 36($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $5, $4, 1
 ; MIPS32-NEXT:    move $6, $2
-; MIPS32-NEXT:    movn $6, $1, $3
+; MIPS32-NEXT:    movn $6, $1, $5
 ; MIPS32-NEXT:    lw $1, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $6, 0($1)
 ; MIPS32-NEXT:    sw $2, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 48
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1

 ; MIPS32-NEXT:    addiu $1, $sp, 72
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 76
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 80
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    ori $8, $zero, 0
 ; MIPS32-NEXT:    mtc1 $8, $f0
-; MIPS32-NEXT:    ori $8, $zero, 1
-; MIPS32-NEXT:    and $8, $4, $8
+; MIPS32-NEXT:    andi $8, $4, 1
 ; MIPS32-NEXT:    sw $1, 52($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 48($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 40($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 36($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 32($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    swc1 $f0, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $8, $BB3_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB3_4
+; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB3_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB3_5
+; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB3_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lwc1 $f0, 0($1)
 ; MIPS32-NEXT:    swc1 $f0, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB3_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lwc1 $f0, 0($1)
 ; MIPS32-NEXT:    swc1 $f0, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB3_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 32($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lwc1 $f0, 0($1)
 ; MIPS32-NEXT:    swc1 $f0, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB3_6: # %b.PHI.1
 ; MIPS32-NEXT:    lwc1 $f0, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.s $f1, $f0
 ; MIPS32-NEXT:    lwc1 $f2, 24($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    swc1 $f0, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    swc1 $f1, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    swc1 $f2, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB3_8
+; MIPS32-NEXT:    bnez $2, $BB3_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB3_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    lwc1 $f0, 16($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    swc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 56
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 48($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB3_11
+; MIPS32-NEXT:    lw $1, 48($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB3_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB3_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 36($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lwc1 $f0, 0($1)
 ; MIPS32-NEXT:    swc1 $f0, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB3_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lwc1 $f0, 0($1)
 ; MIPS32-NEXT:    swc1 $f0, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB3_13: # %b.PHI.2
 ; MIPS32-NEXT:    lwc1 $f0, 4($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.s $f1, $f0
 ; MIPS32-NEXT:    mov.s $f2, $f0
 ; MIPS32-NEXT:    swc1 $f0, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    swc1 $f1, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    swc1 $f2, 8($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB3_15
+; MIPS32-NEXT:    bnez $2, $BB3_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    lwc1 $f0, 0($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    swc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 56
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_15: # %b.PHI.3
 ; MIPS32-NEXT:    lwc1 $f0, 8($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lwc1 $f1, 12($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 40($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $2, $1
-; MIPS32-NEXT:    movn.s $f0, $f1, $3
-; MIPS32-NEXT:    lw $3, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $3, $1
+; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    movn.s $f0, $f1, $2
+; MIPS32-NEXT:    lw $2, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    mov.s $f2, $f1
-; MIPS32-NEXT:    movn.s $f2, $f0, $1
-; MIPS32-NEXT:    lw $1, 28($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    swc1 $f2, 0($1)
-; MIPS32-NEXT:    swc1 $f1, 0($1)
+; MIPS32-NEXT:    movn.s $f2, $f0, $3
+; MIPS32-NEXT:    lw $3, 28($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    swc1 $f2, 0($3)
+; MIPS32-NEXT:    swc1 $f1, 0($3)
 ; MIPS32-NEXT:    addiu $sp, $sp, 56
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1
 
 pre.PHI.1:
   br i1 %cnd1, label %b.PHI.1.1, label %pre.PHI.1.0

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %b, i64* %c, i64* %result) {
 ; MIPS32-LABEL: long_chain_ambiguous_i64_in_fpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -72
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 72
 ; MIPS32-NEXT:    addiu $1, $sp, 88
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 92
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 96
 ; MIPS32-NEXT:    lw $3, 0($3)
-; MIPS32-NEXT:    ori $8, $zero, 1
-; MIPS32-NEXT:    and $8, $4, $8
+; MIPS32-NEXT:    andi $8, $4, 1
 ; MIPS32-NEXT:    sw $1, 68($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 64($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 60($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 56($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 52($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 48($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $8, $BB0_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB0_4
+; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB0_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 56($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB0_5
+; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB0_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB0_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB0_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 48($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:  $BB0_6: # %b.PHI.1
 ; MIPS32-NEXT:    ldc1 $f0, 32($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 56($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.d $f2, $f0
 ; MIPS32-NEXT:    sdc1 $f0, 24($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 16($sp) # 8-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB0_8
+; MIPS32-NEXT:    bnez $2, $BB0_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB0_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    ldc1 $f0, 24($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 72
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 64($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB0_11
+; MIPS32-NEXT:    lw $1, 64($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB0_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB0_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB0_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:  $BB0_13: # %b.PHI.2
 ; MIPS32-NEXT:    ldc1 $f0, 8($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.d $f2, $f0
 ; MIPS32-NEXT:    sdc1 $f0, 0($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 16($sp) # 8-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB0_15
+; MIPS32-NEXT:    bnez $2, $BB0_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    ldc1 $f0, 0($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 72
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_15: # %b.PHI.3
 ; MIPS32-NEXT:    ldc1 $f0, 16($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f2, 16($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 56($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $2, $1
-; MIPS32-NEXT:    movn.d $f0, $f2, $3
-; MIPS32-NEXT:    lw $3, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $3, $1
+; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    movn.d $f0, $f2, $2
+; MIPS32-NEXT:    lw $2, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    mov.d $f4, $f2
-; MIPS32-NEXT:    movn.d $f4, $f0, $1
-; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    sdc1 $f4, 0($1)
-; MIPS32-NEXT:    sdc1 $f2, 0($1)
+; MIPS32-NEXT:    movn.d $f4, $f0, $3
+; MIPS32-NEXT:    lw $3, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sdc1 $f4, 0($3)
+; MIPS32-NEXT:    sdc1 $f2, 0($3)
 ; MIPS32-NEXT:    addiu $sp, $sp, 72
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1
 
 pre.PHI.1:
   br i1 %cnd1, label %b.PHI.1.1, label %pre.PHI.1.0

 ; MIPS32-NEXT:    .cfi_def_cfa_offset 80
 ; MIPS32-NEXT:    addiu $1, $sp, 96
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 100
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 104
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    ori $8, $zero, 0
-; MIPS32-NEXT:    ori $9, $zero, 1
-; MIPS32-NEXT:    and $9, $4, $9
+; MIPS32-NEXT:    andi $9, $4, 1
 ; MIPS32-NEXT:    sw $1, 76($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 72($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 68($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 64($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 60($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 56($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 52($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $8, 48($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $9, $BB1_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 68($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB1_4
+; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB1_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 64($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB1_5
+; MIPS32-NEXT:    lw $1, 64($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB1_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    lw $3, 4($1)
 ; MIPS32-NEXT:    sw $2, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 40($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB1_6

 ; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    lw $3, 4($1)
 ; MIPS32-NEXT:    sw $2, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 40($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB1_6: # %b.PHI.1
 ; MIPS32-NEXT:    lw $1, 40($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    lw $4, 64($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $4, $3
+; MIPS32-NEXT:    lw $3, 64($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $4, $3, 1
 ; MIPS32-NEXT:    move $5, $2
 ; MIPS32-NEXT:    move $6, $1
 ; MIPS32-NEXT:    lw $7, 48($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $8, 48($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 36($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 32($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $8, 16($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $3, $BB1_8
+; MIPS32-NEXT:    bnez $4, $BB1_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB1_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    lw $1, 32($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    lw $3, 36($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $3, 4($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 80
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 72($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB1_11
+; MIPS32-NEXT:    lw $1, 72($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB1_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB1_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    lw $3, 4($1)
 ; MIPS32-NEXT:    sw $2, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    j $BB1_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 76($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 0($1)
 ; MIPS32-NEXT:    lw $3, 4($1)
 ; MIPS32-NEXT:    sw $2, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:  $BB1_13: # %b.PHI.2
 ; MIPS32-NEXT:    lw $1, 8($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 12($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    lw $4, 68($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $4, $3
+; MIPS32-NEXT:    lw $3, 68($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $4, $3, 1
 ; MIPS32-NEXT:    move $5, $2
 ; MIPS32-NEXT:    move $6, $1
 ; MIPS32-NEXT:    move $7, $2
 ; MIPS32-NEXT:    move $8, $1
 ; MIPS32-NEXT:    sw $1, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 0($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $8, 16($sp) # 4-byte Folded Spill
-; MIPS32-NEXT:    bnez $3, $BB1_15
+; MIPS32-NEXT:    bnez $4, $BB1_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    lw $1, 0($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $1, 0($2)
 ; MIPS32-NEXT:    lw $3, 4($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $3, 4($2)
 ; MIPS32-NEXT:    addiu $sp, $sp, 80
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_15: # %b.PHI.3
 ; MIPS32-NEXT:    lw $1, 16($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $2, 20($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $3, 24($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    lw $4, 28($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    ori $5, $zero, 1
-; MIPS32-NEXT:    lw $6, 64($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $7, $6, $5
-; MIPS32-NEXT:    movn $2, $4, $7
-; MIPS32-NEXT:    movn $1, $3, $7
-; MIPS32-NEXT:    lw $7, 68($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $5, $7, $5
+; MIPS32-NEXT:    lw $5, 64($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $6, $5, 1
+; MIPS32-NEXT:    movn $2, $4, $6
+; MIPS32-NEXT:    movn $1, $3, $6
+; MIPS32-NEXT:    lw $6, 68($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $7, $6, 1
 ; MIPS32-NEXT:    move $8, $4
-; MIPS32-NEXT:    movn $8, $2, $5
+; MIPS32-NEXT:    movn $8, $2, $7
 ; MIPS32-NEXT:    move $2, $3
-; MIPS32-NEXT:    movn $2, $1, $5
+; MIPS32-NEXT:    movn $2, $1, $7
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sw $8, 0($1)
 ; MIPS32-NEXT:    sw $2, 4($1)
 ; MIPS32-NEXT:    sw $4, 0($1)
 ; MIPS32-NEXT:    sw $3, 4($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 80
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop

 ; MIPS32-NEXT:    addiu $sp, $sp, -72
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 72
 ; MIPS32-NEXT:    addiu $1, $sp, 88
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 92
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 96
 ; MIPS32-NEXT:    lw $3, 0($3)
-; MIPS32-NEXT:    ori $8, $zero, 1
-; MIPS32-NEXT:    and $8, $4, $8
+; MIPS32-NEXT:    andi $8, $4, 1
 ; MIPS32-NEXT:    sw $1, 68($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 64($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 60($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 56($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 52($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 48($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 44($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $8, $BB2_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB2_4
+; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB2_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 56($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB2_5
+; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB2_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB2_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB2_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 48($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:  $BB2_6: # %b.PHI.1
 ; MIPS32-NEXT:    ldc1 $f0, 32($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 56($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.d $f2, $f0
 ; MIPS32-NEXT:    sdc1 $f0, 24($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 16($sp) # 8-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB2_8
+; MIPS32-NEXT:    bnez $2, $BB2_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB2_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    ldc1 $f0, 24($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 72
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 64($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB2_11
+; MIPS32-NEXT:    lw $1, 64($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB2_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB2_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 52($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB2_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:  $BB2_13: # %b.PHI.2
 ; MIPS32-NEXT:    ldc1 $f0, 8($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.d $f2, $f0
 ; MIPS32-NEXT:    sdc1 $f0, 0($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 16($sp) # 8-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB2_15
+; MIPS32-NEXT:    bnez $2, $BB2_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    ldc1 $f0, 0($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 72
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_15: # %b.PHI.3
 ; MIPS32-NEXT:    ldc1 $f0, 16($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f2, 16($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 56($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $2, $1
-; MIPS32-NEXT:    movn.d $f0, $f2, $3
-; MIPS32-NEXT:    lw $3, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $3, $1
+; MIPS32-NEXT:    lw $1, 56($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    movn.d $f0, $f2, $2
+; MIPS32-NEXT:    lw $2, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    mov.d $f4, $f2
-; MIPS32-NEXT:    movn.d $f4, $f0, $1
-; MIPS32-NEXT:    lw $1, 44($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    sdc1 $f4, 0($1)
-; MIPS32-NEXT:    sdc1 $f2, 0($1)
+; MIPS32-NEXT:    movn.d $f4, $f0, $3
+; MIPS32-NEXT:    lw $3, 44($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sdc1 $f4, 0($3)
+; MIPS32-NEXT:    sdc1 $f2, 0($3)
 ; MIPS32-NEXT:    addiu $sp, $sp, 72
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1
 
 pre.PHI.1:
   br i1 %cnd1, label %b.PHI.1.1, label %pre.PHI.1.0

 ; MIPS32-NEXT:    addiu $2, $sp, 108
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 112
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    ori $8, $zero, 0
 ; MIPS32-NEXT:    ori $9, $zero, 0
 ; MIPS32-NEXT:    mtc1 $9, $f0
 ; MIPS32-NEXT:    mtc1 $8, $f1
-; MIPS32-NEXT:    ori $8, $zero, 1
-; MIPS32-NEXT:    and $8, $4, $8
+; MIPS32-NEXT:    andi $8, $4, 1
 ; MIPS32-NEXT:    sw $1, 84($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $4, 80($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $5, 76($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 72($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 68($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 64($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $3, 60($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f0, 48($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    bnez $8, $BB3_9
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %pre.PHI.1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 76($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB3_4
+; MIPS32-NEXT:    lw $1, 76($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB3_4
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.2: # %pre.PHI.1.0
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 72($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB3_5
+; MIPS32-NEXT:    lw $1, 72($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB3_5
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.3: # %b.PHI.1.0
 ; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 40($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB3_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_4: # %b.PHI.1.1
 ; MIPS32-NEXT:    lw $1, 84($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 40($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB3_6
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_5: # %b.PHI.1.2
 ; MIPS32-NEXT:    lw $1, 64($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 40($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:  $BB3_6: # %b.PHI.1
 ; MIPS32-NEXT:    ldc1 $f0, 40($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 72($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 72($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.d $f2, $f0
 ; MIPS32-NEXT:    ldc1 $f4, 48($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 32($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 24($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f4, 16($sp) # 8-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB3_8
+; MIPS32-NEXT:    bnez $2, $BB3_8
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.7: # %b.PHI.1
 ; MIPS32-NEXT:    j $BB3_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_8: # %b.PHI.1.end
 ; MIPS32-NEXT:    ldc1 $f0, 32($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 88
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_9: # %pre.PHI.2
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 80($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
-; MIPS32-NEXT:    bnez $1, $BB3_11
+; MIPS32-NEXT:    lw $1, 80($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    bnez $2, $BB3_11
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.10: # %pre.PHI.2
 ; MIPS32-NEXT:    j $BB3_12
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_11: # %b.PHI.2.0
 ; MIPS32-NEXT:    lw $1, 68($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    j $BB3_13
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_12: # %b.PHI.2.1
 ; MIPS32-NEXT:    lw $1, 84($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f0, 0($1)
 ; MIPS32-NEXT:    sdc1 $f0, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:  $BB3_13: # %b.PHI.2
 ; MIPS32-NEXT:    ldc1 $f0, 8($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 76($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $2, $1
+; MIPS32-NEXT:    lw $1, 76($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
 ; MIPS32-NEXT:    mov.d $f2, $f0
 ; MIPS32-NEXT:    mov.d $f4, $f0
 ; MIPS32-NEXT:    sdc1 $f0, 0($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 24($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f4, 16($sp) # 8-byte Folded Spill
-; MIPS32-NEXT:    bnez $1, $BB3_15
+; MIPS32-NEXT:    bnez $2, $BB3_15
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.14: # %b.PHI.2.end
 ; MIPS32-NEXT:    ldc1 $f0, 0($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    sdc1 $f0, 0($1)
 ; MIPS32-NEXT:    addiu $sp, $sp, 88
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_15: # %b.PHI.3
 ; MIPS32-NEXT:    ldc1 $f0, 16($sp) # 8-byte Folded Reload
 ; MIPS32-NEXT:    ldc1 $f2, 24($sp) # 8-byte Folded Reload
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    lw $2, 72($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $3, $2, $1
-; MIPS32-NEXT:    movn.d $f0, $f2, $3
-; MIPS32-NEXT:    lw $3, 76($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    and $1, $3, $1
+; MIPS32-NEXT:    lw $1, 72($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    movn.d $f0, $f2, $2
+; MIPS32-NEXT:    lw $2, 76($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    andi $3, $2, 1
 ; MIPS32-NEXT:    mov.d $f4, $f2
-; MIPS32-NEXT:    movn.d $f4, $f0, $1
-; MIPS32-NEXT:    lw $1, 60($sp) # 4-byte Folded Reload
-; MIPS32-NEXT:    sdc1 $f4, 0($1)
-; MIPS32-NEXT:    sdc1 $f2, 0($1)
+; MIPS32-NEXT:    movn.d $f4, $f0, $3
+; MIPS32-NEXT:    lw $3, 60($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    sdc1 $f4, 0($3)
+; MIPS32-NEXT:    sdc1 $f2, 0($3)
 ; MIPS32-NEXT:    addiu $sp, $sp, 88
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   br i1 %cnd0, label %pre.PHI.2, label %pre.PHI.1
 
 pre.PHI.1:
   br i1 %cnd1, label %b.PHI.1.1, label %pre.PHI.1.0

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll

entry:
   %mul = mul i8 %b, %a
   ret i8 %mul
 }
 
 define zeroext i8 @mul_i8_zext(i8 zeroext %a, i8 zeroext %b) {
 ; MIPS32-LABEL: mul_i8_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    mul $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 255
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 255
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %mul = mul i8 %b, %a
   ret i8 %mul
 }
 
 define i8 @mul_i8_aext(i8 %a, i8 %b) {
entry:
   %mul = mul i16 %b, %a
   ret i16 %mul
 }
 
 define zeroext i16 @mul_i16_zext(i16 zeroext %a, i16 zeroext %b) {
 ; MIPS32-LABEL: mul_i16_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    mul $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 65535
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 65535
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %mul = mul i16 %b, %a
   ret i16 %mul
 }
 
 define i16 @mul_i16_aext(i16 %a, i16 %b) {

 ; MIPS32-NEXT:    lw $8, 0($8)
 ; MIPS32-NEXT:    mul $9, $1, $4
 ; MIPS32-NEXT:    mul $10, $2, $4
 ; MIPS32-NEXT:    mul $11, $1, $5
 ; MIPS32-NEXT:    multu $1, $4
 ; MIPS32-NEXT:    mfhi $12
 ; MIPS32-NEXT:    addu $10, $10, $11
 ; MIPS32-NEXT:    sltu $11, $10, $11
-; MIPS32-NEXT:    ori $13, $zero, 1
-; MIPS32-NEXT:    and $11, $11, $13
+; MIPS32-NEXT:    andi $11, $11, 1
 ; MIPS32-NEXT:    addu $10, $10, $12
 ; MIPS32-NEXT:    sltu $12, $10, $12
-; MIPS32-NEXT:    and $12, $12, $13
+; MIPS32-NEXT:    andi $12, $12, 1
 ; MIPS32-NEXT:    addu $11, $11, $12
 ; MIPS32-NEXT:    mul $12, $3, $4
-; MIPS32-NEXT:    mul $14, $2, $5
-; MIPS32-NEXT:    mul $15, $1, $6
+; MIPS32-NEXT:    mul $13, $2, $5
+; MIPS32-NEXT:    mul $14, $1, $6
 ; MIPS32-NEXT:    multu $2, $4
-; MIPS32-NEXT:    mfhi $24
+; MIPS32-NEXT:    mfhi $15
 ; MIPS32-NEXT:    multu $1, $5
-; MIPS32-NEXT:    mfhi $25
+; MIPS32-NEXT:    mfhi $24
+; MIPS32-NEXT:    addu $12, $12, $13
+; MIPS32-NEXT:    sltu $13, $12, $13
+; MIPS32-NEXT:    andi $13, $13, 1
 ; MIPS32-NEXT:    addu $12, $12, $14
 ; MIPS32-NEXT:    sltu $14, $12, $14
-; MIPS32-NEXT:    and $14, $14, $13
+; MIPS32-NEXT:    andi $14, $14, 1
+; MIPS32-NEXT:    addu $13, $13, $14
 ; MIPS32-NEXT:    addu $12, $12, $15
-; MIPS32-NEXT:    sltu $15, $12, $15
-; MIPS32-NEXT:    and $15, $15, $13
-; MIPS32-NEXT:    addu $14, $14, $15
+; MIPS32-NEXT:    sltu $14, $12, $15
+; MIPS32-NEXT:    andi $14, $14, 1
+; MIPS32-NEXT:    addu $13, $13, $14
 ; MIPS32-NEXT:    addu $12, $12, $24
-; MIPS32-NEXT:    sltu $15, $12, $24
-; MIPS32-NEXT:    and $15, $15, $13
-; MIPS32-NEXT:    addu $14, $14, $15
-; MIPS32-NEXT:    addu $12, $12, $25
-; MIPS32-NEXT:    sltu $15, $12, $25
-; MIPS32-NEXT:    and $15, $15, $13
-; MIPS32-NEXT:    addu $14, $14, $15
+; MIPS32-NEXT:    sltu $14, $12, $24
+; MIPS32-NEXT:    andi $14, $14, 1
+; MIPS32-NEXT:    addu $13, $13, $14
 ; MIPS32-NEXT:    addu $12, $12, $11
 ; MIPS32-NEXT:    sltu $11, $12, $11
-; MIPS32-NEXT:    and $11, $11, $13
-; MIPS32-NEXT:    addu $11, $14, $11
+; MIPS32-NEXT:    andi $11, $11, 1
+; MIPS32-NEXT:    addu $11, $13, $11
 ; MIPS32-NEXT:    mul $8, $8, $4
 ; MIPS32-NEXT:    mul $13, $3, $5
 ; MIPS32-NEXT:    mul $14, $2, $6
 ; MIPS32-NEXT:    mul $7, $1, $7
 ; MIPS32-NEXT:    multu $3, $4
 ; MIPS32-NEXT:    mfhi $3
 ; MIPS32-NEXT:    multu $2, $5
 ; MIPS32-NEXT:    mfhi $2

 declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32)
 define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag) {
 ; MIPS32-LABEL: umul_with_overflow:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    mul $1, $4, $5
 ; MIPS32-NEXT:    multu $4, $5
 ; MIPS32-NEXT:    mfhi $2
 ; MIPS32-NEXT:    sltu $2, $zero, $2
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $2, $2, $3
+; MIPS32-NEXT:    andi $2, $2, 1
 ; MIPS32-NEXT:    sb $2, 0($7)
 ; MIPS32-NEXT:    sw $1, 0($6)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
   %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs)
   %carry_flag = extractvalue { i32, i1 } %res, 1
   %mul = extractvalue { i32, i1 } %res, 0
   store i1 %carry_flag, i1* %pcarry_flag
   store i32 %mul, i32* %pmul
   ret void
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define i1 @phi_i1(i1 %cnd, i1 %a, i1 %b) {
 ; MIPS32-LABEL: phi_i1:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB0_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB0_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB0_2: # %cond.true
cond.end:
   ret i1 %cond
 }
 
 define i8 @phi_i8(i1 %cnd, i8 %a, i8 %b) {
 ; MIPS32-LABEL: phi_i8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB1_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB1_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB1_2: # %cond.true
cond.end:
   ret i8 %cond
 }
 
 define i16 @phi_i16(i1 %cnd, i16 %a, i16 %b) {
 ; MIPS32-LABEL: phi_i16:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB2_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB2_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB2_2: # %cond.true
cond.end:
   ret i16 %cond
 }
 
 define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
 ; MIPS32-LABEL: phi_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    sw $5, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB3_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB3_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB3_2: # %cond.true

 ; MIPS32-LABEL: phi_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -24
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 24
 ; MIPS32-NEXT:    addiu $1, $sp, 40
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 44
 ; MIPS32-NEXT:    lw $2, 0($2)
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $3, $4, $3
+; MIPS32-NEXT:    andi $3, $4, 1
 ; MIPS32-NEXT:    sw $1, 20($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $6, 16($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $3, $BB4_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB4_3

 
 define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
 ; MIPS32-LABEL: phi_ambiguous_i64_in_fpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -32
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 32
 ; MIPS32-NEXT:    ldc1 $f0, 0($5)
 ; MIPS32-NEXT:    ldc1 $f2, 0($6)
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    sw $7, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f0, 16($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f2, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB5_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB5_3
 ; MIPS32-NEXT:    nop

 
 define float @phi_float(i1 %cnd, float %a, float %b) {
 ; MIPS32-LABEL: phi_float:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
 ; MIPS32-NEXT:    mtc1 $5, $f0
 ; MIPS32-NEXT:    mtc1 $6, $f1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    swc1 $f0, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    swc1 $f1, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB6_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB6_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB6_2: # %cond.true

 
 define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {
 ; MIPS32-LABEL: phi_ambiguous_float_in_gpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 16
 ; MIPS32-NEXT:    lw $1, 0($5)
 ; MIPS32-NEXT:    lw $2, 0($6)
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $3, $4, $3
+; MIPS32-NEXT:    andi $3, $4, 1
 ; MIPS32-NEXT:    sw $1, 12($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $7, 8($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    bnez $3, $BB7_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB7_3
 ; MIPS32-NEXT:    nop

 
 define double @phi_double(double %a, double %b, i1 %cnd) {
 ; MIPS32-LABEL: phi_double:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -24
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 24
 ; MIPS32-NEXT:    addiu $1, $sp, 40
 ; MIPS32-NEXT:    lw $1, 0($1)
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    sdc1 $f12, 16($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    sdc1 $f14, 8($sp) # 8-byte Folded Spill
 ; MIPS32-NEXT:    bnez $1, $BB8_2
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  # %bb.1: # %entry
 ; MIPS32-NEXT:    j $BB8_3
 ; MIPS32-NEXT:    nop
 ; MIPS32-NEXT:  $BB8_2: # %cond.true

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll

entry:
   %rem = srem i64 %b, %a
   ret i64 %rem
 }
 
 ; udiv
 define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
 ; MIPS32-LABEL: udiv_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    and $2, $5, $1
-; MIPS32-NEXT:    and $1, $4, $1
-; MIPS32-NEXT:    divu $zero, $2, $1
-; MIPS32-NEXT:    teq $1, $zero, 7
+; MIPS32-NEXT:    andi $1, $5, 255
+; MIPS32-NEXT:    andi $2, $4, 255
+; MIPS32-NEXT:    divu $zero, $1, $2
+; MIPS32-NEXT:    teq $2, $zero, 7
 ; MIPS32-NEXT:    mflo $1
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $2, $1, 24
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %div = udiv i8 %b, %a
   ret i8 %div
 }
 
 define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
 ; MIPS32-LABEL: udiv_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 65535
-; MIPS32-NEXT:    and $2, $5, $1
-; MIPS32-NEXT:    and $1, $4, $1
-; MIPS32-NEXT:    divu $zero, $2, $1
-; MIPS32-NEXT:    teq $1, $zero, 7
+; MIPS32-NEXT:    andi $1, $5, 65535
+; MIPS32-NEXT:    andi $2, $4, 65535
+; MIPS32-NEXT:    divu $zero, $1, $2
+; MIPS32-NEXT:    teq $2, $zero, 7
 ; MIPS32-NEXT:    mflo $1
 ; MIPS32-NEXT:    sll $1, $1, 16
 ; MIPS32-NEXT:    sra $2, $1, 16
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %div = udiv i16 %b, %a
   ret i16 %div
entry:
   %div = udiv i64 %b, %a
   ret i64 %div
 }
 
 ; urem
 define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
 ; MIPS32-LABEL: urem_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 255
-; MIPS32-NEXT:    and $2, $5, $1
-; MIPS32-NEXT:    and $1, $4, $1
-; MIPS32-NEXT:    divu $zero, $2, $1
-; MIPS32-NEXT:    teq $1, $zero, 7
+; MIPS32-NEXT:    andi $1, $5, 255
+; MIPS32-NEXT:    andi $2, $4, 255
+; MIPS32-NEXT:    divu $zero, $1, $2
+; MIPS32-NEXT:    teq $2, $zero, 7
 ; MIPS32-NEXT:    mfhi $1
 ; MIPS32-NEXT:    sll $1, $1, 24
 ; MIPS32-NEXT:    sra $2, $1, 24
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %rem = urem i8 %b, %a
   ret i8 %rem
 }
 
 define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
 ; MIPS32-LABEL: urem_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 65535
-; MIPS32-NEXT:    and $2, $5, $1
-; MIPS32-NEXT:    and $1, $4, $1
-; MIPS32-NEXT:    divu $zero, $2, $1
-; MIPS32-NEXT:    teq $1, $zero, 7
+; MIPS32-NEXT:    andi $1, $5, 65535
+; MIPS32-NEXT:    andi $2, $4, 65535
+; MIPS32-NEXT:    divu $zero, $1, $2
+; MIPS32-NEXT:    teq $2, $zero, 7
 ; MIPS32-NEXT:    mfhi $1
 ; MIPS32-NEXT:    sll $1, $1, 16
 ; MIPS32-NEXT:    sra $2, $1, 16
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %rem = urem i16 %b, %a
   ret i16 %rem

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
 define i8 @select_i8(i1 %test, i8 %a, i8 %b) {
 ; MIPS32-LABEL: select_i8:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i8 %a, i8 %b
   ret i8 %cond
 }
 
 define i16 @select_i16(i1 %test, i16 %a, i16 %b) {
 ; MIPS32-LABEL: select_i16:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i16 %a, i16 %b
   ret i16 %cond
 }
 
 define i32 @select_i32(i1 %test, i32 %a, i32 %b) {
 ; MIPS32-LABEL: select_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i32 %a, i32 %b
   ret i32 %cond
 }
 
 define i32* @select_ptr(i1 %test, i32* %a, i32* %b) {
 ; MIPS32-LABEL: select_ptr:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    movn $6, $5, $1
 ; MIPS32-NEXT:    move $2, $6
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i32* %a, i32* %b
   ret i32* %cond
 }
 
 define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
 ; MIPS32-LABEL: select_with_negation:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $4, $5
 ; MIPS32-NEXT:    not $1, $1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    movn $7, $6, $1
 ; MIPS32-NEXT:    move $2, $7
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp slt i32 %a, %b
   %lneg = xor i1 %cmp, true
   %cond = select i1 %lneg, i32 %x, i32 %y
   ret i32 %cond
 }
 
 define i64 @select_i64(i1 %test, i64 %a, i64 %b) {
 ; MIPS32-LABEL: select_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $sp, $sp, -8
 ; MIPS32-NEXT:    .cfi_def_cfa_offset 8
 ; MIPS32-NEXT:    addiu $1, $sp, 24
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 28
 ; MIPS32-NEXT:    lw $2, 0($2)
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $3, $4, $3
+; MIPS32-NEXT:    andi $3, $4, 1
 ; MIPS32-NEXT:    movn $1, $6, $3
 ; MIPS32-NEXT:    movn $2, $7, $3
 ; MIPS32-NEXT:    sw $2, 4($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    move $2, $1
 ; MIPS32-NEXT:    lw $3, 4($sp) # 4-byte Folded Reload
 ; MIPS32-NEXT:    addiu $sp, $sp, 8
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, i64 %a, i64 %b
   ret i64 %cond
 }
 
 define void @select_ambiguous_i64_in_fpr(i1 %test, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
 ; MIPS32-LABEL: select_ambiguous_i64_in_fpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    ldc1 $f0, 0($5)
 ; MIPS32-NEXT:    ldc1 $f2, 0($6)
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    movn.d $f2, $f0, $1
 ; MIPS32-NEXT:    sdc1 $f2, 0($7)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load i64, i64* %i64_ptr_a, align 8
   %1 = load i64, i64* %i64_ptr_b, align 8
   %cond = select i1 %test, i64 %0, i64 %1
   store i64 %cond, i64* %i64_ptr_c, align 8
   ret void
 }
 
 define float @select_float(i1 %test, float %a, float %b) {
 ; MIPS32-LABEL: select_float:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    mtc1 $5, $f0
 ; MIPS32-NEXT:    mtc1 $6, $f1
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    andi $1, $4, 1
 ; MIPS32-NEXT:    movn.s $f1, $f0, $1
 ; MIPS32-NEXT:    mov.s $f0, $f1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, float %a, float %b
   ret float %cond
 }
 
 define void @select_ambiguous_float_in_gpr(i1 %test, float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {
 ; MIPS32-LABEL: select_ambiguous_float_in_gpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lw $1, 0($5)
 ; MIPS32-NEXT:    lw $2, 0($6)
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $3, $4, $3
+; MIPS32-NEXT:    andi $3, $4, 1
 ; MIPS32-NEXT:    movn $2, $1, $3
 ; MIPS32-NEXT:    sw $2, 0($7)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load float, float* %f32_ptr_a, align 4
   %1 = load float, float* %f32_ptr_b, align 4
   %cond = select i1 %test, float %0, float %1
   store float %cond, float* %f32_ptr_c, align 4
   ret void
 }
 
 define double @select_double(double %a, double %b, i1 %test) {
 ; MIPS32-LABEL: select_double:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $1, $sp, 16
 ; MIPS32-NEXT:    lw $1, 0($1)
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    movn.d $f14, $f12, $1
 ; MIPS32-NEXT:    mov.d $f0, $f14
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cond = select i1 %test, double %a, double %b
   ret double %cond
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll

 entry:
   %conv = uitofp i32 %a to float
   ret float %conv
 }
 
 define float @u16tof32(i16 zeroext %a) {
 ; FP32-LABEL: u16tof32:
 ; FP32:       # %bb.0: # %entry
-; FP32-NEXT:    ori $1, $zero, 65535
-; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    andi $1, $4, 65535
 ; FP32-NEXT:    lui $2, 17200
 ; FP32-NEXT:    mtc1 $1, $f0
 ; FP32-NEXT:    mtc1 $2, $f1
 ; FP32-NEXT:    lui $1, 17200
 ; FP32-NEXT:    ori $2, $zero, 0
 ; FP32-NEXT:    mtc1 $2, $f2
 ; FP32-NEXT:    mtc1 $1, $f3
 ; FP32-NEXT:    sub.d $f0, $f0, $f2
 ; FP32-NEXT:    cvt.s.d $f0, $f0
 ; FP32-NEXT:    jr $ra
 ; FP32-NEXT:    nop
 ;
 ; FP64-LABEL: u16tof32:
 ; FP64:       # %bb.0: # %entry
-; FP64-NEXT:    ori $1, $zero, 65535
-; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    andi $1, $4, 65535
 ; FP64-NEXT:    lui $2, 17200
 ; FP64-NEXT:    mtc1 $1, $f0
 ; FP64-NEXT:    mthc1 $2, $f0
 ; FP64-NEXT:    lui $1, 17200
 ; FP64-NEXT:    ori $2, $zero, 0
 ; FP64-NEXT:    mtc1 $2, $f1
 ; FP64-NEXT:    mthc1 $1, $f1
 ; FP64-NEXT:    sub.d $f0, $f0, $f1
 ; FP64-NEXT:    cvt.s.d $f0, $f0
 ; FP64-NEXT:    jr $ra
 ; FP64-NEXT:    nop
 entry:
   %conv = uitofp i16 %a to float
   ret float %conv
 }
 
 define float @u8tof32(i8 zeroext %a) {
 ; FP32-LABEL: u8tof32:
 ; FP32:       # %bb.0: # %entry
-; FP32-NEXT:    ori $1, $zero, 255
-; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    andi $1, $4, 255
 ; FP32-NEXT:    lui $2, 17200
 ; FP32-NEXT:    mtc1 $1, $f0
 ; FP32-NEXT:    mtc1 $2, $f1
 ; FP32-NEXT:    lui $1, 17200
 ; FP32-NEXT:    ori $2, $zero, 0
 ; FP32-NEXT:    mtc1 $2, $f2
 ; FP32-NEXT:    mtc1 $1, $f3
 ; FP32-NEXT:    sub.d $f0, $f0, $f2
 ; FP32-NEXT:    cvt.s.d $f0, $f0
 ; FP32-NEXT:    jr $ra
 ; FP32-NEXT:    nop
 ;
 ; FP64-LABEL: u8tof32:
 ; FP64:       # %bb.0: # %entry
-; FP64-NEXT:    ori $1, $zero, 255
-; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    andi $1, $4, 255
 ; FP64-NEXT:    lui $2, 17200
 ; FP64-NEXT:    mtc1 $1, $f0
 ; FP64-NEXT:    mthc1 $2, $f0
 ; FP64-NEXT:    lui $1, 17200
 ; FP64-NEXT:    ori $2, $zero, 0
 ; FP64-NEXT:    mtc1 $2, $f1
 ; FP64-NEXT:    mthc1 $1, $f1
 ; FP64-NEXT:    sub.d $f0, $f0, $f1

 entry:
   %conv = uitofp i32 %a to double
   ret double %conv
 }
 
 define double @u16tof64(i16 zeroext %a) {
 ; FP32-LABEL: u16tof64:
 ; FP32:       # %bb.0: # %entry
-; FP32-NEXT:    ori $1, $zero, 65535
-; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    andi $1, $4, 65535
 ; FP32-NEXT:    lui $2, 17200
 ; FP32-NEXT:    mtc1 $1, $f0
 ; FP32-NEXT:    mtc1 $2, $f1
 ; FP32-NEXT:    lui $1, 17200
 ; FP32-NEXT:    ori $2, $zero, 0
 ; FP32-NEXT:    mtc1 $2, $f2
 ; FP32-NEXT:    mtc1 $1, $f3
 ; FP32-NEXT:    sub.d $f0, $f0, $f2
 ; FP32-NEXT:    jr $ra
 ; FP32-NEXT:    nop
 ;
 ; FP64-LABEL: u16tof64:
 ; FP64:       # %bb.0: # %entry
-; FP64-NEXT:    ori $1, $zero, 65535
-; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    andi $1, $4, 65535
 ; FP64-NEXT:    lui $2, 17200
 ; FP64-NEXT:    mtc1 $1, $f0
 ; FP64-NEXT:    mthc1 $2, $f0
 ; FP64-NEXT:    lui $1, 17200
 ; FP64-NEXT:    ori $2, $zero, 0
 ; FP64-NEXT:    mtc1 $2, $f1
 ; FP64-NEXT:    mthc1 $1, $f1
 ; FP64-NEXT:    sub.d $f0, $f0, $f1
 ; FP64-NEXT:    jr $ra
 ; FP64-NEXT:    nop
 entry:
   %conv = uitofp i16 %a to double
   ret double %conv
 }
 
 define double @u8tof64(i8 zeroext %a) {
 ; FP32-LABEL: u8tof64:
 ; FP32:       # %bb.0: # %entry
-; FP32-NEXT:    ori $1, $zero, 255
-; FP32-NEXT:    and $1, $4, $1
+; FP32-NEXT:    andi $1, $4, 255
 ; FP32-NEXT:    lui $2, 17200
 ; FP32-NEXT:    mtc1 $1, $f0
 ; FP32-NEXT:    mtc1 $2, $f1
 ; FP32-NEXT:    lui $1, 17200
 ; FP32-NEXT:    ori $2, $zero, 0
 ; FP32-NEXT:    mtc1 $2, $f2
 ; FP32-NEXT:    mtc1 $1, $f3
 ; FP32-NEXT:    sub.d $f0, $f0, $f2
 ; FP32-NEXT:    jr $ra
 ; FP32-NEXT:    nop
 ;
 ; FP64-LABEL: u8tof64:
 ; FP64:       # %bb.0: # %entry
-; FP64-NEXT:    ori $1, $zero, 255
-; FP64-NEXT:    and $1, $4, $1
+; FP64-NEXT:    andi $1, $4, 255
 ; FP64-NEXT:    lui $2, 17200
 ; FP64-NEXT:    mtc1 $1, $f0
 ; FP64-NEXT:    mthc1 $2, $f0
 ; FP64-NEXT:    lui $1, 17200
 ; FP64-NEXT:    ori $2, $zero, 0
 ; FP64-NEXT:    mtc1 $2, $f1
 ; FP64-NEXT:    mthc1 $1, $f1
 ; FP64-NEXT:    sub.d $f0, $f0, $f1
 ; FP64-NEXT:    jr $ra
 ; FP64-NEXT:    nop
 entry:
   %conv = uitofp i8 %a to double
   ret double %conv
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll

entry:
   %sub = sub i8 %b, %a
   ret i8 %sub
 }
 
 define zeroext i8 @sub_i8_zext(i8 zeroext %a, i8 zeroext %b) {
 ; MIPS32-LABEL: sub_i8_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 255
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 255
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i8 %b, %a
   ret i8 %sub
 }
 
 define i8 @sub_i8_aext(i8 %a, i8 %b) {
entry:
   %sub = sub i16 %b, %a
   ret i16 %sub
 }
 
 define zeroext i16 @sub_i16_zext(i16 zeroext %a, i16 zeroext %b) {
 ; MIPS32-LABEL: sub_i16_zext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 65535
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    andi $2, $1, 65535
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i16 %b, %a
   ret i16 %sub
 }
 
 define i16 @sub_i16_aext(i16 %a, i16 %b) {
 ; MIPS32-LABEL: sub_i16_aext:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i16 %b, %a
   ret i16 %sub
 }
 
 define i64 @sub_i64(i64 %a, i64 %b) {
 ; MIPS32-LABEL: sub_i64:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    subu $2, $6, $4
 ; MIPS32-NEXT:    sltu $1, $6, $4
 ; MIPS32-NEXT:    subu $3, $7, $5
-; MIPS32-NEXT:    ori $4, $zero, 1
-; MIPS32-NEXT:    and $1, $1, $4
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    subu $3, $3, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i64 %b, %a
   ret i64 %sub
 }
 
 define i128 @sub_i128(i128 %a, i128 %b) {
 ; MIPS32-LABEL: sub_i128:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    addiu $1, $sp, 16
 ; MIPS32-NEXT:    lw $1, 0($1)
 ; MIPS32-NEXT:    addiu $2, $sp, 20
 ; MIPS32-NEXT:    lw $2, 0($2)
 ; MIPS32-NEXT:    addiu $3, $sp, 24
 ; MIPS32-NEXT:    lw $3, 0($3)
 ; MIPS32-NEXT:    addiu $8, $sp, 28
 ; MIPS32-NEXT:    lw $8, 0($8)
 ; MIPS32-NEXT:    subu $9, $1, $4
 ; MIPS32-NEXT:    sltu $1, $1, $4
 ; MIPS32-NEXT:    subu $4, $2, $5
-; MIPS32-NEXT:    ori $10, $zero, 1
-; MIPS32-NEXT:    and $11, $1, $10
-; MIPS32-NEXT:    subu $4, $4, $11
-; MIPS32-NEXT:    xor $11, $2, $5
-; MIPS32-NEXT:    sltiu $11, $11, 1
+; MIPS32-NEXT:    andi $10, $1, 1
+; MIPS32-NEXT:    subu $4, $4, $10
+; MIPS32-NEXT:    xor $10, $2, $5
+; MIPS32-NEXT:    sltiu $10, $10, 1
 ; MIPS32-NEXT:    sltu $2, $2, $5
-; MIPS32-NEXT:    and $5, $11, $10
+; MIPS32-NEXT:    andi $5, $10, 1
 ; MIPS32-NEXT:    movn $2, $1, $5
 ; MIPS32-NEXT:    subu $1, $3, $6
-; MIPS32-NEXT:    and $5, $2, $10
+; MIPS32-NEXT:    andi $5, $2, 1
 ; MIPS32-NEXT:    subu $1, $1, $5
 ; MIPS32-NEXT:    xor $5, $3, $6
 ; MIPS32-NEXT:    sltiu $5, $5, 1
 ; MIPS32-NEXT:    sltu $3, $3, $6
-; MIPS32-NEXT:    and $5, $5, $10
+; MIPS32-NEXT:    andi $5, $5, 1
 ; MIPS32-NEXT:    movn $3, $2, $5
 ; MIPS32-NEXT:    subu $2, $8, $7
-; MIPS32-NEXT:    and $3, $3, $10
+; MIPS32-NEXT:    andi $3, $3, 1
 ; MIPS32-NEXT:    subu $5, $2, $3
 ; MIPS32-NEXT:    move $2, $9
 ; MIPS32-NEXT:    move $3, $4
 ; MIPS32-NEXT:    move $4, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %sub = sub i128 %b, %a
   ret i128 %sub
 }

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll

entry:
   %outgoing_instr = fadd float %0, %1
   ret float %outgoing_instr
 }
 
 define i32 @incoming_gpr(i32 %incoming_phys_reg, i1 %test, i32* %a) {
 ; MIPS32-LABEL: incoming_gpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lw $1, 0($6)
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $5, $2
+; MIPS32-NEXT:    andi $2, $5, 1
 ; MIPS32-NEXT:    movn $4, $1, $2
 ; MIPS32-NEXT:    move $2, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load i32, i32* %a
   %cond = select i1 %test, i32 %0, i32 %incoming_phys_reg
   ret i32 %cond
 }
 
 define float @incoming_fpr(float %incoming_phys_reg, i1 %test, float* %a) {
 ; MIPS32-LABEL: incoming_fpr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lwc1 $f0, 0($6)
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $5, $1
+; MIPS32-NEXT:    andi $1, $5, 1
 ; MIPS32-NEXT:    movn.s $f12, $f0, $1
 ; MIPS32-NEXT:    mov.s $f0, $f12
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load float, float* %a
   %cond = select i1 %test, float %0, float %incoming_phys_reg
   ret float %cond
 }
 
 
 define i32 @incoming_i32_instr(i32 %val1, i32 %val2, i32* %i32_ptr, i1 %test) {
 ; MIPS32-LABEL: incoming_i32_instr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lw $1, 0($6)
 ; MIPS32-NEXT:    addu $2, $5, $4
-; MIPS32-NEXT:    ori $3, $zero, 1
-; MIPS32-NEXT:    and $3, $7, $3
+; MIPS32-NEXT:    andi $3, $7, 1
 ; MIPS32-NEXT:    movn $2, $1, $3
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load i32, i32* %i32_ptr
   %incoming_instr = add i32 %val2, %val1
   %cond = select i1 %test, i32 %0, i32 %incoming_instr
   ret i32 %cond
 }
 
 define float @incoming_float_instr(float %val1, float %val2, float* %float_ptr, i1 %test) {
 ; MIPS32-LABEL: incoming_float_instr:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lwc1 $f0, 0($6)
 ; MIPS32-NEXT:    add.s $f1, $f14, $f12
-; MIPS32-NEXT:    ori $1, $zero, 1
-; MIPS32-NEXT:    and $1, $7, $1
+; MIPS32-NEXT:    andi $1, $7, 1
 ; MIPS32-NEXT:    movn.s $f1, $f0, $1
 ; MIPS32-NEXT:    mov.s $f0, $f1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load float, float* %float_ptr
   %incoming_instr = fadd float %val2, %val1
   %cond = select i1 %test, float %0, float %incoming_instr
   ret float %cond
 }
 

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/truncStore_and_aExtLoad.ll

entry:
   %0 = load i16, i16* %px
   ret i16 %0
 }
 
 define void @load_store_i1(i1* %px, i1* %py) {
 ; MIPS32-LABEL: load_store_i1:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lbu $1, 0($5)
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    andi $1, $1, 1
 ; MIPS32-NEXT:    sb $1, 0($4)
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %0 = load i1, i1* %py
   store i1 %0, i1* %px
   ret void
 }