[MIPS GlobalISel] Select addiu

[Petar.Avramovic]

Summary

Introduce IntImmLeaf version of PatLeaf immSExt16 for 32-bit immediates.
Change immSExt16 with imm32SExt16 for addiu.
This keeps same behavior for SDAG and allows for GlobalISel selectImpl
to select 'G_CONSTANT imm' + G_ADD into ADDIu when 32-bit imm satisfies
imm32SExt16 predicate: sign extending 16 low bits of imm is equal to imm.

[atanasyan]

LGTM

llvm/lib/Target/Mips/MipsInstrInfo.td

1268

It's unrelated to this patch but probably this comment should say about "8-bit sign extended".

llvm/lib/Target/Mips/MipsInstrInfo.td

 }]>;
 
 // Plus 1.
 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
 
 // Node immediate is zero (e.g. insve.d)
 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
 
 // Node immediate fits as 16-bit sign extended on target immediate.
 // e.g. addi, andi
 def immSExt8  : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
 
 // Node immediate fits as 16-bit sign extended on target immediate.
 // e.g. addi, andi
 def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
+def imm32SExt16  : IntImmLeaf<i32, [{ return isInt<16>(Imm.getSExtValue()); }]>;
 
 // Node immediate fits as 7-bit zero extended on target immediate.
 def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;
 def timmZExt7 : PatLeaf<(timm), [{ return isUInt<7>(N->getZExtValue()); }]>;
 
 // Node immediate fits as 16-bit zero extended on target immediate.
 // The LO16 param means that only the lower 16 bits of the node
 // immediate are caught.

 //===----------------------------------------------------------------------===//
 //===----------------------------------------------------------------------===//
 // MipsI Instructions
 //===----------------------------------------------------------------------===//
 
 /// Arithmetic Instructions (ALU Immediate)
 let AdditionalPredicates = [NotInMicroMips] in {
   def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
-                                             II_ADDIU, immSExt16, add>,
+                                             II_ADDIU, imm32SExt16, add>,
               ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1;
 
   def ANDi : MMRel, StdMMR6Rel,
              ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
              ADDI_FM<0xc>, ISA_MIPS1;
   def ORi  : MMRel, StdMMR6Rel,
              ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
              ADDI_FM<0xd>, ISA_MIPS1;

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @add_i32(i32 %x, i32 %y) {entry: ret void}
+  define void @add_i32() {entry: ret void}
+  define void @add_imm() {entry: ret void}
+  define void @add_negative_imm() {entry: ret void}
+  define void @add_not_imm32SExt16() {entry: ret void}
 
 ...
 ---
 name:            add_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
bb.0.entry:
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %2:gprb(s32) = G_ADD %0, %1
     $v0 = COPY %2(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            add_imm
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: add_imm
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], 3
+    ; MIPS32: $v0 = COPY [[ADDiu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 3
+    %2:gprb(s32) = G_ADD %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            add_negative_imm
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: add_negative_imm
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], -3
+    ; MIPS32: $v0 = COPY [[ADDiu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 -3
+    %2:gprb(s32) = G_ADD %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            add_not_imm32SExt16
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: add_not_imm32SExt16
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 65535
+    ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[COPY]], [[ORi]]
+    ; MIPS32: $v0 = COPY [[ADDu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 65535
+    %2:gprb(s32) = G_ADD %0, %1
+    $v0 = COPY %2(s32)
+    RetRA implicit $v0
+
+...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll

 ; MIPS32-NEXT:    addiu $sp, $sp, 8
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %add = add i128 %b, %a
   ret i128 %add
 }
 
+define i32 @add_imm(i32 %a) {
+; MIPS32-LABEL: add_imm:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $2, $4, 3
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %add = add i32 %a, 3
+  ret i32 %add
+}
+
+define i32 @add_negative_imm(i32 %a) {
+; MIPS32-LABEL: add_negative_imm:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $2, $4, -3
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %add = add i32 %a, -3
+  ret i32 %add
+}
+
+define i32 @add_not_imm32SExt16(i32 %a) {
+; MIPS32-LABEL: add_not_imm32SExt16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    ori $1, $zero, 65535
+; MIPS32-NEXT:    addu $2, $4, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %add = add i32 %a, 65535
+  ret i32 %add
+}
+
 declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
 define void @uadd_with_overflow(i32 %lhs, i32 %rhs, i32* %padd, i1* %pcarry_flag) {
 ; MIPS32-LABEL: uadd_with_overflow:
 ; MIPS32:       # %bb.0:
 ; MIPS32-NEXT:    addu $1, $4, $5
 ; MIPS32-NEXT:    sltu $2, $1, $5
 ; MIPS32-NEXT:    ori $3, $zero, 1
 ; MIPS32-NEXT:    and $2, $2, $3

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll

 ; MIPS32-NEXT:    sw $ra, 28($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    sw $fp, 24($sp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    .cfi_offset 31, -4
 ; MIPS32-NEXT:    .cfi_offset 30, -8
 ; MIPS32-NEXT:    move $fp, $sp
 ; MIPS32-NEXT:    .cfi_def_cfa_register 30
 ; MIPS32-NEXT:    ori $1, $zero, 1
 ; MIPS32-NEXT:    ori $2, $zero, 0
-; MIPS32-NEXT:    addu $3, $5, $1
+; MIPS32-NEXT:    addiu $3, $5, 1
 ; MIPS32-NEXT:    mul $1, $3, $1
-; MIPS32-NEXT:    ori $3, $zero, 7
-; MIPS32-NEXT:    addu $1, $1, $3
+; MIPS32-NEXT:    addiu $1, $1, 7
 ; MIPS32-NEXT:    addiu $3, $zero, 65528
 ; MIPS32-NEXT:    and $1, $1, $3
 ; MIPS32-NEXT:    move $3, $sp
 ; MIPS32-NEXT:    subu $1, $3, $1
 ; MIPS32-NEXT:    move $sp, $1
 ; MIPS32-NEXT:    addiu $sp, $sp, -16
 ; MIPS32-NEXT:    sw $4, 20($fp) # 4-byte Folded Spill
 ; MIPS32-NEXT:    move $4, $1