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Differential D70067

[RISCV][NFC] Add nounwind to LKK test functions
ClosedPublic

Authored by luismarques on Nov 11 2019, 1:01 AM.

Details

Reviewers
asb
lenary
xbolva00
Commits
rG4197a76593a6: [RISCV][NFC] Add nounwind to LKK test functions
Summary

What it says on the tin.

Diff Detail

Event Timeline

luismarques created this revision.Nov 11 2019, 1:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 11 2019, 1:01 AM
Herald added subscribers: llvm-commits, sameer.abuasal, pzheng and 23 others. · View Herald Transcript
xbolva00 accepted this revision.Nov 11 2019, 1:35 AM
This revision is now accepted and ready to land.Nov 11 2019, 1:35 AM
Closed by commit rG4197a76593a6: [RISCV][NFC] Add nounwind to LKK test functions (authored by luismarques). · Explain WhyNov 11 2019, 1:52 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
98 lines
271 lines
68 lines
246 lines

Diff 228651

llvm/test/CodeGen/RISCV/srem-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define i32 @fold_srem_positive_odd(i32 %x) { define i32 @fold_srem_positive_odd(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_positive_odd: ; RV32I-LABEL: fold_srem_positive_odd:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_positive_odd: ; RV32IM-LABEL: fold_srem_positive_odd:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 706409 ; RV32IM-NEXT: lui a1, 706409
; RV32IM-NEXT: addi a1, a1, 389 ; RV32IM-NEXT: addi a1, a1, 389
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: add a1, a1, a0 ; RV32IM-NEXT: add a1, a1, a0
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 6 ; RV32IM-NEXT: srai a1, a1, 6
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_positive_odd: ; RV64I-LABEL: fold_srem_positive_odd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_positive_odd: ; RV64IM-LABEL: fold_srem_positive_odd:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 1045903 ; RV64IM-NEXT: lui a1, 1045903
; RV64IM-NEXT: addiw a1, a1, -733 ; RV64IM-NEXT: addiw a1, a1, -733
; RV64IM-NEXT: slli a1, a1, 15 ; RV64IM-NEXT: slli a1, a1, 15
; RV64IM-NEXT: addi a1, a1, 1035 ; RV64IM-NEXT: addi a1, a1, 1035
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -905 ; RV64IM-NEXT: addi a1, a1, -905
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -1767 ; RV64IM-NEXT: addi a1, a1, -1767
; RV64IM-NEXT: mulh a1, a0, a1 ; RV64IM-NEXT: mulh a1, a0, a1
; RV64IM-NEXT: add a1, a1, a0 ; RV64IM-NEXT: add a1, a1, a0
; RV64IM-NEXT: srli a2, a1, 63 ; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 6 ; RV64IM-NEXT: srai a1, a1, 6
; RV64IM-NEXT: add a1, a1, a2 ; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 95 ; RV64IM-NEXT: addi a2, zero, 95
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, 95 %1 = srem i32 %x, 95
ret i32 %1 ret i32 %1
} }
define i32 @fold_srem_positive_even(i32 %x) { define i32 @fold_srem_positive_even(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_positive_even: ; RV32I-LABEL: fold_srem_positive_even:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, zero, 1060 ; RV32I-NEXT: addi a1, zero, 1060
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_positive_even: ; RV32IM-LABEL: fold_srem_positive_even:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 253241 ; RV32IM-NEXT: lui a1, 253241
; RV32IM-NEXT: addi a1, a1, -15 ; RV32IM-NEXT: addi a1, a1, -15
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8 ; RV32IM-NEXT: srai a1, a1, 8
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, 1060 ; RV32IM-NEXT: addi a2, zero, 1060
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_positive_even: ; RV64I-LABEL: fold_srem_positive_even:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, 1060 ; RV64I-NEXT: addi a1, zero, 1060
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_positive_even: ; RV64IM-LABEL: fold_srem_positive_even:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 506482 ; RV64IM-NEXT: lui a1, 506482
; RV64IM-NEXT: addiw a1, a1, -31 ; RV64IM-NEXT: addiw a1, a1, -31
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, 711 ; RV64IM-NEXT: addi a1, a1, 711
; RV64IM-NEXT: slli a1, a1, 19 ; RV64IM-NEXT: slli a1, a1, 19
; RV64IM-NEXT: addi a1, a1, 1979 ; RV64IM-NEXT: addi a1, a1, 1979
; RV64IM-NEXT: mulh a1, a0, a1 ; RV64IM-NEXT: mulh a1, a0, a1
; RV64IM-NEXT: srli a2, a1, 63 ; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 9 ; RV64IM-NEXT: srai a1, a1, 9
; RV64IM-NEXT: add a1, a1, a2 ; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 1060 ; RV64IM-NEXT: addi a2, zero, 1060
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, 1060 %1 = srem i32 %x, 1060
ret i32 %1 ret i32 %1
} }
define i32 @fold_srem_negative_odd(i32 %x) { define i32 @fold_srem_negative_odd(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_negative_odd: ; RV32I-LABEL: fold_srem_negative_odd:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, zero, -723 ; RV32I-NEXT: addi a1, zero, -723
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_negative_odd: ; RV32IM-LABEL: fold_srem_negative_odd:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 677296 ; RV32IM-NEXT: lui a1, 677296
; RV32IM-NEXT: addi a1, a1, -91 ; RV32IM-NEXT: addi a1, a1, -91
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8 ; RV32IM-NEXT: srai a1, a1, 8
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, -723 ; RV32IM-NEXT: addi a2, zero, -723
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_negative_odd: ; RV64I-LABEL: fold_srem_negative_odd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, zero, -723 ; RV64I-NEXT: addi a1, zero, -723
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_negative_odd: ; RV64IM-LABEL: fold_srem_negative_odd:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 4781 ; RV64IM-NEXT: lui a1, 4781
; RV64IM-NEXT: addiw a1, a1, 2045 ; RV64IM-NEXT: addiw a1, a1, 2045
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, 1371 ; RV64IM-NEXT: addi a1, a1, 1371
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, -11 ; RV64IM-NEXT: addi a1, a1, -11
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -1355 ; RV64IM-NEXT: addi a1, a1, -1355
; RV64IM-NEXT: mulh a1, a0, a1 ; RV64IM-NEXT: mulh a1, a0, a1
; RV64IM-NEXT: sub a1, a1, a0 ; RV64IM-NEXT: sub a1, a1, a0
; RV64IM-NEXT: srli a2, a1, 63 ; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 9 ; RV64IM-NEXT: srai a1, a1, 9
; RV64IM-NEXT: add a1, a1, a2 ; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: addi a2, zero, -723 ; RV64IM-NEXT: addi a2, zero, -723
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, -723 %1 = srem i32 %x, -723
ret i32 %1 ret i32 %1
} }
define i32 @fold_srem_negative_even(i32 %x) { define i32 @fold_srem_negative_even(i32 %x) nounwind {
; RV32I-LABEL: fold_srem_negative_even: ; RV32I-LABEL: fold_srem_negative_even:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: lui a1, 1048570 ; RV32I-NEXT: lui a1, 1048570
; RV32I-NEXT: addi a1, a1, 1595 ; RV32I-NEXT: addi a1, a1, 1595
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_negative_even: ; RV32IM-LABEL: fold_srem_negative_even:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 1036895 ; RV32IM-NEXT: lui a1, 1036895
; RV32IM-NEXT: addi a1, a1, 999 ; RV32IM-NEXT: addi a1, a1, 999
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 8 ; RV32IM-NEXT: srai a1, a1, 8
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: lui a2, 1048570 ; RV32IM-NEXT: lui a2, 1048570
; RV32IM-NEXT: addi a2, a2, 1595 ; RV32IM-NEXT: addi a2, a2, 1595
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_negative_even: ; RV64I-LABEL: fold_srem_negative_even:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: lui a1, 1048570 ; RV64I-NEXT: lui a1, 1048570
; RV64I-NEXT: addiw a1, a1, 1595 ; RV64I-NEXT: addiw a1, a1, 1595
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_negative_even: ; RV64IM-LABEL: fold_srem_negative_even:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a0, a0 ; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: lui a1, 1036895 ; RV64IM-NEXT: lui a1, 1036895
; RV64IM-NEXT: addiw a1, a1, 999 ; RV64IM-NEXT: addiw a1, a1, 999
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, 11 ; RV64IM-NEXT: addi a1, a1, 11
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -523 ; RV64IM-NEXT: addi a1, a1, -523
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -481 ; RV64IM-NEXT: addi a1, a1, -481
; RV64IM-NEXT: mulh a1, a0, a1 ; RV64IM-NEXT: mulh a1, a0, a1
; RV64IM-NEXT: srli a2, a1, 63 ; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 12 ; RV64IM-NEXT: srai a1, a1, 12
; RV64IM-NEXT: add a1, a1, a2 ; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: lui a2, 1048570 ; RV64IM-NEXT: lui a2, 1048570
; RV64IM-NEXT: addiw a2, a2, 1595 ; RV64IM-NEXT: addiw a2, a2, 1595
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, -22981 %1 = srem i32 %x, -22981
ret i32 %1 ret i32 %1
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define i32 @combine_srem_sdiv(i32 %x) { define i32 @combine_srem_sdiv(i32 %x) nounwind {
; RV32I-LABEL: combine_srem_sdiv: ; RV32I-LABEL: combine_srem_sdiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: call __divsi3
; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: add a0, s1, a0
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_srem_sdiv: ; RV32IM-LABEL: combine_srem_sdiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 706409 ; RV32IM-NEXT: lui a1, 706409
; RV32IM-NEXT: addi a1, a1, 389 ; RV32IM-NEXT: addi a1, a1, 389
; RV32IM-NEXT: mulh a1, a0, a1 ; RV32IM-NEXT: mulh a1, a0, a1
; RV32IM-NEXT: add a1, a1, a0 ; RV32IM-NEXT: add a1, a1, a0
; RV32IM-NEXT: srli a2, a1, 31 ; RV32IM-NEXT: srli a2, a1, 31
; RV32IM-NEXT: srai a1, a1, 6 ; RV32IM-NEXT: srai a1, a1, 6
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a2, a1, a2 ; RV32IM-NEXT: mul a2, a1, a2
; RV32IM-NEXT: sub a0, a0, a2 ; RV32IM-NEXT: sub a0, a0, a2
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_srem_sdiv: ; RV64I-LABEL: combine_srem_sdiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp)
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp)
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: sext.w s0, a0 ; RV64I-NEXT: sext.w s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __divdi3 ; RV64I-NEXT: call __divdi3
; RV64I-NEXT: addw a0, s1, a0 ; RV64I-NEXT: addw a0, s1, a0
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp)
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_srem_sdiv: ; RV64IM-LABEL: combine_srem_sdiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0 ; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: lui a2, 1045903 ; RV64IM-NEXT: lui a2, 1045903
; RV64IM-NEXT: addiw a2, a2, -733 ; RV64IM-NEXT: addiw a2, a2, -733
; RV64IM-NEXT: slli a2, a2, 15 ; RV64IM-NEXT: slli a2, a2, 15
; RV64IM-NEXT: addi a2, a2, 1035 ; RV64IM-NEXT: addi a2, a2, 1035
; RV64IM-NEXT: slli a2, a2, 12 ; RV64IM-NEXT: slli a2, a2, 12
; RV64IM-NEXT: addi a2, a2, -905 ; RV64IM-NEXT: addi a2, a2, -905
; RV64IM-NEXT: slli a2, a2, 12 ; RV64IM-NEXT: slli a2, a2, 12
; RV64IM-NEXT: addi a2, a2, -1767 ; RV64IM-NEXT: addi a2, a2, -1767
; RV64IM-NEXT: mulh a2, a1, a2 ; RV64IM-NEXT: mulh a2, a1, a2
; RV64IM-NEXT: add a1, a2, a1 ; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srli a2, a1, 63 ; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 6 ; RV64IM-NEXT: srai a1, a1, 6
; RV64IM-NEXT: add a1, a1, a2 ; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 95 ; RV64IM-NEXT: addi a2, zero, 95
; RV64IM-NEXT: mul a2, a1, a2 ; RV64IM-NEXT: mul a2, a1, a2
; RV64IM-NEXT: sub a0, a0, a2 ; RV64IM-NEXT: sub a0, a0, a2
; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, 95 %1 = srem i32 %x, 95
%2 = sdiv i32 %x, 95 %2 = sdiv i32 %x, 95
%3 = add i32 %1, %2 %3 = add i32 %1, %2
ret i32 %3 ret i32 %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define i32 @dont_fold_srem_power_of_two(i32 %x) { define i32 @dont_fold_srem_power_of_two(i32 %x) nounwind {
; RV32I-LABEL: dont_fold_srem_power_of_two: ; RV32I-LABEL: dont_fold_srem_power_of_two:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 26 ; RV32I-NEXT: srli a1, a1, 26
; RV32I-NEXT: add a1, a0, a1 ; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: andi a1, a1, -64 ; RV32I-NEXT: andi a1, a1, -64
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_power_of_two: ; RV32IM-LABEL: dont_fold_srem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a1, a0, 31 ; RV32IM-NEXT: srai a1, a0, 31
; RV32IM-NEXT: srli a1, a1, 26 ; RV32IM-NEXT: srli a1, a1, 26
; RV32IM-NEXT: add a1, a0, a1 ; RV32IM-NEXT: add a1, a0, a1
; RV32IM-NEXT: andi a1, a1, -64 ; RV32IM-NEXT: andi a1, a1, -64
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_power_of_two: ; RV64I-LABEL: dont_fold_srem_power_of_two:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: srli a1, a1, 57 ; RV64I-NEXT: srli a1, a1, 57
; RV64I-NEXT: andi a1, a1, 63 ; RV64I-NEXT: andi a1, a1, 63
; RV64I-NEXT: add a1, a0, a1 ; RV64I-NEXT: add a1, a0, a1
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 32 ; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: addi a2, a2, -64 ; RV64I-NEXT: addi a2, a2, -64
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: subw a0, a0, a1 ; RV64I-NEXT: subw a0, a0, a1
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_power_of_two: ; RV64IM-LABEL: dont_fold_srem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0 ; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: srli a1, a1, 57 ; RV64IM-NEXT: srli a1, a1, 57
; RV64IM-NEXT: andi a1, a1, 63 ; RV64IM-NEXT: andi a1, a1, 63
; RV64IM-NEXT: add a1, a0, a1 ; RV64IM-NEXT: add a1, a0, a1
; RV64IM-NEXT: addi a2, zero, 1 ; RV64IM-NEXT: addi a2, zero, 1
; RV64IM-NEXT: slli a2, a2, 32 ; RV64IM-NEXT: slli a2, a2, 32
; RV64IM-NEXT: addi a2, a2, -64 ; RV64IM-NEXT: addi a2, a2, -64
; RV64IM-NEXT: and a1, a1, a2 ; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: subw a0, a0, a1 ; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, 64 %1 = srem i32 %x, 64
ret i32 %1 ret i32 %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define i32 @dont_fold_srem_one(i32 %x) { define i32 @dont_fold_srem_one(i32 %x) nounwind {
; CHECK-LABEL: dont_fold_srem_one: ; CHECK-LABEL: dont_fold_srem_one:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mv a0, zero ; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = srem i32 %x, 1 %1 = srem i32 %x, 1
ret i32 %1 ret i32 %1
} }
; Don't fold if the divisor is 2^31. ; Don't fold if the divisor is 2^31.
define i32 @dont_fold_srem_i32_smax(i32 %x) { define i32 @dont_fold_srem_i32_smax(i32 %x) nounwind {
; RV32I-LABEL: dont_fold_srem_i32_smax: ; RV32I-LABEL: dont_fold_srem_i32_smax:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: add a1, a0, a1 ; RV32I-NEXT: add a1, a0, a1
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_i32_smax: ; RV32IM-LABEL: dont_fold_srem_i32_smax:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a1, a0, 31 ; RV32IM-NEXT: srai a1, a0, 31
; RV32IM-NEXT: srli a1, a1, 1 ; RV32IM-NEXT: srli a1, a1, 1
; RV32IM-NEXT: add a1, a0, a1 ; RV32IM-NEXT: add a1, a0, a1
; RV32IM-NEXT: lui a2, 524288 ; RV32IM-NEXT: lui a2, 524288
; RV32IM-NEXT: and a1, a1, a2 ; RV32IM-NEXT: and a1, a1, a2
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_i32_smax: ; RV64I-LABEL: dont_fold_srem_i32_smax:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a1, a0 ; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: srli a1, a1, 32 ; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: addiw a2, a2, -1 ; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: add a1, a0, a1 ; RV64I-NEXT: add a1, a0, a1
; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 31 ; RV64I-NEXT: slli a2, a2, 31
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_i32_smax: ; RV64IM-LABEL: dont_fold_srem_i32_smax:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a0 ; RV64IM-NEXT: sext.w a1, a0
; RV64IM-NEXT: srli a1, a1, 32 ; RV64IM-NEXT: srli a1, a1, 32
; RV64IM-NEXT: lui a2, 524288 ; RV64IM-NEXT: lui a2, 524288
; RV64IM-NEXT: addiw a2, a2, -1 ; RV64IM-NEXT: addiw a2, a2, -1
; RV64IM-NEXT: and a1, a1, a2 ; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: add a1, a0, a1 ; RV64IM-NEXT: add a1, a0, a1
; RV64IM-NEXT: addi a2, zero, 1 ; RV64IM-NEXT: addi a2, zero, 1
; RV64IM-NEXT: slli a2, a2, 31 ; RV64IM-NEXT: slli a2, a2, 31
; RV64IM-NEXT: and a1, a1, a2 ; RV64IM-NEXT: and a1, a1, a2
; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i32 %x, 2147483648 %1 = srem i32 %x, 2147483648
ret i32 %1 ret i32 %1
} }
; Don't fold i64 srem ; Don't fold i64 srem
define i64 @dont_fold_srem_i64(i64 %x) { define i64 @dont_fold_srem_i64(i64 %x) nounwind {
; RV32I-LABEL: dont_fold_srem_i64: ; RV32I-LABEL: dont_fold_srem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a2, zero, 98 ; RV32I-NEXT: addi a2, zero, 98
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __moddi3 ; RV32I-NEXT: call __moddi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_i64: ; RV32IM-LABEL: dont_fold_srem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: .cfi_def_cfa_offset 16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp)
; RV32IM-NEXT: .cfi_offset ra, -4
; RV32IM-NEXT: addi a2, zero, 98 ; RV32IM-NEXT: addi a2, zero, 98
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __moddi3 ; RV32IM-NEXT: call __moddi3
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp)
; RV32IM-NEXT: .cfi_restore ra
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_i64: ; RV64I-LABEL: dont_fold_srem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: addi a1, zero, 98
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM-LABEL: dont_fold_srem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 2675 ; RV64IM-NEXT: lui a1, 2675
; RV64IM-NEXT: addiw a1, a1, -251 ; RV64IM-NEXT: addiw a1, a1, -251
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, 1839 ; RV64IM-NEXT: addi a1, a1, 1839
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, 167 ; RV64IM-NEXT: addi a1, a1, 167
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, 1505 ; RV64IM-NEXT: addi a1, a1, 1505
; RV64IM-NEXT: mulh a1, a0, a1 ; RV64IM-NEXT: mulh a1, a0, a1
; RV64IM-NEXT: srli a2, a1, 63 ; RV64IM-NEXT: srli a2, a1, 63
; RV64IM-NEXT: srai a1, a1, 5 ; RV64IM-NEXT: srai a1, a1, 5
; RV64IM-NEXT: add a1, a1, a2 ; RV64IM-NEXT: add a1, a1, a2
; RV64IM-NEXT: addi a2, zero, 98 ; RV64IM-NEXT: addi a2, zero, 98
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem i64 %x, 98 %1 = srem i64 %x, 98
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) { define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_srem_vec_1: ; RV32I-LABEL: fold_srem_vec_1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s3, 8(a1)
; RV32I-NEXT: lh s0, 4(a1) ; RV32I-NEXT: lh s0, 4(a1)
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
Show All 15 Lines
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_vec_1: ; RV32IM-LABEL: fold_srem_vec_1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a6, 12(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a4, 0(a1)
; RV32IM-NEXT: lh a1, 4(a1) ; RV32IM-NEXT: lh a1, 4(a1)
Show All 34 Lines
; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: add a4, a4, a5
; RV32IM-NEXT: addi a5, zero, -1003 ; RV32IM-NEXT: addi a5, zero, -1003
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a4, a4, a5
; RV32IM-NEXT: sub a4, a6, a4 ; RV32IM-NEXT: sub a4, a6, a4
; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_vec_1: ; RV64I-LABEL: fold_srem_vec_1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: .cfi_def_cfa_offset 64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: .cfi_offset s4, -48
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s3, 16(a1)
; RV64I-NEXT: lh s0, 8(a1) ; RV64I-NEXT: lh s0, 8(a1)
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
Show All 15 Lines
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp)
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_vec_1: ; RV64IM-LABEL: fold_srem_vec_1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a6, 24(a1)
; RV64IM-NEXT: lh a3, 16(a1) ; RV64IM-NEXT: lh a3, 16(a1)
; RV64IM-NEXT: lh a4, 8(a1) ; RV64IM-NEXT: lh a4, 8(a1)
; RV64IM-NEXT: lh a1, 0(a1) ; RV64IM-NEXT: lh a1, 0(a1)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: add a4, a4, a5
; RV64IM-NEXT: addi a5, zero, -1003 ; RV64IM-NEXT: addi a5, zero, -1003
; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a4, a6, a4 ; RV64IM-NEXT: sub a4, a6, a4
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a3, 4(a0) ; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: sh a1, 0(a0) ; RV64IM-NEXT: sh a1, 0(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003> %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_srem_vec_2: ; RV32I-LABEL: fold_srem_vec_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s3, 8(a1)
; RV32I-NEXT: lh s0, 4(a1) ; RV32I-NEXT: lh s0, 4(a1)
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
Show All 15 Lines
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_vec_2: ; RV32IM-LABEL: fold_srem_vec_2:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a6, 12(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a4, 0(a1)
; RV32IM-NEXT: lh a1, 4(a1) ; RV32IM-NEXT: lh a1, 4(a1)
Show All 27 Lines
; RV32IM-NEXT: srli a3, a3, 6 ; RV32IM-NEXT: srli a3, a3, 6
; RV32IM-NEXT: add a3, a3, a4 ; RV32IM-NEXT: add a3, a3, a4
; RV32IM-NEXT: mul a3, a3, a7 ; RV32IM-NEXT: mul a3, a3, a7
; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sub a3, a6, a3
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a3, 6(a0)
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: sh t0, 0(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_vec_2: ; RV64I-LABEL: fold_srem_vec_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: .cfi_def_cfa_offset 64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: .cfi_offset s4, -48
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s3, 16(a1)
; RV64I-NEXT: lh s0, 8(a1) ; RV64I-NEXT: lh s0, 8(a1)
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
Show All 15 Lines
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp)
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_vec_2: ; RV64IM-LABEL: fold_srem_vec_2:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a6, 24(a1)
; RV64IM-NEXT: lh a7, 16(a1) ; RV64IM-NEXT: lh a7, 16(a1)
; RV64IM-NEXT: lh a4, 8(a1) ; RV64IM-NEXT: lh a4, 8(a1)
; RV64IM-NEXT: lh a1, 0(a1) ; RV64IM-NEXT: lh a1, 0(a1)
Show All 33 Lines
; RV64IM-NEXT: srli a4, a4, 6 ; RV64IM-NEXT: srli a4, a4, 6
; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: add a4, a4, a5
; RV64IM-NEXT: mul a3, a4, a3 ; RV64IM-NEXT: mul a3, a4, a3
; RV64IM-NEXT: sub a3, a6, a3 ; RV64IM-NEXT: sub a3, a6, a3
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a2, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh t0, 0(a0) ; RV64IM-NEXT: sh t0, 0(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) { define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind {
; RV32I-LABEL: combine_srem_sdiv: ; RV32I-LABEL: combine_srem_sdiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: .cfi_def_cfa_offset 48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp)
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp)
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp)
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp)
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: .cfi_offset s6, -32
; RV32I-NEXT: .cfi_offset s7, -36
; RV32I-NEXT: .cfi_offset s8, -40
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: lh s2, 0(a1) ; RV32I-NEXT: lh s2, 0(a1)
; RV32I-NEXT: lh s3, 4(a1) ; RV32I-NEXT: lh s3, 4(a1)
; RV32I-NEXT: lh s4, 8(a1) ; RV32I-NEXT: lh s4, 8(a1)
; RV32I-NEXT: lh s1, 12(a1) ; RV32I-NEXT: lh s1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
Show All 39 Lines
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp)
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp)
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp)
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp)
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: .cfi_restore s6
; RV32I-NEXT: .cfi_restore s7
; RV32I-NEXT: .cfi_restore s8
; RV32I-NEXT: .cfi_restore s9
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_srem_sdiv: ; RV32IM-LABEL: combine_srem_sdiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 0(a1) ; RV32IM-NEXT: lh a6, 0(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a4, 12(a1)
; RV32IM-NEXT: lh a1, 8(a1) ; RV32IM-NEXT: lh a1, 8(a1)
Show All 31 Lines
; RV32IM-NEXT: add a4, a5, a4 ; RV32IM-NEXT: add a4, a5, a4
; RV32IM-NEXT: add a1, a3, a1 ; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: add a2, t2, a2 ; RV32IM-NEXT: add a2, t2, a2
; RV32IM-NEXT: add a3, t1, t0 ; RV32IM-NEXT: add a3, t1, t0
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a3, 6(a0)
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a4, 0(a0) ; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_srem_sdiv: ; RV64I-LABEL: combine_srem_sdiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: .cfi_def_cfa_offset 96
; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd ra, 88(sp)
; RV64I-NEXT: sd s0, 80(sp) ; RV64I-NEXT: sd s0, 80(sp)
; RV64I-NEXT: sd s1, 72(sp) ; RV64I-NEXT: sd s1, 72(sp)
; RV64I-NEXT: sd s2, 64(sp) ; RV64I-NEXT: sd s2, 64(sp)
; RV64I-NEXT: sd s3, 56(sp) ; RV64I-NEXT: sd s3, 56(sp)
; RV64I-NEXT: sd s4, 48(sp) ; RV64I-NEXT: sd s4, 48(sp)
; RV64I-NEXT: sd s5, 40(sp) ; RV64I-NEXT: sd s5, 40(sp)
; RV64I-NEXT: sd s6, 32(sp) ; RV64I-NEXT: sd s6, 32(sp)
; RV64I-NEXT: sd s7, 24(sp) ; RV64I-NEXT: sd s7, 24(sp)
; RV64I-NEXT: sd s8, 16(sp) ; RV64I-NEXT: sd s8, 16(sp)
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: .cfi_offset s4, -48
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: .cfi_offset s6, -64
; RV64I-NEXT: .cfi_offset s7, -72
; RV64I-NEXT: .cfi_offset s8, -80
; RV64I-NEXT: .cfi_offset s9, -88
; RV64I-NEXT: lh s2, 0(a1) ; RV64I-NEXT: lh s2, 0(a1)
; RV64I-NEXT: lh s3, 8(a1) ; RV64I-NEXT: lh s3, 8(a1)
; RV64I-NEXT: lh s4, 16(a1) ; RV64I-NEXT: lh s4, 16(a1)
; RV64I-NEXT: lh s1, 24(a1) ; RV64I-NEXT: lh s1, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
Show All 39 Lines
; RV64I-NEXT: ld s6, 32(sp) ; RV64I-NEXT: ld s6, 32(sp)
; RV64I-NEXT: ld s5, 40(sp) ; RV64I-NEXT: ld s5, 40(sp)
; RV64I-NEXT: ld s4, 48(sp) ; RV64I-NEXT: ld s4, 48(sp)
; RV64I-NEXT: ld s3, 56(sp) ; RV64I-NEXT: ld s3, 56(sp)
; RV64I-NEXT: ld s2, 64(sp) ; RV64I-NEXT: ld s2, 64(sp)
; RV64I-NEXT: ld s1, 72(sp) ; RV64I-NEXT: ld s1, 72(sp)
; RV64I-NEXT: ld s0, 80(sp) ; RV64I-NEXT: ld s0, 80(sp)
; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: ld ra, 88(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: .cfi_restore s6
; RV64I-NEXT: .cfi_restore s7
; RV64I-NEXT: .cfi_restore s8
; RV64I-NEXT: .cfi_restore s9
; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_srem_sdiv: ; RV64IM-LABEL: combine_srem_sdiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 0(a1) ; RV64IM-NEXT: lh a6, 0(a1)
; RV64IM-NEXT: lh a7, 8(a1) ; RV64IM-NEXT: lh a7, 8(a1)
; RV64IM-NEXT: lh a4, 16(a1) ; RV64IM-NEXT: lh a4, 16(a1)
; RV64IM-NEXT: lh a1, 24(a1) ; RV64IM-NEXT: lh a1, 24(a1)
Show All 37 Lines
; RV64IM-NEXT: add a2, a5, a2 ; RV64IM-NEXT: add a2, a5, a2
; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a3, a4, a3
; RV64IM-NEXT: add a1, t2, a1 ; RV64IM-NEXT: add a1, t2, a1
; RV64IM-NEXT: add a4, t1, t3 ; RV64IM-NEXT: add a4, t1, t3
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a2, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%3 = add <4 x i16> %1, %2 %3 = add <4 x i16> %1, %2
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_srem_power_of_two: ; RV32I-LABEL: dont_fold_srem_power_of_two:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: lh a0, 12(a1) ; RV32I-NEXT: lh a0, 12(a1)
; RV32I-NEXT: lh a3, 8(a1) ; RV32I-NEXT: lh a3, 8(a1)
; RV32I-NEXT: lh a1, 4(a1) ; RV32I-NEXT: lh a1, 4(a1)
; RV32I-NEXT: srai a4, a2, 31 ; RV32I-NEXT: srai a4, a2, 31
; RV32I-NEXT: srli a4, a4, 26 ; RV32I-NEXT: srli a4, a4, 26
; RV32I-NEXT: add a4, a2, a4 ; RV32I-NEXT: add a4, a2, a4
Show All 19 Lines
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: sh s2, 0(s0) ; RV32I-NEXT: sh s2, 0(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_power_of_two: ; RV32IM-LABEL: dont_fold_srem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 8(a1) ; RV32IM-NEXT: lh a6, 8(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a4, 12(a1)
; RV32IM-NEXT: lh a1, 0(a1) ; RV32IM-NEXT: lh a1, 0(a1)
Show All 25 Lines
; RV32IM-NEXT: add a3, a6, a3 ; RV32IM-NEXT: add a3, a6, a3
; RV32IM-NEXT: addi a4, a5, -8 ; RV32IM-NEXT: addi a4, a5, -8
; RV32IM-NEXT: and a3, a3, a4 ; RV32IM-NEXT: and a3, a3, a4
; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sub a3, a6, a3
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a2, 2(a0)
; RV32IM-NEXT: sh a1, 0(a0) ; RV32IM-NEXT: sh a1, 0(a0)
; RV32IM-NEXT: sh a7, 6(a0) ; RV32IM-NEXT: sh a7, 6(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_power_of_two: ; RV64I-LABEL: dont_fold_srem_power_of_two:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: lh a0, 24(a1) ; RV64I-NEXT: lh a0, 24(a1)
; RV64I-NEXT: lh a3, 16(a1) ; RV64I-NEXT: lh a3, 16(a1)
; RV64I-NEXT: lh a1, 8(a1) ; RV64I-NEXT: lh a1, 8(a1)
; RV64I-NEXT: srai a4, a2, 63 ; RV64I-NEXT: srai a4, a2, 63
; RV64I-NEXT: srli a4, a4, 58 ; RV64I-NEXT: srli a4, a4, 58
; RV64I-NEXT: add a4, a2, a4 ; RV64I-NEXT: add a4, a2, a4
Show All 19 Lines
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: sh s2, 0(s0) ; RV64I-NEXT: sh s2, 0(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_power_of_two: ; RV64IM-LABEL: dont_fold_srem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a6, 16(a1) ; RV64IM-NEXT: lh a6, 16(a1)
; RV64IM-NEXT: lh a3, 8(a1) ; RV64IM-NEXT: lh a3, 8(a1)
; RV64IM-NEXT: lh a4, 0(a1) ; RV64IM-NEXT: lh a4, 0(a1)
; RV64IM-NEXT: lh a1, 24(a1) ; RV64IM-NEXT: lh a1, 24(a1)
Show All 31 Lines
; RV64IM-NEXT: add a3, a6, a3 ; RV64IM-NEXT: add a3, a6, a3
; RV64IM-NEXT: addiw a4, a5, -8 ; RV64IM-NEXT: addiw a4, a5, -8
; RV64IM-NEXT: and a3, a3, a4 ; RV64IM-NEXT: and a3, a3, a4
; RV64IM-NEXT: sub a3, a6, a3 ; RV64IM-NEXT: sub a3, a6, a3
; RV64IM-NEXT: sh a3, 4(a0) ; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: sh a1, 0(a0) ; RV64IM-NEXT: sh a1, 0(a0)
; RV64IM-NEXT: sh a7, 6(a0) ; RV64IM-NEXT: sh a7, 6(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95> %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) { define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_srem_one: ; RV32I-LABEL: dont_fold_srem_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh s1, 8(a1) ; RV32I-NEXT: lh s1, 8(a1)
; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: lh a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 654 ; RV32I-NEXT: addi a1, zero, 654
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: call __modsi3
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
Show All 9 Lines
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_one: ; RV32IM-LABEL: dont_fold_srem_one:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a2, 12(a1) ; RV32IM-NEXT: lh a2, 12(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a1, 8(a1) ; RV32IM-NEXT: lh a1, 8(a1)
; RV32IM-NEXT: lui a4, 820904 ; RV32IM-NEXT: lui a4, 820904
Show All 25 Lines
; RV32IM-NEXT: lui a5, 1 ; RV32IM-NEXT: lui a5, 1
; RV32IM-NEXT: addi a5, a5, 1327 ; RV32IM-NEXT: addi a5, a5, 1327
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a4, a4, a5
; RV32IM-NEXT: sub a2, a2, a4 ; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: sh zero, 0(a0) ; RV32IM-NEXT: sh zero, 0(a0)
; RV32IM-NEXT: sh a2, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a1, 4(a0) ; RV32IM-NEXT: sh a1, 4(a0)
; RV32IM-NEXT: sh a3, 2(a0) ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_one: ; RV64I-LABEL: dont_fold_srem_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh s1, 16(a1) ; RV64I-NEXT: lh s1, 16(a1)
; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: lh a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
Show All 9 Lines
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_one: ; RV64IM-LABEL: dont_fold_srem_one:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 24(a1) ; RV64IM-NEXT: lh a2, 24(a1)
; RV64IM-NEXT: lh a3, 8(a1) ; RV64IM-NEXT: lh a3, 8(a1)
; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lh a1, 16(a1)
; RV64IM-NEXT: lui a4, 1043590 ; RV64IM-NEXT: lui a4, 1043590
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sub a2, a2, a4
; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 6(a0) ; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423> %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^15. ; Don't fold if the divisor is 2^15.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i16_smax: ; RV32I-LABEL: dont_fold_urem_i16_smax:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: lh a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s2, 12(a1)
; RV32I-NEXT: lh a0, 8(a1) ; RV32I-NEXT: lh a0, 8(a1)
; RV32I-NEXT: slli a1, a2, 16 ; RV32I-NEXT: slli a1, a2, 16
; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: srai a1, a1, 31
; RV32I-NEXT: srli a1, a1, 17 ; RV32I-NEXT: srli a1, a1, 17
; RV32I-NEXT: add a1, a2, a1 ; RV32I-NEXT: add a1, a2, a1
Show All 11 Lines
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i16_smax: ; RV32IM-LABEL: dont_fold_urem_i16_smax:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a2, 4(a1) ; RV32IM-NEXT: lh a2, 4(a1)
; RV32IM-NEXT: slli a6, a2, 16 ; RV32IM-NEXT: slli a6, a2, 16
; RV32IM-NEXT: lh a4, 8(a1) ; RV32IM-NEXT: lh a4, 8(a1)
; RV32IM-NEXT: lh a1, 12(a1) ; RV32IM-NEXT: lh a1, 12(a1)
Show All 22 Lines
; RV32IM-NEXT: add a4, a2, a4 ; RV32IM-NEXT: add a4, a2, a4
; RV32IM-NEXT: lui a5, 8 ; RV32IM-NEXT: lui a5, 8
; RV32IM-NEXT: and a4, a4, a5 ; RV32IM-NEXT: and a4, a4, a5
; RV32IM-NEXT: sub a2, a2, a4 ; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: sh zero, 0(a0) ; RV32IM-NEXT: sh zero, 0(a0)
; RV32IM-NEXT: sh a1, 6(a0) ; RV32IM-NEXT: sh a1, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a2, 2(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i16_smax: ; RV64I-LABEL: dont_fold_urem_i16_smax:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: lh a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s2, 24(a1)
; RV64I-NEXT: lh a0, 16(a1) ; RV64I-NEXT: lh a0, 16(a1)
; RV64I-NEXT: slli a1, a2, 48 ; RV64I-NEXT: slli a1, a2, 48
; RV64I-NEXT: srai a1, a1, 63 ; RV64I-NEXT: srai a1, a1, 63
; RV64I-NEXT: srli a1, a1, 49 ; RV64I-NEXT: srli a1, a1, 49
; RV64I-NEXT: add a1, a2, a1 ; RV64I-NEXT: add a1, a2, a1
Show All 11 Lines
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i16_smax: ; RV64IM-LABEL: dont_fold_urem_i16_smax:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 8(a1) ; RV64IM-NEXT: lh a2, 8(a1)
; RV64IM-NEXT: slli a6, a2, 48 ; RV64IM-NEXT: slli a6, a2, 48
; RV64IM-NEXT: lh a4, 24(a1) ; RV64IM-NEXT: lh a4, 24(a1)
; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lh a1, 16(a1)
Show All 34 Lines
; RV64IM-NEXT: add a4, a2, a4 ; RV64IM-NEXT: add a4, a2, a4
; RV64IM-NEXT: lui a5, 8 ; RV64IM-NEXT: lui a5, 8
; RV64IM-NEXT: and a4, a4, a5 ; RV64IM-NEXT: and a4, a4, a5
; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sub a2, a2, a4
; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423> %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 srem. ; Don't fold i64 srem.
define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) { define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind {
; RV32I-LABEL: dont_fold_srem_i64: ; RV32I-LABEL: dont_fold_srem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: .cfi_def_cfa_offset 48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp)
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp)
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp)
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp)
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: .cfi_offset s6, -32
; RV32I-NEXT: .cfi_offset s7, -36
; RV32I-NEXT: .cfi_offset s8, -40
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s2, 24(a1)
; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s3, 28(a1)
; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s4, 16(a1)
; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s5, 20(a1)
; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s6, 8(a1)
; RV32I-NEXT: lw s1, 12(a1) ; RV32I-NEXT: lw s1, 12(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
Show All 38 Lines
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp)
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp)
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp)
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp)
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: .cfi_restore s6
; RV32I-NEXT: .cfi_restore s7
; RV32I-NEXT: .cfi_restore s8
; RV32I-NEXT: .cfi_restore s9
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_i64: ; RV32IM-LABEL: dont_fold_srem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: addi sp, sp, -48
; RV32IM-NEXT: .cfi_def_cfa_offset 48
; RV32IM-NEXT: sw ra, 44(sp) ; RV32IM-NEXT: sw ra, 44(sp)
; RV32IM-NEXT: sw s0, 40(sp) ; RV32IM-NEXT: sw s0, 40(sp)
; RV32IM-NEXT: sw s1, 36(sp) ; RV32IM-NEXT: sw s1, 36(sp)
; RV32IM-NEXT: sw s2, 32(sp) ; RV32IM-NEXT: sw s2, 32(sp)
; RV32IM-NEXT: sw s3, 28(sp) ; RV32IM-NEXT: sw s3, 28(sp)
; RV32IM-NEXT: sw s4, 24(sp) ; RV32IM-NEXT: sw s4, 24(sp)
; RV32IM-NEXT: sw s5, 20(sp) ; RV32IM-NEXT: sw s5, 20(sp)
; RV32IM-NEXT: sw s6, 16(sp) ; RV32IM-NEXT: sw s6, 16(sp)
; RV32IM-NEXT: sw s7, 12(sp) ; RV32IM-NEXT: sw s7, 12(sp)
; RV32IM-NEXT: sw s8, 8(sp) ; RV32IM-NEXT: sw s8, 8(sp)
; RV32IM-NEXT: sw s9, 4(sp) ; RV32IM-NEXT: sw s9, 4(sp)
; RV32IM-NEXT: .cfi_offset ra, -4
; RV32IM-NEXT: .cfi_offset s0, -8
; RV32IM-NEXT: .cfi_offset s1, -12
; RV32IM-NEXT: .cfi_offset s2, -16
; RV32IM-NEXT: .cfi_offset s3, -20
; RV32IM-NEXT: .cfi_offset s4, -24
; RV32IM-NEXT: .cfi_offset s5, -28
; RV32IM-NEXT: .cfi_offset s6, -32
; RV32IM-NEXT: .cfi_offset s7, -36
; RV32IM-NEXT: .cfi_offset s8, -40
; RV32IM-NEXT: .cfi_offset s9, -44
; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s2, 24(a1)
; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s3, 28(a1)
; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s4, 16(a1)
; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s5, 20(a1)
; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s6, 8(a1)
; RV32IM-NEXT: lw s1, 12(a1) ; RV32IM-NEXT: lw s1, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
Show All 38 Lines
; RV32IM-NEXT: lw s6, 16(sp) ; RV32IM-NEXT: lw s6, 16(sp)
; RV32IM-NEXT: lw s5, 20(sp) ; RV32IM-NEXT: lw s5, 20(sp)
; RV32IM-NEXT: lw s4, 24(sp) ; RV32IM-NEXT: lw s4, 24(sp)
; RV32IM-NEXT: lw s3, 28(sp) ; RV32IM-NEXT: lw s3, 28(sp)
; RV32IM-NEXT: lw s2, 32(sp) ; RV32IM-NEXT: lw s2, 32(sp)
; RV32IM-NEXT: lw s1, 36(sp) ; RV32IM-NEXT: lw s1, 36(sp)
; RV32IM-NEXT: lw s0, 40(sp) ; RV32IM-NEXT: lw s0, 40(sp)
; RV32IM-NEXT: lw ra, 44(sp) ; RV32IM-NEXT: lw ra, 44(sp)
; RV32IM-NEXT: .cfi_restore ra
; RV32IM-NEXT: .cfi_restore s0
; RV32IM-NEXT: .cfi_restore s1
; RV32IM-NEXT: .cfi_restore s2
; RV32IM-NEXT: .cfi_restore s3
; RV32IM-NEXT: .cfi_restore s4
; RV32IM-NEXT: .cfi_restore s5
; RV32IM-NEXT: .cfi_restore s6
; RV32IM-NEXT: .cfi_restore s7
; RV32IM-NEXT: .cfi_restore s8
; RV32IM-NEXT: .cfi_restore s9
; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: addi sp, sp, 48
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_i64: ; RV64I-LABEL: dont_fold_srem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s2, 24(a1)
; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld s1, 16(a1)
; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: ld a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3 ; RV64I-NEXT: call __moddi3
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
Show All 9 Lines
; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd a0, 24(s0)
; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s1, 16(s0)
; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: sd s3, 8(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM-LABEL: dont_fold_srem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: ld a2, 24(a1) ; RV64IM-NEXT: ld a2, 24(a1)
; RV64IM-NEXT: ld a3, 8(a1) ; RV64IM-NEXT: ld a3, 8(a1)
; RV64IM-NEXT: ld a1, 16(a1) ; RV64IM-NEXT: ld a1, 16(a1)
; RV64IM-NEXT: lui a4, 1043590 ; RV64IM-NEXT: lui a4, 1043590
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sub a2, a2, a4
; RV64IM-NEXT: sd zero, 0(a0) ; RV64IM-NEXT: sd zero, 0(a0)
; RV64IM-NEXT: sd a2, 24(a0) ; RV64IM-NEXT: sd a2, 24(a0)
; RV64IM-NEXT: sd a3, 8(a0) ; RV64IM-NEXT: sd a3, 8(a0)
; RV64IM-NEXT: sd a1, 16(a0) ; RV64IM-NEXT: sd a1, 16(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/RISCV/urem-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define i32 @fold_urem_positive_odd(i32 %x) { define i32 @fold_urem_positive_odd(i32 %x) nounwind {
; RV32I-LABEL: fold_urem_positive_odd: ; RV32I-LABEL: fold_urem_positive_odd:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_positive_odd: ; RV32IM-LABEL: fold_urem_positive_odd:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 364242 ; RV32IM-NEXT: lui a1, 364242
; RV32IM-NEXT: addi a1, a1, 777 ; RV32IM-NEXT: addi a1, a1, 777
; RV32IM-NEXT: mulhu a1, a0, a1 ; RV32IM-NEXT: mulhu a1, a0, a1
; RV32IM-NEXT: sub a2, a0, a1 ; RV32IM-NEXT: sub a2, a0, a1
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli a2, a2, 1
; RV32IM-NEXT: add a1, a2, a1 ; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: srli a1, a1, 6 ; RV32IM-NEXT: srli a1, a1, 6
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_positive_odd: ; RV64I-LABEL: fold_urem_positive_odd:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_positive_odd: ; RV64IM-LABEL: fold_urem_positive_odd:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1423 ; RV64IM-NEXT: lui a1, 1423
; RV64IM-NEXT: addiw a1, a1, -733 ; RV64IM-NEXT: addiw a1, a1, -733
; RV64IM-NEXT: slli a1, a1, 15 ; RV64IM-NEXT: slli a1, a1, 15
; RV64IM-NEXT: addi a1, a1, 1035 ; RV64IM-NEXT: addi a1, a1, 1035
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, -1811 ; RV64IM-NEXT: addi a1, a1, -1811
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, 561 ; RV64IM-NEXT: addi a1, a1, 561
; RV64IM-NEXT: mulhu a1, a0, a1 ; RV64IM-NEXT: mulhu a1, a0, a1
; RV64IM-NEXT: sub a2, a0, a1 ; RV64IM-NEXT: sub a2, a0, a1
; RV64IM-NEXT: srli a2, a2, 1 ; RV64IM-NEXT: srli a2, a2, 1
; RV64IM-NEXT: add a1, a2, a1 ; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srli a1, a1, 6 ; RV64IM-NEXT: srli a1, a1, 6
; RV64IM-NEXT: addi a2, zero, 95 ; RV64IM-NEXT: addi a2, zero, 95
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem i32 %x, 95 %1 = urem i32 %x, 95
ret i32 %1 ret i32 %1
} }
define i32 @fold_urem_positive_even(i32 %x) { define i32 @fold_urem_positive_even(i32 %x) nounwind {
; RV32I-LABEL: fold_urem_positive_even: ; RV32I-LABEL: fold_urem_positive_even:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a1, zero, 1060 ; RV32I-NEXT: addi a1, zero, 1060
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_positive_even: ; RV32IM-LABEL: fold_urem_positive_even:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 1012964 ; RV32IM-NEXT: lui a1, 1012964
; RV32IM-NEXT: addi a1, a1, -61 ; RV32IM-NEXT: addi a1, a1, -61
; RV32IM-NEXT: mulhu a1, a0, a1 ; RV32IM-NEXT: mulhu a1, a0, a1
; RV32IM-NEXT: srli a1, a1, 10 ; RV32IM-NEXT: srli a1, a1, 10
; RV32IM-NEXT: addi a2, zero, 1060 ; RV32IM-NEXT: addi a2, zero, 1060
; RV32IM-NEXT: mul a1, a1, a2 ; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: sub a0, a0, a1 ; RV32IM-NEXT: sub a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_positive_even: ; RV64I-LABEL: fold_urem_positive_even:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a1, zero, 1060 ; RV64I-NEXT: addi a1, zero, 1060
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_positive_even: ; RV64IM-LABEL: fold_urem_positive_even:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1048020 ; RV64IM-NEXT: lui a1, 1048020
; RV64IM-NEXT: addiw a1, a1, -1793 ; RV64IM-NEXT: addiw a1, a1, -1793
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, 139 ; RV64IM-NEXT: addi a1, a1, 139
; RV64IM-NEXT: slli a1, a1, 14 ; RV64IM-NEXT: slli a1, a1, 14
; RV64IM-NEXT: addi a1, a1, 1793 ; RV64IM-NEXT: addi a1, a1, 1793
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, -139 ; RV64IM-NEXT: addi a1, a1, -139
; RV64IM-NEXT: mulhu a1, a0, a1 ; RV64IM-NEXT: mulhu a1, a0, a1
; RV64IM-NEXT: srli a1, a1, 10 ; RV64IM-NEXT: srli a1, a1, 10
; RV64IM-NEXT: addi a2, zero, 1060 ; RV64IM-NEXT: addi a2, zero, 1060
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem i32 %x, 1060 %1 = urem i32 %x, 1060
ret i32 %1 ret i32 %1
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define i32 @combine_urem_udiv(i32 %x) { define i32 @combine_urem_udiv(i32 %x) nounwind {
; RV32I-LABEL: combine_urem_udiv: ; RV32I-LABEL: combine_urem_udiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp) ; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw s1, 4(sp) ; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: call __udivsi3
; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: add a0, s1, a0
; RV32I-NEXT: lw s1, 4(sp) ; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_urem_udiv: ; RV32IM-LABEL: combine_urem_udiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lui a1, 364242 ; RV32IM-NEXT: lui a1, 364242
; RV32IM-NEXT: addi a1, a1, 777 ; RV32IM-NEXT: addi a1, a1, 777
; RV32IM-NEXT: mulhu a1, a0, a1 ; RV32IM-NEXT: mulhu a1, a0, a1
; RV32IM-NEXT: sub a2, a0, a1 ; RV32IM-NEXT: sub a2, a0, a1
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli a2, a2, 1
; RV32IM-NEXT: add a1, a2, a1 ; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: srli a1, a1, 6 ; RV32IM-NEXT: srli a1, a1, 6
; RV32IM-NEXT: addi a2, zero, 95 ; RV32IM-NEXT: addi a2, zero, 95
; RV32IM-NEXT: mul a2, a1, a2 ; RV32IM-NEXT: mul a2, a1, a2
; RV32IM-NEXT: sub a0, a0, a2 ; RV32IM-NEXT: sub a0, a0, a2
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_urem_udiv: ; RV64I-LABEL: combine_urem_udiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp) ; RV64I-NEXT: sd ra, 24(sp)
; RV64I-NEXT: sd s0, 16(sp) ; RV64I-NEXT: sd s0, 16(sp)
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli s0, a0, 32 ; RV64I-NEXT: srli s0, a0, 32
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __udivdi3 ; RV64I-NEXT: call __udivdi3
; RV64I-NEXT: add a0, s1, a0 ; RV64I-NEXT: add a0, s1, a0
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: ld s0, 16(sp) ; RV64I-NEXT: ld s0, 16(sp)
; RV64I-NEXT: ld ra, 24(sp) ; RV64I-NEXT: ld ra, 24(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_urem_udiv: ; RV64IM-LABEL: combine_urem_udiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 32 ; RV64IM-NEXT: slli a0, a0, 32
; RV64IM-NEXT: srli a0, a0, 32 ; RV64IM-NEXT: srli a0, a0, 32
; RV64IM-NEXT: lui a1, 1423 ; RV64IM-NEXT: lui a1, 1423
; RV64IM-NEXT: addiw a1, a1, -733 ; RV64IM-NEXT: addiw a1, a1, -733
; RV64IM-NEXT: slli a1, a1, 15 ; RV64IM-NEXT: slli a1, a1, 15
; RV64IM-NEXT: addi a1, a1, 1035 ; RV64IM-NEXT: addi a1, a1, 1035
; RV64IM-NEXT: slli a1, a1, 13 ; RV64IM-NEXT: slli a1, a1, 13
; RV64IM-NEXT: addi a1, a1, -1811 ; RV64IM-NEXT: addi a1, a1, -1811
; RV64IM-NEXT: slli a1, a1, 12 ; RV64IM-NEXT: slli a1, a1, 12
; RV64IM-NEXT: addi a1, a1, 561 ; RV64IM-NEXT: addi a1, a1, 561
; RV64IM-NEXT: mulhu a1, a0, a1 ; RV64IM-NEXT: mulhu a1, a0, a1
; RV64IM-NEXT: sub a2, a0, a1 ; RV64IM-NEXT: sub a2, a0, a1
; RV64IM-NEXT: srli a2, a2, 1 ; RV64IM-NEXT: srli a2, a2, 1
; RV64IM-NEXT: add a1, a2, a1 ; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: srli a1, a1, 6 ; RV64IM-NEXT: srli a1, a1, 6
; RV64IM-NEXT: addi a2, zero, 95 ; RV64IM-NEXT: addi a2, zero, 95
; RV64IM-NEXT: mul a2, a1, a2 ; RV64IM-NEXT: mul a2, a1, a2
; RV64IM-NEXT: sub a0, a0, a2 ; RV64IM-NEXT: sub a0, a0, a2
; RV64IM-NEXT: add a0, a0, a1 ; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem i32 %x, 95 %1 = urem i32 %x, 95
%2 = udiv i32 %x, 95 %2 = udiv i32 %x, 95
%3 = add i32 %1, %2 %3 = add i32 %1, %2
ret i32 %3 ret i32 %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define i32 @dont_fold_urem_power_of_two(i32 %x) { define i32 @dont_fold_urem_power_of_two(i32 %x) nounwind {
; CHECK-LABEL: dont_fold_urem_power_of_two: ; CHECK-LABEL: dont_fold_urem_power_of_two:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: andi a0, a0, 63 ; CHECK-NEXT: andi a0, a0, 63
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem i32 %x, 64 %1 = urem i32 %x, 64
ret i32 %1 ret i32 %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define i32 @dont_fold_urem_one(i32 %x) { define i32 @dont_fold_urem_one(i32 %x) nounwind {
; CHECK-LABEL: dont_fold_urem_one: ; CHECK-LABEL: dont_fold_urem_one:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mv a0, zero ; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem i32 %x, 1 %1 = urem i32 %x, 1
ret i32 %1 ret i32 %1
} }
; Don't fold if the divisor is 2^32. ; Don't fold if the divisor is 2^32.
define i32 @dont_fold_urem_i32_umax(i32 %x) { define i32 @dont_fold_urem_i32_umax(i32 %x) nounwind {
; CHECK-LABEL: dont_fold_urem_i32_umax: ; CHECK-LABEL: dont_fold_urem_i32_umax:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem i32 %x, 4294967296 %1 = urem i32 %x, 4294967296
ret i32 %1 ret i32 %1
} }
; Don't fold i64 urem ; Don't fold i64 urem
define i64 @dont_fold_urem_i64(i64 %x) { define i64 @dont_fold_urem_i64(i64 %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i64: ; RV32I-LABEL: dont_fold_urem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: addi a2, zero, 98 ; RV32I-NEXT: addi a2, zero, 98
; RV32I-NEXT: mv a3, zero ; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __umoddi3 ; RV32I-NEXT: call __umoddi3
; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i64: ; RV32IM-LABEL: dont_fold_urem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: .cfi_def_cfa_offset 16
; RV32IM-NEXT: sw ra, 12(sp) ; RV32IM-NEXT: sw ra, 12(sp)
; RV32IM-NEXT: .cfi_offset ra, -4
; RV32IM-NEXT: addi a2, zero, 98 ; RV32IM-NEXT: addi a2, zero, 98
; RV32IM-NEXT: mv a3, zero ; RV32IM-NEXT: mv a3, zero
; RV32IM-NEXT: call __umoddi3 ; RV32IM-NEXT: call __umoddi3
; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: lw ra, 12(sp)
; RV32IM-NEXT: .cfi_restore ra
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i64: ; RV64I-LABEL: dont_fold_urem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: addi a1, zero, 98 ; RV64I-NEXT: addi a1, zero, 98
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i64: ; RV64IM-LABEL: dont_fold_urem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: srli a1, a0, 1 ; RV64IM-NEXT: srli a1, a0, 1
; RV64IM-NEXT: lui a2, 2675 ; RV64IM-NEXT: lui a2, 2675
; RV64IM-NEXT: addiw a2, a2, -251 ; RV64IM-NEXT: addiw a2, a2, -251
; RV64IM-NEXT: slli a2, a2, 13 ; RV64IM-NEXT: slli a2, a2, 13
; RV64IM-NEXT: addi a2, a2, 1839 ; RV64IM-NEXT: addi a2, a2, 1839
; RV64IM-NEXT: slli a2, a2, 13 ; RV64IM-NEXT: slli a2, a2, 13
; RV64IM-NEXT: addi a2, a2, 167 ; RV64IM-NEXT: addi a2, a2, 167
; RV64IM-NEXT: slli a2, a2, 13 ; RV64IM-NEXT: slli a2, a2, 13
; RV64IM-NEXT: addi a2, a2, 1505 ; RV64IM-NEXT: addi a2, a2, 1505
; RV64IM-NEXT: mulhu a1, a1, a2 ; RV64IM-NEXT: mulhu a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 4 ; RV64IM-NEXT: srli a1, a1, 4
; RV64IM-NEXT: addi a2, zero, 98 ; RV64IM-NEXT: addi a2, zero, 98
; RV64IM-NEXT: mul a1, a1, a2 ; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: sub a0, a0, a1 ; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem i64 %x, 98 %1 = urem i64 %x, 98
ret i64 %1 ret i64 %1
} }

llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s ; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s
define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_urem_vec_1: ; RV32I-LABEL: fold_urem_vec_1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s2, 12(a1)
; RV32I-NEXT: lhu s3, 8(a1) ; RV32I-NEXT: lhu s3, 8(a1)
; RV32I-NEXT: lhu s0, 4(a1) ; RV32I-NEXT: lhu s0, 4(a1)
; RV32I-NEXT: lhu a2, 0(a1) ; RV32I-NEXT: lhu a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
Show All 15 Lines
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_vec_1: ; RV32IM-LABEL: fold_urem_vec_1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 12(a1) ; RV32IM-NEXT: lhu a6, 12(a1)
; RV32IM-NEXT: lhu a3, 8(a1) ; RV32IM-NEXT: lhu a3, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1) ; RV32IM-NEXT: lhu a4, 0(a1)
; RV32IM-NEXT: lhu a1, 4(a1) ; RV32IM-NEXT: lhu a1, 4(a1)
Show All 28 Lines
; RV32IM-NEXT: srli a4, a4, 8 ; RV32IM-NEXT: srli a4, a4, 8
; RV32IM-NEXT: addi a5, zero, 1003 ; RV32IM-NEXT: addi a5, zero, 1003
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a4, a4, a5
; RV32IM-NEXT: sub a4, a6, a4 ; RV32IM-NEXT: sub a4, a6, a4
; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_vec_1: ; RV64I-LABEL: fold_urem_vec_1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: .cfi_def_cfa_offset 64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: .cfi_offset s4, -48
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s2, 24(a1)
; RV64I-NEXT: lhu s3, 16(a1) ; RV64I-NEXT: lhu s3, 16(a1)
; RV64I-NEXT: lhu s0, 8(a1) ; RV64I-NEXT: lhu s0, 8(a1)
; RV64I-NEXT: lhu a2, 0(a1) ; RV64I-NEXT: lhu a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
Show All 15 Lines
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp)
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_vec_1: ; RV64IM-LABEL: fold_urem_vec_1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 24(a1) ; RV64IM-NEXT: lhu a6, 24(a1)
; RV64IM-NEXT: lhu a3, 16(a1) ; RV64IM-NEXT: lhu a3, 16(a1)
; RV64IM-NEXT: lhu a4, 8(a1) ; RV64IM-NEXT: lhu a4, 8(a1)
; RV64IM-NEXT: lhu a1, 0(a1) ; RV64IM-NEXT: lhu a1, 0(a1)
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; RV64IM-NEXT: srli a4, a4, 7 ; RV64IM-NEXT: srli a4, a4, 7
; RV64IM-NEXT: addi a5, zero, 1003 ; RV64IM-NEXT: addi a5, zero, 1003
; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a4, a6, a4 ; RV64IM-NEXT: sub a4, a6, a4
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a3, 4(a0) ; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a2, 2(a0) ; RV64IM-NEXT: sh a2, 2(a0)
; RV64IM-NEXT: sh a1, 0(a0) ; RV64IM-NEXT: sh a1, 0(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003> %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_urem_vec_2: ; RV32I-LABEL: fold_urem_vec_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp) ; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp) ; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s2, 12(a1)
; RV32I-NEXT: lhu s3, 8(a1) ; RV32I-NEXT: lhu s3, 8(a1)
; RV32I-NEXT: lhu s0, 4(a1) ; RV32I-NEXT: lhu s0, 4(a1)
; RV32I-NEXT: lhu a2, 0(a1) ; RV32I-NEXT: lhu a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
Show All 15 Lines
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s1)
; RV32I-NEXT: lw s5, 4(sp) ; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp) ; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_vec_2: ; RV32IM-LABEL: fold_urem_vec_2:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 12(a1) ; RV32IM-NEXT: lhu a6, 12(a1)
; RV32IM-NEXT: lhu a7, 8(a1) ; RV32IM-NEXT: lhu a7, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1) ; RV32IM-NEXT: lhu a4, 0(a1)
; RV32IM-NEXT: lhu a1, 4(a1) ; RV32IM-NEXT: lhu a1, 4(a1)
Show All 27 Lines
; RV32IM-NEXT: add a4, a5, a4 ; RV32IM-NEXT: add a4, a5, a4
; RV32IM-NEXT: srli a4, a4, 6 ; RV32IM-NEXT: srli a4, a4, 6
; RV32IM-NEXT: mul a3, a4, a3 ; RV32IM-NEXT: mul a3, a4, a3
; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sub a3, a6, a3
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a3, 6(a0)
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: sh t0, 0(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_vec_2: ; RV64I-LABEL: fold_urem_vec_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: .cfi_def_cfa_offset 64
; RV64I-NEXT: sd ra, 56(sp) ; RV64I-NEXT: sd ra, 56(sp)
; RV64I-NEXT: sd s0, 48(sp) ; RV64I-NEXT: sd s0, 48(sp)
; RV64I-NEXT: sd s1, 40(sp) ; RV64I-NEXT: sd s1, 40(sp)
; RV64I-NEXT: sd s2, 32(sp) ; RV64I-NEXT: sd s2, 32(sp)
; RV64I-NEXT: sd s3, 24(sp) ; RV64I-NEXT: sd s3, 24(sp)
; RV64I-NEXT: sd s4, 16(sp) ; RV64I-NEXT: sd s4, 16(sp)
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: .cfi_offset s4, -48
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s2, 24(a1)
; RV64I-NEXT: lhu s3, 16(a1) ; RV64I-NEXT: lhu s3, 16(a1)
; RV64I-NEXT: lhu s0, 8(a1) ; RV64I-NEXT: lhu s0, 8(a1)
; RV64I-NEXT: lhu a2, 0(a1) ; RV64I-NEXT: lhu a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
Show All 15 Lines
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s1)
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp)
; RV64I-NEXT: ld s4, 16(sp) ; RV64I-NEXT: ld s4, 16(sp)
; RV64I-NEXT: ld s3, 24(sp) ; RV64I-NEXT: ld s3, 24(sp)
; RV64I-NEXT: ld s2, 32(sp) ; RV64I-NEXT: ld s2, 32(sp)
; RV64I-NEXT: ld s1, 40(sp) ; RV64I-NEXT: ld s1, 40(sp)
; RV64I-NEXT: ld s0, 48(sp) ; RV64I-NEXT: ld s0, 48(sp)
; RV64I-NEXT: ld ra, 56(sp) ; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: addi sp, sp, 64 ; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_vec_2: ; RV64IM-LABEL: fold_urem_vec_2:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 24(a1) ; RV64IM-NEXT: lhu a6, 24(a1)
; RV64IM-NEXT: lhu a7, 16(a1) ; RV64IM-NEXT: lhu a7, 16(a1)
; RV64IM-NEXT: lhu a4, 8(a1) ; RV64IM-NEXT: lhu a4, 8(a1)
; RV64IM-NEXT: lhu a1, 0(a1) ; RV64IM-NEXT: lhu a1, 0(a1)
Show All 33 Lines
; RV64IM-NEXT: add a4, a5, a4 ; RV64IM-NEXT: add a4, a5, a4
; RV64IM-NEXT: srli a4, a4, 6 ; RV64IM-NEXT: srli a4, a4, 6
; RV64IM-NEXT: mul a3, a4, a3 ; RV64IM-NEXT: mul a3, a4, a3
; RV64IM-NEXT: sub a3, a6, a3 ; RV64IM-NEXT: sub a3, a6, a3
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a2, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh t0, 0(a0) ; RV64IM-NEXT: sh t0, 0(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) { define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind {
; RV32I-LABEL: combine_urem_udiv: ; RV32I-LABEL: combine_urem_udiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: .cfi_def_cfa_offset 48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp)
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp)
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp)
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp)
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: .cfi_offset s6, -32
; RV32I-NEXT: .cfi_offset s7, -36
; RV32I-NEXT: .cfi_offset s8, -40
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: lhu s2, 0(a1) ; RV32I-NEXT: lhu s2, 0(a1)
; RV32I-NEXT: lhu s3, 4(a1) ; RV32I-NEXT: lhu s3, 4(a1)
; RV32I-NEXT: lhu s4, 8(a1) ; RV32I-NEXT: lhu s4, 8(a1)
; RV32I-NEXT: lhu s1, 12(a1) ; RV32I-NEXT: lhu s1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
Show All 39 Lines
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp)
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp)
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp)
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp)
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: .cfi_restore s6
; RV32I-NEXT: .cfi_restore s7
; RV32I-NEXT: .cfi_restore s8
; RV32I-NEXT: .cfi_restore s9
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_urem_udiv: ; RV32IM-LABEL: combine_urem_udiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 0(a1) ; RV32IM-NEXT: lhu a6, 0(a1)
; RV32IM-NEXT: lhu a7, 4(a1) ; RV32IM-NEXT: lhu a7, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1) ; RV32IM-NEXT: lhu a4, 12(a1)
; RV32IM-NEXT: lhu a1, 8(a1) ; RV32IM-NEXT: lhu a1, 8(a1)
Show All 31 Lines
; RV32IM-NEXT: add a2, a5, a2 ; RV32IM-NEXT: add a2, a5, a2
; RV32IM-NEXT: add a1, a4, a1 ; RV32IM-NEXT: add a1, a4, a1
; RV32IM-NEXT: add a3, t2, a3 ; RV32IM-NEXT: add a3, t2, a3
; RV32IM-NEXT: add a4, t1, t3 ; RV32IM-NEXT: add a4, t1, t3
; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_urem_udiv: ; RV64I-LABEL: combine_urem_udiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: .cfi_def_cfa_offset 96
; RV64I-NEXT: sd ra, 88(sp) ; RV64I-NEXT: sd ra, 88(sp)
; RV64I-NEXT: sd s0, 80(sp) ; RV64I-NEXT: sd s0, 80(sp)
; RV64I-NEXT: sd s1, 72(sp) ; RV64I-NEXT: sd s1, 72(sp)
; RV64I-NEXT: sd s2, 64(sp) ; RV64I-NEXT: sd s2, 64(sp)
; RV64I-NEXT: sd s3, 56(sp) ; RV64I-NEXT: sd s3, 56(sp)
; RV64I-NEXT: sd s4, 48(sp) ; RV64I-NEXT: sd s4, 48(sp)
; RV64I-NEXT: sd s5, 40(sp) ; RV64I-NEXT: sd s5, 40(sp)
; RV64I-NEXT: sd s6, 32(sp) ; RV64I-NEXT: sd s6, 32(sp)
; RV64I-NEXT: sd s7, 24(sp) ; RV64I-NEXT: sd s7, 24(sp)
; RV64I-NEXT: sd s8, 16(sp) ; RV64I-NEXT: sd s8, 16(sp)
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: .cfi_offset s4, -48
; RV64I-NEXT: .cfi_offset s5, -56
; RV64I-NEXT: .cfi_offset s6, -64
; RV64I-NEXT: .cfi_offset s7, -72
; RV64I-NEXT: .cfi_offset s8, -80
; RV64I-NEXT: .cfi_offset s9, -88
; RV64I-NEXT: lhu s2, 0(a1) ; RV64I-NEXT: lhu s2, 0(a1)
; RV64I-NEXT: lhu s3, 8(a1) ; RV64I-NEXT: lhu s3, 8(a1)
; RV64I-NEXT: lhu s4, 16(a1) ; RV64I-NEXT: lhu s4, 16(a1)
; RV64I-NEXT: lhu s1, 24(a1) ; RV64I-NEXT: lhu s1, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
Show All 39 Lines
; RV64I-NEXT: ld s6, 32(sp) ; RV64I-NEXT: ld s6, 32(sp)
; RV64I-NEXT: ld s5, 40(sp) ; RV64I-NEXT: ld s5, 40(sp)
; RV64I-NEXT: ld s4, 48(sp) ; RV64I-NEXT: ld s4, 48(sp)
; RV64I-NEXT: ld s3, 56(sp) ; RV64I-NEXT: ld s3, 56(sp)
; RV64I-NEXT: ld s2, 64(sp) ; RV64I-NEXT: ld s2, 64(sp)
; RV64I-NEXT: ld s1, 72(sp) ; RV64I-NEXT: ld s1, 72(sp)
; RV64I-NEXT: ld s0, 80(sp) ; RV64I-NEXT: ld s0, 80(sp)
; RV64I-NEXT: ld ra, 88(sp) ; RV64I-NEXT: ld ra, 88(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: .cfi_restore s4
; RV64I-NEXT: .cfi_restore s5
; RV64I-NEXT: .cfi_restore s6
; RV64I-NEXT: .cfi_restore s7
; RV64I-NEXT: .cfi_restore s8
; RV64I-NEXT: .cfi_restore s9
; RV64I-NEXT: addi sp, sp, 96 ; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_urem_udiv: ; RV64IM-LABEL: combine_urem_udiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 0(a1) ; RV64IM-NEXT: lhu a6, 0(a1)
; RV64IM-NEXT: lhu a7, 8(a1) ; RV64IM-NEXT: lhu a7, 8(a1)
; RV64IM-NEXT: lhu a4, 16(a1) ; RV64IM-NEXT: lhu a4, 16(a1)
; RV64IM-NEXT: lhu a1, 24(a1) ; RV64IM-NEXT: lhu a1, 24(a1)
Show All 37 Lines
; RV64IM-NEXT: add a2, a5, a2 ; RV64IM-NEXT: add a2, a5, a2
; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a3, a4, a3
; RV64IM-NEXT: add a1, t2, a1 ; RV64IM-NEXT: add a1, t2, a1
; RV64IM-NEXT: add a4, t1, t3 ; RV64IM-NEXT: add a4, t1, t3
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a2, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%3 = add <4 x i16> %1, %2 %3 = add <4 x i16> %1, %2
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_power_of_two: ; RV32I-LABEL: dont_fold_urem_power_of_two:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: lhu s2, 8(a1) ; RV32I-NEXT: lhu s2, 8(a1)
; RV32I-NEXT: lhu s3, 4(a1) ; RV32I-NEXT: lhu s3, 4(a1)
; RV32I-NEXT: lhu s1, 0(a1) ; RV32I-NEXT: lhu s1, 0(a1)
; RV32I-NEXT: lhu a2, 12(a1) ; RV32I-NEXT: lhu a2, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 95 ; RV32I-NEXT: addi a1, zero, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: andi a1, s1, 63 ; RV32I-NEXT: andi a1, s1, 63
; RV32I-NEXT: andi a2, s3, 31 ; RV32I-NEXT: andi a2, s3, 31
; RV32I-NEXT: andi a3, s2, 7 ; RV32I-NEXT: andi a3, s2, 7
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh a3, 4(s0) ; RV32I-NEXT: sh a3, 4(s0)
; RV32I-NEXT: sh a2, 2(s0) ; RV32I-NEXT: sh a2, 2(s0)
; RV32I-NEXT: sh a1, 0(s0) ; RV32I-NEXT: sh a1, 0(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_power_of_two: ; RV32IM-LABEL: dont_fold_urem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 8(a1) ; RV32IM-NEXT: lhu a6, 8(a1)
; RV32IM-NEXT: lhu a3, 4(a1) ; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1) ; RV32IM-NEXT: lhu a4, 12(a1)
; RV32IM-NEXT: lhu a1, 0(a1) ; RV32IM-NEXT: lhu a1, 0(a1)
Show All 9 Lines
; RV32IM-NEXT: sub a2, a4, a2 ; RV32IM-NEXT: sub a2, a4, a2
; RV32IM-NEXT: andi a1, a1, 63 ; RV32IM-NEXT: andi a1, a1, 63
; RV32IM-NEXT: andi a3, a3, 31 ; RV32IM-NEXT: andi a3, a3, 31
; RV32IM-NEXT: andi a4, a6, 7 ; RV32IM-NEXT: andi a4, a6, 7
; RV32IM-NEXT: sh a4, 4(a0) ; RV32IM-NEXT: sh a4, 4(a0)
; RV32IM-NEXT: sh a3, 2(a0) ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: sh a1, 0(a0) ; RV32IM-NEXT: sh a1, 0(a0)
; RV32IM-NEXT: sh a2, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_power_of_two: ; RV64I-LABEL: dont_fold_urem_power_of_two:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: lhu s2, 16(a1) ; RV64I-NEXT: lhu s2, 16(a1)
; RV64I-NEXT: lhu s3, 8(a1) ; RV64I-NEXT: lhu s3, 8(a1)
; RV64I-NEXT: lhu s1, 0(a1) ; RV64I-NEXT: lhu s1, 0(a1)
; RV64I-NEXT: lhu a2, 24(a1) ; RV64I-NEXT: lhu a2, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 95 ; RV64I-NEXT: addi a1, zero, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: andi a1, s1, 63 ; RV64I-NEXT: andi a1, s1, 63
; RV64I-NEXT: andi a2, s3, 31 ; RV64I-NEXT: andi a2, s3, 31
; RV64I-NEXT: andi a3, s2, 7 ; RV64I-NEXT: andi a3, s2, 7
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh a3, 4(s0) ; RV64I-NEXT: sh a3, 4(s0)
; RV64I-NEXT: sh a2, 2(s0) ; RV64I-NEXT: sh a2, 2(s0)
; RV64I-NEXT: sh a1, 0(s0) ; RV64I-NEXT: sh a1, 0(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_power_of_two: ; RV64IM-LABEL: dont_fold_urem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a6, 16(a1) ; RV64IM-NEXT: lhu a6, 16(a1)
; RV64IM-NEXT: lhu a3, 8(a1) ; RV64IM-NEXT: lhu a3, 8(a1)
; RV64IM-NEXT: lhu a4, 0(a1) ; RV64IM-NEXT: lhu a4, 0(a1)
; RV64IM-NEXT: lhu a1, 24(a1) ; RV64IM-NEXT: lhu a1, 24(a1)
Show All 15 Lines
; RV64IM-NEXT: sub a1, a1, a2 ; RV64IM-NEXT: sub a1, a1, a2
; RV64IM-NEXT: andi a2, a4, 63 ; RV64IM-NEXT: andi a2, a4, 63
; RV64IM-NEXT: andi a3, a3, 31 ; RV64IM-NEXT: andi a3, a3, 31
; RV64IM-NEXT: andi a4, a6, 7 ; RV64IM-NEXT: andi a4, a6, 7
; RV64IM-NEXT: sh a4, 4(a0) ; RV64IM-NEXT: sh a4, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a2, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: sh a1, 6(a0) ; RV64IM-NEXT: sh a1, 6(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95> %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_one: ; RV32I-LABEL: dont_fold_urem_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: .cfi_def_cfa_offset 32
; RV32I-NEXT: sw ra, 28(sp) ; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp) ; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp) ; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp) ; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp) ; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s2, 12(a1)
; RV32I-NEXT: lhu s1, 8(a1) ; RV32I-NEXT: lhu s1, 8(a1)
; RV32I-NEXT: lhu a2, 4(a1) ; RV32I-NEXT: lhu a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, zero, 654 ; RV32I-NEXT: addi a1, zero, 654
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
Show All 9 Lines
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw s3, 12(sp) ; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp) ; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp) ; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp) ; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_one: ; RV32IM-LABEL: dont_fold_urem_one:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a2, 4(a1) ; RV32IM-NEXT: lhu a2, 4(a1)
; RV32IM-NEXT: lhu a3, 12(a1) ; RV32IM-NEXT: lhu a3, 12(a1)
; RV32IM-NEXT: lhu a1, 8(a1) ; RV32IM-NEXT: lhu a1, 8(a1)
; RV32IM-NEXT: srli a4, a2, 1 ; RV32IM-NEXT: srli a4, a2, 1
Show All 18 Lines
; RV32IM-NEXT: lui a5, 1 ; RV32IM-NEXT: lui a5, 1
; RV32IM-NEXT: addi a5, a5, 1327 ; RV32IM-NEXT: addi a5, a5, 1327
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a4, a4, a5
; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: sub a3, a3, a4
; RV32IM-NEXT: sh zero, 0(a0) ; RV32IM-NEXT: sh zero, 0(a0)
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a3, 6(a0)
; RV32IM-NEXT: sh a1, 4(a0) ; RV32IM-NEXT: sh a1, 4(a0)
; RV32IM-NEXT: sh a2, 2(a0) ; RV32IM-NEXT: sh a2, 2(a0)
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_one: ; RV64I-LABEL: dont_fold_urem_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s2, 24(a1)
; RV64I-NEXT: lhu s1, 16(a1) ; RV64I-NEXT: lhu s1, 16(a1)
; RV64I-NEXT: lhu a2, 8(a1) ; RV64I-NEXT: lhu a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
Show All 9 Lines
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_one: ; RV64IM-LABEL: dont_fold_urem_one:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 24(a1) ; RV64IM-NEXT: lhu a2, 24(a1)
; RV64IM-NEXT: lhu a3, 8(a1) ; RV64IM-NEXT: lhu a3, 8(a1)
; RV64IM-NEXT: lhu a1, 16(a1) ; RV64IM-NEXT: lhu a1, 16(a1)
; RV64IM-NEXT: lui a4, 3206 ; RV64IM-NEXT: lui a4, 3206
Show All 39 Lines
; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sub a2, a2, a4
; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 6(a0) ; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a1, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423> %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^16. ; Don't fold if the divisor is 2^16.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; CHECK-LABEL: dont_fold_urem_i16_smax: ; CHECK-LABEL: dont_fold_urem_i16_smax:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423> %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold i64 urem. ; Don't fold i64 urem.
define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) { define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i64: ; RV32I-LABEL: dont_fold_urem_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: .cfi_def_cfa_offset 48
; RV32I-NEXT: sw ra, 44(sp) ; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw s0, 40(sp) ; RV32I-NEXT: sw s0, 40(sp)
; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw s1, 36(sp)
; RV32I-NEXT: sw s2, 32(sp) ; RV32I-NEXT: sw s2, 32(sp)
; RV32I-NEXT: sw s3, 28(sp) ; RV32I-NEXT: sw s3, 28(sp)
; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw s4, 24(sp)
; RV32I-NEXT: sw s5, 20(sp) ; RV32I-NEXT: sw s5, 20(sp)
; RV32I-NEXT: sw s6, 16(sp) ; RV32I-NEXT: sw s6, 16(sp)
; RV32I-NEXT: sw s7, 12(sp) ; RV32I-NEXT: sw s7, 12(sp)
; RV32I-NEXT: sw s8, 8(sp) ; RV32I-NEXT: sw s8, 8(sp)
; RV32I-NEXT: sw s9, 4(sp) ; RV32I-NEXT: sw s9, 4(sp)
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_offset s2, -16
; RV32I-NEXT: .cfi_offset s3, -20
; RV32I-NEXT: .cfi_offset s4, -24
; RV32I-NEXT: .cfi_offset s5, -28
; RV32I-NEXT: .cfi_offset s6, -32
; RV32I-NEXT: .cfi_offset s7, -36
; RV32I-NEXT: .cfi_offset s8, -40
; RV32I-NEXT: .cfi_offset s9, -44
; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s2, 24(a1)
; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s3, 28(a1)
; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s4, 16(a1)
; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s5, 20(a1)
; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s6, 8(a1)
; RV32I-NEXT: lw s1, 12(a1) ; RV32I-NEXT: lw s1, 12(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
Show All 38 Lines
; RV32I-NEXT: lw s6, 16(sp) ; RV32I-NEXT: lw s6, 16(sp)
; RV32I-NEXT: lw s5, 20(sp) ; RV32I-NEXT: lw s5, 20(sp)
; RV32I-NEXT: lw s4, 24(sp) ; RV32I-NEXT: lw s4, 24(sp)
; RV32I-NEXT: lw s3, 28(sp) ; RV32I-NEXT: lw s3, 28(sp)
; RV32I-NEXT: lw s2, 32(sp) ; RV32I-NEXT: lw s2, 32(sp)
; RV32I-NEXT: lw s1, 36(sp) ; RV32I-NEXT: lw s1, 36(sp)
; RV32I-NEXT: lw s0, 40(sp) ; RV32I-NEXT: lw s0, 40(sp)
; RV32I-NEXT: lw ra, 44(sp) ; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: .cfi_restore ra
; RV32I-NEXT: .cfi_restore s0
; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: .cfi_restore s2
; RV32I-NEXT: .cfi_restore s3
; RV32I-NEXT: .cfi_restore s4
; RV32I-NEXT: .cfi_restore s5
; RV32I-NEXT: .cfi_restore s6
; RV32I-NEXT: .cfi_restore s7
; RV32I-NEXT: .cfi_restore s8
; RV32I-NEXT: .cfi_restore s9
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i64: ; RV32IM-LABEL: dont_fold_urem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: addi sp, sp, -48
; RV32IM-NEXT: .cfi_def_cfa_offset 48
; RV32IM-NEXT: sw ra, 44(sp) ; RV32IM-NEXT: sw ra, 44(sp)
; RV32IM-NEXT: sw s0, 40(sp) ; RV32IM-NEXT: sw s0, 40(sp)
; RV32IM-NEXT: sw s1, 36(sp) ; RV32IM-NEXT: sw s1, 36(sp)
; RV32IM-NEXT: sw s2, 32(sp) ; RV32IM-NEXT: sw s2, 32(sp)
; RV32IM-NEXT: sw s3, 28(sp) ; RV32IM-NEXT: sw s3, 28(sp)
; RV32IM-NEXT: sw s4, 24(sp) ; RV32IM-NEXT: sw s4, 24(sp)
; RV32IM-NEXT: sw s5, 20(sp) ; RV32IM-NEXT: sw s5, 20(sp)
; RV32IM-NEXT: sw s6, 16(sp) ; RV32IM-NEXT: sw s6, 16(sp)
; RV32IM-NEXT: sw s7, 12(sp) ; RV32IM-NEXT: sw s7, 12(sp)
; RV32IM-NEXT: sw s8, 8(sp) ; RV32IM-NEXT: sw s8, 8(sp)
; RV32IM-NEXT: sw s9, 4(sp) ; RV32IM-NEXT: sw s9, 4(sp)
; RV32IM-NEXT: .cfi_offset ra, -4
; RV32IM-NEXT: .cfi_offset s0, -8
; RV32IM-NEXT: .cfi_offset s1, -12
; RV32IM-NEXT: .cfi_offset s2, -16
; RV32IM-NEXT: .cfi_offset s3, -20
; RV32IM-NEXT: .cfi_offset s4, -24
; RV32IM-NEXT: .cfi_offset s5, -28
; RV32IM-NEXT: .cfi_offset s6, -32
; RV32IM-NEXT: .cfi_offset s7, -36
; RV32IM-NEXT: .cfi_offset s8, -40
; RV32IM-NEXT: .cfi_offset s9, -44
; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s2, 24(a1)
; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s3, 28(a1)
; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s4, 16(a1)
; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s5, 20(a1)
; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s6, 8(a1)
; RV32IM-NEXT: lw s1, 12(a1) ; RV32IM-NEXT: lw s1, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
Show All 38 Lines
; RV32IM-NEXT: lw s6, 16(sp) ; RV32IM-NEXT: lw s6, 16(sp)
; RV32IM-NEXT: lw s5, 20(sp) ; RV32IM-NEXT: lw s5, 20(sp)
; RV32IM-NEXT: lw s4, 24(sp) ; RV32IM-NEXT: lw s4, 24(sp)
; RV32IM-NEXT: lw s3, 28(sp) ; RV32IM-NEXT: lw s3, 28(sp)
; RV32IM-NEXT: lw s2, 32(sp) ; RV32IM-NEXT: lw s2, 32(sp)
; RV32IM-NEXT: lw s1, 36(sp) ; RV32IM-NEXT: lw s1, 36(sp)
; RV32IM-NEXT: lw s0, 40(sp) ; RV32IM-NEXT: lw s0, 40(sp)
; RV32IM-NEXT: lw ra, 44(sp) ; RV32IM-NEXT: lw ra, 44(sp)
; RV32IM-NEXT: .cfi_restore ra
; RV32IM-NEXT: .cfi_restore s0
; RV32IM-NEXT: .cfi_restore s1
; RV32IM-NEXT: .cfi_restore s2
; RV32IM-NEXT: .cfi_restore s3
; RV32IM-NEXT: .cfi_restore s4
; RV32IM-NEXT: .cfi_restore s5
; RV32IM-NEXT: .cfi_restore s6
; RV32IM-NEXT: .cfi_restore s7
; RV32IM-NEXT: .cfi_restore s8
; RV32IM-NEXT: .cfi_restore s9
; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: addi sp, sp, 48
; RV32IM-NEXT: .cfi_def_cfa_offset 0
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i64: ; RV64I-LABEL: dont_fold_urem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: .cfi_def_cfa_offset 48
; RV64I-NEXT: sd ra, 40(sp) ; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: sd s0, 32(sp) ; RV64I-NEXT: sd s0, 32(sp)
; RV64I-NEXT: sd s1, 24(sp) ; RV64I-NEXT: sd s1, 24(sp)
; RV64I-NEXT: sd s2, 16(sp) ; RV64I-NEXT: sd s2, 16(sp)
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_offset s2, -32
; RV64I-NEXT: .cfi_offset s3, -40
; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s2, 24(a1)
; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld s1, 16(a1)
; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: ld a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, zero, 654 ; RV64I-NEXT: addi a1, zero, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3 ; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
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; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd a0, 24(s0)
; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s1, 16(s0)
; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: sd s3, 8(s0)
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: ld s2, 16(sp) ; RV64I-NEXT: ld s2, 16(sp)
; RV64I-NEXT: ld s1, 24(sp) ; RV64I-NEXT: ld s1, 24(sp)
; RV64I-NEXT: ld s0, 32(sp) ; RV64I-NEXT: ld s0, 32(sp)
; RV64I-NEXT: ld ra, 40(sp) ; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: .cfi_restore ra
; RV64I-NEXT: .cfi_restore s0
; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: .cfi_restore s2
; RV64I-NEXT: .cfi_restore s3
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i64: ; RV64IM-LABEL: dont_fold_urem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: ld a2, 24(a1) ; RV64IM-NEXT: ld a2, 24(a1)
; RV64IM-NEXT: ld a3, 8(a1) ; RV64IM-NEXT: ld a3, 8(a1)
; RV64IM-NEXT: ld a1, 16(a1) ; RV64IM-NEXT: ld a1, 16(a1)
; RV64IM-NEXT: lui a4, 3206 ; RV64IM-NEXT: lui a4, 3206
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; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a4, a4, a5 ; RV64IM-NEXT: mul a4, a4, a5
; RV64IM-NEXT: sub a2, a2, a4 ; RV64IM-NEXT: sub a2, a2, a4
; RV64IM-NEXT: sd zero, 0(a0) ; RV64IM-NEXT: sd zero, 0(a0)
; RV64IM-NEXT: sd a2, 24(a0) ; RV64IM-NEXT: sd a2, 24(a0)
; RV64IM-NEXT: sd a3, 8(a0) ; RV64IM-NEXT: sd a3, 8(a0)
; RV64IM-NEXT: sd a1, 16(a0) ; RV64IM-NEXT: sd a1, 16(a0)
; RV64IM-NEXT: .cfi_def_cfa_offset 0
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }