[TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (3) (baseline tests)

[joanlluch]

Summary

This is baseline tests for D69326

Incorporates a command line flag for the MSP430 and adds a test cases to help showing the effects of applying D69326

More details and motivation for this patch in D69326

[spatel]

LGTM

[joanlluch]

Hi @spatel, @asl
Thanks for reviewing this. I'm getting some trouble at committing to the upstream repo in the way I would like. I asked for help here first, but then I thought it was better to use llvm-dev instead to avoid clutter here. So this is an edit removing my previous comment. Thanks again

[spatel]

In D69975#1738400, @joanlluch wrote:

Hi @spatel, @asl
Thanks for reviewing this. I'm getting some trouble at committing to the upstream repo in the way I would like. I asked for help here first, but then I thought it was better to use llvm-dev instead to avoid clutter here. So this is an edit removing my previous comment. Thanks again

Posting the question to llvm-dev was the correct choice. It may be off-topic for this patch, but let me link it here for reference since the original comment went to the lists/email from here:
http://lists.llvm.org/pipermail/llvm-dev/2019-November/136610.html
(I don't know the answer myself, so hopefully someone else can tell us.)

[joanlluch]

This is now commited to the github repo
https://github.com/llvm/llvm-project/commit/fe0763d28a572f72007637c7bd097bc19cbb58fc

llvm/lib/Target/MSP430/MSP430ISelLowering.h

public:
     /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
     /// necessarily apply to truncate instructions. e.g. on msp430, all
     /// instructions that define 8-bit values implicit zero-extend the result
     /// out to 16 bits.
     bool isZExtFree(Type *Ty1, Type *Ty2) const override;
     bool isZExtFree(EVT VT1, EVT VT2) const override;
     bool isZExtFree(SDValue Val, EVT VT2) const override;
 
+    bool isLegalICmpImmediate(int64_t) const override;
     unsigned getShiftAmountThreshold(EVT VT) const override;
 
     MachineBasicBlock *
     EmitInstrWithCustomInserter(MachineInstr &MI,
                                 MachineBasicBlock *BB) const override;
     MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
                                       MachineBasicBlock *BB) const;
 

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "msp430-lower"
 
+static cl::opt<bool>MSP430NoLegalImmediate(
+  "msp430-no-legal-immediate", cl::Hidden,
+  cl::desc("Enable non legal immediates (for testing purposes only)"),
+  cl::init(false));
+
 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
                                            const MSP430Subtarget &STI)
     : TargetLowering(TM) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
   addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
 
default:
     llvm_unreachable("unimplemented operand");
   }
 }
 
 // Set transforms into shift amounts above 2 as not profitable
 unsigned MSP430TargetLowering::getShiftAmountThreshold(EVT VT) const {
   return 2;
 }
+
+// Implemented to verify test case assertions in
+// tests/codegen/msp430/shift-amount-threshold-b.ll
+bool MSP430TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
+  if (MSP430NoLegalImmediate)
+    return Immed >= -32 && Immed < 32;
+  return TargetLowering::isLegalICmpImmediate(Immed);
+}
+
 //===----------------------------------------------------------------------===//
 //                       MSP430 Inline Assembly Support
 //===----------------------------------------------------------------------===//
 
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 TargetLowering::ConstraintType
 MSP430TargetLowering::getConstraintType(StringRef Constraint) const {

llvm/test/CodeGen/MSP430/shift-amount-threshold-b.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=msp430-- -msp430-no-legal-immediate=true < %s | FileCheck %s
+
+; Test case for the following transformation in TargetLowering::SimplifySetCC
+; (X & -256) == 256 -> (X >> 8) == 1
+define i16 @testSimplifySetCC_2(i16 %x) {
+; CHECK-LABEL: testSimplifySetCC_2:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    clrc
+; CHECK-NEXT:    rrc r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    cmp #1, r12
+; CHECK-NEXT:    mov r2, r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    and #1, r12
+; CHECK-NEXT:    ret
+entry:
+  %and = and i16 %x, -64
+  %cmp = icmp eq i16 %and, 64
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}
+
+; Test case for the following transformation in TargetLowering::SimplifySetCC
+; X >  0x0ffffffff -> (X >> 32) >= 1
+define i16 @testSimplifySetCC_3(i16 %x) {
+; CHECK-LABEL: testSimplifySetCC_3:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    clrc
+; CHECK-NEXT:    rrc r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    tst r12
+; CHECK-NEXT:    mov r2, r13
+; CHECK-NEXT:    rra r13
+; CHECK-NEXT:    mov #1, r12
+; CHECK-NEXT:    bic r13, r12
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp ugt i16 %x, 63
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}
+
+; Test case for the following transformation in TargetLowering::SimplifySetCC
+; X <  0x100000000 -> (X >> 32) <  1
+define i16 @testSimplifySetCC_4(i16 %x) {
+; CHECK-LABEL: testSimplifySetCC_4:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    clrc
+; CHECK-NEXT:    rrc r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    tst r12
+; CHECK-NEXT:    mov r2, r12
+; CHECK-NEXT:    rra r12
+; CHECK-NEXT:    and #1, r12
+; CHECK-NEXT:    ret
+entry:
+  %cmp = icmp ult i16 %x, 64
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}