[arm] Add core definition for armv8l and armv7l

[omjavaid]

Summary

This patch adds core definitions in lldb ArchSpecs for armv8l and armv7l cores. There is also fix where while merging target and paltform triple we were updating core and triple which results in new triple with unknown environment and vendor. This fixes issues where lldb has a triple created after parsing elf header and another from the platform and we should be using consolidated information from both sides.

On Linux systems running on armv8 we are returned armv8l in case we are running 32bit sysroot on 64bit kernel (l for little endian).

Similarly for armv8 hardware running 32bit kernel and 32bit sysroot we are returned armv7l. This is quite common when we run 32 bit arm using docker container.

Also clang return target triple=armv8l-unknown-linux-gnueabihf

[labath]

Everything except the CoreUpdated part LGTM. The CoreUpdated part could use another look from someone more familiar with what exactly that code was trying to achieve. And a test... I'd consider breaking that off into a separate patch.

lldb/packages/Python/lldbsuite/test/make/Makefile.rules

242

Whitespace issues? If the file uses spaces/tabs inconsistently, feel free to reformat in in a separate NFC patch.

[omjavaid]

I have updated the patch as suggested and will move out the triple fix and whitespace issue in separate patches. Committing remaining changes shortly.

lldb/include/lldb/Utility/ArchSpec.h

enum Core {
     eCore_arm_armv4,
     eCore_arm_armv4t,
     eCore_arm_armv5,
     eCore_arm_armv5e,
     eCore_arm_armv5t,
     eCore_arm_armv6,
     eCore_arm_armv6m,
     eCore_arm_armv7,
+    eCore_arm_armv7l,
     eCore_arm_armv7f,
     eCore_arm_armv7s,
     eCore_arm_armv7k,
     eCore_arm_armv7m,
     eCore_arm_armv7em,
     eCore_arm_xscale,
 
     eCore_thumb,
     eCore_thumbv4t,
     eCore_thumbv5,
     eCore_thumbv5e,
     eCore_thumbv6,
     eCore_thumbv6m,
     eCore_thumbv7,
     eCore_thumbv7s,
     eCore_thumbv7k,
     eCore_thumbv7f,
     eCore_thumbv7m,
     eCore_thumbv7em,
     eCore_arm_arm64,
     eCore_arm_armv8,
+    eCore_arm_armv8l,
     eCore_arm_arm64_32,
     eCore_arm_aarch64,
 
     eCore_mips32,
     eCore_mips32r2,
     eCore_mips32r3,
     eCore_mips32r5,
     eCore_mips32r6,

lldb/packages/Python/lldbsuite/test/lldbplatformutil.py

 import lldbsuite.test.lldbplatform as lldbplatform
 
 
 def check_first_register_readable(test_case):
     arch = test_case.getArchitecture()
 
     if arch in ['x86_64', 'i386']:
         test_case.expect("register read eax", substrs=['eax = 0x'])
-    elif arch in ['arm', 'armv7', 'armv7k']:
+    elif arch in ['arm', 'armv7', 'armv7k', 'armv8l', 'armv7l']:
         test_case.expect("register read r0", substrs=['r0 = 0x'])
     elif arch in ['aarch64', 'arm64', 'arm64e', 'arm64_32']:
         test_case.expect("register read x0", substrs=['x0 = 0x'])
     elif re.match("mips", arch):
         test_case.expect("register read zero", substrs=['zero = 0x'])
     elif arch in ['s390x']:
         test_case.expect("register read r0", substrs=['r0 = 0x'])
     elif arch in ['powerpc64le']:

lldb/packages/Python/lldbsuite/test/make/Makefile.rules

else
   endif
   ifeq "$(ARCH)" "powerpc64le"
     override ARCH := $(subst powerpc64le,64,$(ARCH))
   endif
   ifeq "$(ARCH)" "aarch64"
     override ARCH :=
     override ARCHFLAG :=
   endif
-  ifeq "$(ARCH)" "arm"
+  ifeq "$(findstring arm,$(ARCH))" "arm"
     override ARCH :=
     override ARCHFLAG :=
   endif
   ifeq "$(ARCH)" "s390x"
     override ARCH :=
     override ARCHFLAG :=
   endif
   ifeq "$(findstring mips,$(ARCH))" "mips"

lldb/source/Utility/ArchSpec.cpp

static const CoreDefinition g_core_definitions[] = {
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
      "armv5t"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
      "armv6"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
      "armv6m"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
      "armv7"},
+    {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
+     "armv7l"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
      "armv7f"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
      "armv7s"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
      "armv7k"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
      "armv7m"},
static const CoreDefinition g_core_definitions[] = {
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
      "thumbv7m"},
     {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
      "thumbv7em"},
     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
      ArchSpec::eCore_arm_arm64, "arm64"},
     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
      ArchSpec::eCore_arm_armv8, "armv8"},
+    {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm,
+      ArchSpec::eCore_arm_armv8l, "armv8l"},
     {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
       ArchSpec::eCore_arm_arm64_32, "arm64_32"},
     {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
      ArchSpec::eCore_arm_aarch64, "aarch64"},
 
     // mips32, mips32r2, mips32r3, mips32r5, mips32r6
     {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
      "mips"},
if (!enforce_exact_match) {
         return true;
       try_inverse = true;
     }
     break;
 
   case ArchSpec::eCore_arm_armv7f:
   case ArchSpec::eCore_arm_armv7k:
   case ArchSpec::eCore_arm_armv7s:
+  case ArchSpec::eCore_arm_armv7l:
+  case ArchSpec::eCore_arm_armv8l:
     if (!enforce_exact_match) {
       if (core2 == ArchSpec::eCore_arm_generic)
         return true;
       if (core2 == ArchSpec::eCore_arm_armv7)
         return true;
       try_inverse = false;
     }
     break;