[AMDGPU][MC] Corrected src0 for v_movrelsd_b32 and v_movrelsd_2_b32

[dp]

Summary

These opcodes should not accept SGPRs as src0, only VGPRs are legal.

See https://bugs.llvm.org/show_bug.cgi?id=40903

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/VOP1Instructions.td

def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> {
   let HasExtSDWA = 0;
   let HasExtSDWA9 = 0;
 }
 
 // Special case because there are no true output operands.  Hack vdst
 // to be a src operand. The custom inserter must add a tied implicit
 // def and use of the super register since there seems to be no way to
 // add an implicit def of a virtual register in tablegen.
-def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> {
+class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
   let Src0RC32 = VOPDstOperand<VGPR_32>;
   let Src0RC64 = VOPDstOperand<VGPR_32>;
 
   let Outs = (outs);
-  let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0);
-  let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0);
+  let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
+  let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
   let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0,
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
   let InsDPP16 = !con(InsDPP, (ins FI:$fi));
 
   let InsSDWA = (ins Src0RC32:$vdst, Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
                      clampmod:$clamp, omod:$omod, dst_sel:$dst_sel, dst_unused:$dst_unused,
                      src0_sel:$src0_sel);
class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
   let HasExtDPP = 0;
   let HasExtSDWA = 0;
   let HasExtSDWA9 = 0;
 
   let HasDst = 0;
   let EmitDst = 1; // force vdst emission
 }
 
+def VOP_MOVRELD : VOP_MOVREL<VSrc_b32>;
+def VOP_MOVRELSD : VOP_MOVREL<VRegSrc_32>;
+
 let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
 // v_movreld_b32 is a special case because the destination output
  // register is really a source. It isn't actually read (but may be
  // written), and is only to provide the base register to start
  // indexing from. Tablegen seems to not let you define an implicit
  // virtual register output for the super register being written into,
  // so this must have an implicit def of the register added to it.
 defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
 defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>;
-defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
+defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;
 } // End Uses = [M0, EXEC]
 
 defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>;
 
 let SubtargetPredicate = isGFX6GFX7 in {
   let SchedRW = [WriteQuarterRate32] in {
     defm V_LOG_CLAMP_F32 :
       VOP1Inst<"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>;

 let SubtargetPredicate = isGFX9Only in {
   defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
 } // End SubtargetPredicate = isGFX9Only
 
 let SubtargetPredicate = isGFX10Plus in {
   defm V_PIPEFLUSH        : VOP1Inst<"v_pipeflush", VOP_NONE>;
 
   let Uses = [M0] in {
-    // FIXME-GFX10: Should V_MOVRELSD_2_B32 be VOP_NO_EXT?
     defm V_MOVRELSD_2_B32 :
-      VOP1Inst<"v_movrelsd_2_b32", VOP_NO_EXT<VOP_I32_I32>>;
+      VOP1Inst<"v_movrelsd_2_b32", VOP_MOVRELSD>;
 
     def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {
       let Constraints = "$vdst = $src1, $vdst1 = $src0";
       let DisableEncoding = "$vdst1,$src1";
       let SchedRW = [Write64Bit, Write64Bit];
     }
   } // End Uses = [M0]
 } // End SubtargetPredicate = isGFX10Plus

llvm/test/MC/AMDGPU/gfx10_asm_all.s

 // GFX10: encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
 
 v_movrelsd_b32_e64 v255, v1
 // GFX10: encoding: [0xff,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
 
 v_movrelsd_b32_e64 v5, v255
 // GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
 
+v_movrelsd_b32 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
 v_movrelsd_2_b32 v5, v1
 // GFX10: encoding: [0x01,0x91,0x0a,0x7e]
 
 v_movrelsd_2_b32 v255, v1
 // GFX10: encoding: [0x01,0x91,0xfe,0x7f]
 
 v_movrelsd_2_b32 v5, v255
 // GFX10: encoding: [0xff,0x91,0x0a,0x7e]
 
 v_movrelsd_2_b32_e64 v5, v1
 // GFX10: encoding: [0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
 
 v_movrelsd_2_b32_e64 v255, v1
 // GFX10: encoding: [0xff,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
 
 v_movrelsd_2_b32_e64 v5, v255
 // GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
 
+v_movrelsd_2_b32 v5, s1
+// GFX10-ERR: error: invalid operand for instruction
+
 v_cvt_f16_u16_e32 v5, v1
 // GFX10: encoding: [0x01,0xa1,0x0a,0x7e]
 
 v_cvt_f16_u16_e32 v255, v1
 // GFX10: encoding: [0x01,0xa1,0xfe,0x7f]
 
 v_cvt_f16_u16_e32 v5, v255
 // GFX10: encoding: [0xff,0xa1,0x0a,0x7e]

llvm/test/MC/AMDGPU/vop1.s

 // SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
 // VI:   v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
 v_movrels_b32_e32 v1, v2
 
 // SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
 // VI:   v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
 v_movrelsd_b32_e32 v1, v2
 
+// NOSICI: error: invalid operand for instruction
+// NOVI: error: invalid operand for instruction
+v_movrelsd_b32_e32 v1, s2
+
 // NOSI: error: instruction not supported on this GPU
 // NOSI: v_log_legacy_f32 v1, v2
 // CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]
 // VI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x99,0x02,0x7e]
 v_log_legacy_f32 v1, v2
 
 // NOSI: error: instruction not supported on this GPU
 // NOSI: v_exp_legacy_f32 v1, v2