[WebAssembly] Handle multiple loads of splatted loads

[tlively]

Summary

Fixes an ISel failure when a splatted load is used more than once. The
failure was due to the hacks we were doing in ISel lowering to
preserve the original load as the operand of a LOAD_SPLAT node. The
fix is to properly lower the splatted use of the load to a separate
LOAD_SPLAT node.

[aheejin]

LGTM. It's interesting that we can use MemIntrinsicNode for this purpose even if it's not an intrinsic...
(I guess we can also use MachineSDNode because we are effectively doing isel before we reach tablegen, but given that we've used it only in WebAssemblyISelDAGToDAG.cpp and we do most custom SIMD lowering in WebAssemblyISelLowering.cpp, this looks like a good trick.)

llvm/lib/Target/WebAssembly/WebAssemblyISD.def

 HANDLE_NODETYPE(WrapperPIC)
 HANDLE_NODETYPE(BR_IF)
 HANDLE_NODETYPE(BR_TABLE)
 HANDLE_NODETYPE(SHUFFLE)
 HANDLE_NODETYPE(SWIZZLE)
 HANDLE_NODETYPE(VEC_SHL)
 HANDLE_NODETYPE(VEC_SHR_S)
 HANDLE_NODETYPE(VEC_SHR_U)
-HANDLE_NODETYPE(LOAD_SPLAT)
 HANDLE_NODETYPE(THROW)
 HANDLE_NODETYPE(MEMORY_COPY)
 HANDLE_NODETYPE(MEMORY_FILL)
 
-// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
+// Memory intrinsics
+HANDLE_MEM_NODETYPE(LOAD_SPLAT)

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h

 
 namespace llvm {
 
 namespace WebAssemblyISD {
 
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
 #define HANDLE_NODETYPE(NODE) NODE,
+#define HANDLE_MEM_NODETYPE(NODE)
 #include "WebAssemblyISD.def"
+  FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE,
 #undef HANDLE_NODETYPE
+#undef HANDLE_MEM_NODETYPE
+#define HANDLE_NODETYPE(NODE)
+#define HANDLE_MEM_NODETYPE(NODE) NODE,
+#include "WebAssemblyISD.def"
+#undef HANDLE_NODETYPE
+#undef HANDLE_MEM_NODETYPE
 };
 
 } // end namespace WebAssemblyISD
 
 class WebAssemblySubtarget;
 class WebAssemblyTargetMachine;
 
 class WebAssemblyTargetLowering final : public TargetLowering {

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

case WebAssembly::FP_TO_UINT_I64_F64:
     llvm_unreachable("Unexpected instruction to emit with custom inserter");
   }
 }
 
 const char *
 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
   case WebAssemblyISD::FIRST_NUMBER:
+  case WebAssemblyISD::FIRST_MEM_OPCODE:
     break;
 #define HANDLE_NODETYPE(NODE)                                                  \
   case WebAssemblyISD::NODE:                                                   \
     return "WebAssemblyISD::" #NODE;
+#define HANDLE_MEM_NODETYPE(NODE) HANDLE_NODETYPE(NODE)
 #include "WebAssemblyISD.def"
+#undef HANDLE_MEM_NODETYPE
 #undef HANDLE_NODETYPE
   }
   return nullptr;
 }
 
 std::pair<unsigned, const TargetRegisterClass *>
 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
     const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
if (Subtarget->hasUnimplementedSIMD128()) {
     }
   }
   if (!Result) {
     // Use a splat, but possibly a load_splat
     LoadSDNode *SplattedLoad;
     if (Subtarget->hasUnimplementedSIMD128() &&
         (SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) &&
         SplattedLoad->getMemoryVT() == VecT.getVectorElementType()) {
-      Result = DAG.getNode(WebAssemblyISD::LOAD_SPLAT, DL, VecT, SplatValue);
+      Result = DAG.getMemIntrinsicNode(
+          WebAssemblyISD::LOAD_SPLAT, DL, DAG.getVTList({VecT}),
+          {SplattedLoad->getChain(), SplattedLoad->getBasePtr(),
+           SplattedLoad->getOffset()},
+          SplattedLoad->getMemoryVT(), SplattedLoad->getMemOperand());
     } else {
       Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
     }
     IsLaneConstructed = [&](size_t _, const SDValue &Lane) {
       return Lane == SplatValue;
     };
   }
 

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            vec#".load_splat\t$off$p2align", simdop>;
 }
 
 defm "" : SIMDLoadSplat<"v8x16", 194>;
 defm "" : SIMDLoadSplat<"v16x8", 195>;
 defm "" : SIMDLoadSplat<"v32x4", 196>;
 defm "" : SIMDLoadSplat<"v64x2", 197>;
 
-def wasm_load_splat_t : SDTypeProfile<1, 1, []>;
-def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t>;
-
-foreach args = [["v16i8", "i32", "extloadi8"], ["v8i16", "i32", "extloadi16"],
-                ["v4i32", "i32", "load"], ["v2i64", "i64", "load"],
-                ["v4f32", "f32", "load"], ["v2f64", "f64", "load"]] in
-def load_splat_#args[0] :
-  PatFrag<(ops node:$addr), (wasm_load_splat
-            (!cast<ValueType>(args[1]) (!cast<PatFrag>(args[2]) node:$addr)))>;
+def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
+def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t,
+                             [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
 
 let Predicates = [HasUnimplementedSIMD128] in
 foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
                 ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
 def : LoadPatNoOffset<!cast<ValueType>(args[0]),
-                      !cast<PatFrag>("load_splat_"#args[0]),
+                      load_splat,
                       !cast<NI>("LOAD_SPLAT_"#args[1])>;
 def : LoadPatImmOff<!cast<ValueType>(args[0]),
-                    !cast<PatFrag>("load_splat_"#args[0]),
+                    load_splat,
                     regPlusImm,
                     !cast<NI>("LOAD_SPLAT_"#args[1])>;
 def : LoadPatImmOff<!cast<ValueType>(args[0]),
-                    !cast<PatFrag>("load_splat_"#args[0]),
+                    load_splat,
                     or_is_add,
                     !cast<NI>("LOAD_SPLAT_"#args[1])>;
 def : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
-                        !cast<PatFrag>("load_splat_"#args[0]),
+                        load_splat,
                         !cast<NI>("LOAD_SPLAT_"#args[1])>;
 def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
-                               !cast<PatFrag>("load_splat_"#args[0]),
+                               load_splat,
                                !cast<NI>("LOAD_SPLAT_"#args[1])>;
 }
 
 // Load and extend
 multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
   let mayLoad = 1, UseNamedOperandTable = 1,
       Predicates = [HasUnimplementedSIMD128] in {
   defm LOAD_EXTEND_S_#vec_t :

llvm/test/CodeGen/WebAssembly/simd-load-splat.ll

+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s
+
+; Regression test for an ISel failure when a splatted load had more
+; than one use. The main tests for load_splat are in simd-offset.ll.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: load_splat:
+; CHECK-NEXT: .functype load_splat (i32, i32) -> (i32)
+; CHECK-NEXT: i32.load8_u $[[E:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v8x16.load_splat $push[[V:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.store 0($1), $pop[[V]]{{$}}
+; CHECK-NEXT: return $[[E]]{{$}}
+define i8 @load_splat(i8* %p, <16 x i8>* %out) {
+  %e = load i8, i8* %p
+  %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
+  %v2 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> zeroinitializer
+  store <16 x i8> %v2, <16 x i8>* %out
+  ret i8 %e
+}