Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required)

[vpykhtin]

Summary

This happened to v_cndmask_b32_e64, see the test.

[dstuttard]

LGTM

[dstuttard]

Maybe put [AMDGPU] into the subject line of the commit message

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
         Fail = true;
         break;
       }
       DPPInst.add(*Src1);
       ++NumOperands;
     }
 
     if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {
-      if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
+      if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
+          !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
         LLVM_DEBUG(dbgs() << "  failed: src2 is illegal\n");
         Fail = true;
         break;
       }
       DPPInst.add(*Src2);
     }
 
     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

 name: dpp64_add64_first_combined
 tracksRegLiveness: true
 body: |
   bb.0:
     %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec
     %4:vgpr_32 = V_ADD_I32_e32 %2.sub0, undef %3:vgpr_32, implicit-def $vcc, implicit $exec
     %5:vgpr_32, dead %6:sreg_64_xexec = V_ADDC_U32_e64 1, %2.sub1, undef $vcc, 0, implicit $exec
 ...
+
+# GCN-LABEL: name: dont_combine_cndmask_with_src2
+# GCN: %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec
+name: dont_combine_cndmask_with_src2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vgpr_32 = COPY $vgpr1
+    %2:vgpr_32 = IMPLICIT_DEF
+
+    %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
+    %4:sreg_64_xexec = IMPLICIT_DEF
+    %5:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %1, %4, implicit $exec
+...