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Differential D69426

[clang] Switch arm-mve-intrinsics tests to use %clang_cc1.
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Authored by simon_tatham on Oct 25 2019, 3:26 AM.

Details

Reviewers
dmgreen
Commits
rG11ce19d2119e: [clang] Switch arm-mve-intrinsics tests to use %clang_cc1.
Summary

It isn't really necessary for them to run the clang driver, and it's
more efficient not to (and also more stable against driver changes).
Now they invoke cc1 directly, more like the analogous NEON tests.

Diff Detail

Event Timeline

simon_tatham created this revision.Oct 25 2019, 3:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 25 2019, 3:26 AM
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simon_tatham edited the summary of this revision. (Show Details)Oct 25 2019, 3:27 AM
Harbormaster completed remote builds in B40049: Diff 226400.Oct 25 2019, 3:33 AM
dmgreen accepted this revision.Oct 25 2019, 3:37 AM

Sounds good.

But make sure that -fno-discard-value-names is still included. Otherwise the names like "entry" will not be output, so the tests fail in "non-assert" builds.

This revision is now accepted and ready to land.Oct 25 2019, 3:37 AM
simon_tatham added a comment.Oct 25 2019, 3:50 AM

There's no need, as far as I can see. -fno-discard-value-names is a driver option only. On the cc1 command line the option is -discard-value-names, and it has no negative form: you turn it off by not specifying it in the first place, which indeed these command lines don't.

dmgreen added a comment.Oct 25 2019, 4:02 AM

Ah, I see, that's why it was needed. That makes sense.

Closed by commit rG11ce19d2119e: [clang] Switch arm-mve-intrinsics tests to use %clang_cc1. (authored by simon_tatham). · Explain WhyOct 25 2019, 4:02 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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clang/
test/
CodeGen/
arm-mve-intrinsics/
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Diff 226400

clang/test/CodeGen/arm-mve-intrinsics/scalar-shifts.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_urshrl( // CHECK-LABEL: @test_urshrl(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[VALUE:%.*]], 32 // CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[VALUE:%.*]], 32
// CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[VALUE]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[VALUE]] to i32
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clang/test/CodeGen/arm-mve-intrinsics/vadc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -DPOLYMORPHIC -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vadciq_s32( // CHECK-LABEL: @test_vadciq_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0) // CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
// CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29 // CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
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clang/test/CodeGen/arm-mve-intrinsics/vaddq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -DPOLYMORPHIC -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vaddq_u32( // CHECK-LABEL: @test_vaddq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
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clang/test/CodeGen/arm-mve-intrinsics/vcvt.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vcvttq_f16_f32( // CHECK-LABEL: @test_vcvttq_f16_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcvt.narrow(<8 x half> [[A:%.*]], <4 x float> [[B:%.*]], i32 1) // CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcvt.narrow(<8 x half> [[A:%.*]], <4 x float> [[B:%.*]], i32 1)
// CHECK-NEXT: ret <8 x half> [[TMP0]] // CHECK-NEXT: ret <8 x half> [[TMP0]]
// //
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clang/test/CodeGen/arm-mve-intrinsics/vld24.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -DPOLYMORPHIC -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vld2q_f16( // CHECK-LABEL: @test_vld2q_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0f16(half* [[ADDR:%.*]]) // CHECK-NEXT: [[TMP0:%.*]] = call { <8 x half>, <8 x half> } @llvm.arm.mve.vld2q.v8f16.p0f16(half* [[ADDR:%.*]])
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <8 x half>, <8 x half> } [[TMP0]], 0 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <8 x half>, <8 x half> } [[TMP0]], 0
// CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[STRUCT_FLOAT16X8X2_T:%.*]] undef, <8 x half> [[TMP1]], 0, 0 // CHECK-NEXT: [[TMP2:%.*]] = insertvalue [[STRUCT_FLOAT16X8X2_T:%.*]] undef, <8 x half> [[TMP1]], 0, 0
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clang/test/CodeGen/arm-mve-intrinsics/vldr.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vldrwq_gather_base_wb_s32( // CHECK-LABEL: @test_vldrwq_gather_base_wb_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[ADDR:%.*]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[ADDR:%.*]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 80) // CHECK-NEXT: [[TMP1:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 80)
// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP1]], 1 // CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[TMP1]], 1
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clang/test/CodeGen/arm-mve-intrinsics/vminvq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang --target=arm-arm-none-eabi -march=armv8.1m.main+mve.fp -mfloat-abi=hard -DPOLYMORPHIC -O0 -Xclang -disable-O0-optnone -fno-discard-value-names -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vminvq_s8( // CHECK-LABEL: @test_vminvq_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[A:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[A:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.mve.minv.s.v16i8(i32 [[TMP0]], <16 x i8> [[B:%.*]]) // CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.mve.minv.s.v16i8(i32 [[TMP0]], <16 x i8> [[B:%.*]])
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 // CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
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