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Differential D68905

[update_mir_test_checks] Handle MI flags properly
ClosedPublic

Authored by rtereshin on Oct 11 2019, 11:06 PM.

Details

Reviewers
bogner
Commits
rG044297ccbfcf: [update_mir_test_checks] Handle MI flags properly
rL374829: [update_mir_test_checks] Handle MI flags properly
Summary

previously we would generate literal check lines w/o no reg-exps for
vregs as MI flags (nsw, ninf, etc.) won't be recognized as a part of MI.

Fixing that. Includes updating the MIR tests that suffered from the
problem.

Diff Detail

Repository
rL LLVM

Event Timeline

rtereshin created this revision.Oct 11 2019, 11:06 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 11 2019, 11:06 PM
Herald added subscribers: llvm-commits, Petar.Avramovic, atanasyan and 4 others. · View Herald Transcript
bogner accepted this revision.Oct 14 2019, 10:14 AM

LGTM

utils/update_mir_test_checks.py
37–38

It'd be kind of nice if we could ensure this list stays up to date somehow, but I suppose it really doesn't change much and we'll notice the first time someone updates a test with a flag that's missing here.

This revision is now accepted and ready to land.Oct 14 2019, 10:14 AM
rtereshin marked 2 inline comments as done.Oct 14 2019, 10:39 AM
rtereshin added inline comments.
utils/update_mir_test_checks.py
37–38

Also, the list of flags in the MI def itself, the MIRParser part that handles them, as well as MIRPrinter are all hand-written and kept in sync manually at the moment. I think it's all good enough for now, if it becomes a problem, we will probably be looking into bigger fish to fry when it comes to keeping in sync everything that has to do with MIR syntax.

rtereshin marked an inline comment as done.Oct 14 2019, 2:56 PM
Closed by commit rG044297ccbfcf: [update_mir_test_checks] Handle MI flags properly (authored by rtereshin). · Explain WhyOct 14 2019, 3:02 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 224729

test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir

Show All 36 Lines bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_simple_alloca ; CHECK-LABEL: name: test_simple_alloca
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: %5:_(s64) = nuw G_ADD [[MUL]], [[C1]] ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %5, [[C2]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0) ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]] ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
; CHECK: $sp = COPY [[INTTOPTR]](p0) ; CHECK: $sp = COPY [[INTTOPTR]](p0)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
Show All 27 Lines bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_aligned_alloca ; CHECK-LABEL: name: test_aligned_alloca
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: %5:_(s64) = nuw G_ADD [[MUL]], [[C1]] ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %5, [[C2]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0) ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]] ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32 ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -32
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]] ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C3]]
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](s64) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND1]](s64)
; CHECK: $sp = COPY [[INTTOPTR]](p0) ; CHECK: $sp = COPY [[INTTOPTR]](p0)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
Show All 29 Lines bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_natural_alloca ; CHECK-LABEL: name: test_natural_alloca
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]] ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: %5:_(s64) = nuw G_ADD [[MUL]], [[C1]] ; CHECK: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %5, [[C2]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C2]]
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $sp
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0) ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY1]](p0)
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]] ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[PTRTOINT]], [[AND]]
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s64)
; CHECK: $sp = COPY [[INTTOPTR]](p0) ; CHECK: $sp = COPY [[INTTOPTR]](p0)
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0) ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; CHECK: $x0 = COPY [[COPY2]](p0) ; CHECK: $x0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
Show All 13 Lines

test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir

Show All 36 Linesbody: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP]](s1), %bb.2
; CHECK: bb.1.if.then: ; CHECK: bb.1.if.then:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: %5:_(s32) = nsw G_ADD [[COPY1]], [[COPY]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY1]], [[COPY]]
; CHECK: %6:_(s32) = nsw G_ADD %5, [[COPY1]] ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = nsw G_ADD [[ADD]], [[COPY1]]
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.3
; CHECK: bb.2.if.end: ; CHECK: bb.2.if.end:
; CHECK: successors: %bb.3(0x80000000) ; CHECK: successors: %bb.3(0x80000000)
; CHECK: %7:_(s32) = nsw G_MUL [[COPY1]], [[COPY1]] ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY1]], [[COPY1]]
; CHECK: %8:_(s32) = nuw nsw G_ADD %7, [[C1]] ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[MUL]], [[C1]]
; CHECK: bb.3.return: ; CHECK: bb.3.return:
; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI %6(s32), %bb.1, %8(s32), %bb.2 ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.1, [[ADD2]](s32), %bb.2
; CHECK: $w0 = COPY [[PHI]](s32) ; CHECK: $w0 = COPY [[PHI]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
bb.1.entry: bb.1.entry:
liveins: $w0, $w1 liveins: $w0, $w1
%0:_(s32) = COPY $w0 %0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1 %1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 0 %2:_(s32) = G_CONSTANT i32 0
Show All 20 Lines

test/CodeGen/AArch64/GlobalISel/regbank-fma.mir

Show All 12 Linesbody: |
bb.0: bb.0:
liveins: $s0, $s1, $s2 liveins: $s0, $s1, $s2
; CHECK-LABEL: name: fma_f32 ; CHECK-LABEL: name: fma_f32
; CHECK: liveins: $s0, $s1, $s2 ; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s1 ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s2 ; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s2
; CHECK: %3:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]] ; CHECK: [[FMA:%[0-9]+]]:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $s0 = COPY %3(s32) ; CHECK: $s0 = COPY [[FMA]](s32)
; CHECK: RET_ReallyLR implicit $s0 ; CHECK: RET_ReallyLR implicit $s0
%0:_(s32) = COPY $s0 %0:_(s32) = COPY $s0
%1:_(s32) = COPY $s1 %1:_(s32) = COPY $s1
%2:_(s32) = COPY $s2 %2:_(s32) = COPY $s2
%3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2 %3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
$s0 = COPY %3(s32) $s0 = COPY %3(s32)
RET_ReallyLR implicit $s0 RET_ReallyLR implicit $s0
... ...
--- ---
name: fma_f64 name: fma_f64
alignment: 4 alignment: 4
legalized: true legalized: true
tracksRegLiveness: true tracksRegLiveness: true
machineFunctionInfo: {} machineFunctionInfo: {}
body: | body: |
bb.0: bb.0:
liveins: $d0, $d1, $d2 liveins: $d0, $d1, $d2
; CHECK-LABEL: name: fma_f64 ; CHECK-LABEL: name: fma_f64
; CHECK: liveins: $d0, $d1, $d2 ; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0 ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d1 ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d2 ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d2
; CHECK: %3:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]] ; CHECK: [[FMA:%[0-9]+]]:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $d0 = COPY %3(s64) ; CHECK: $d0 = COPY [[FMA]](s64)
; CHECK: RET_ReallyLR implicit $d0 ; CHECK: RET_ReallyLR implicit $d0
%0:_(s64) = COPY $d0 %0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1 %1:_(s64) = COPY $d1
%2:_(s64) = COPY $d2 %2:_(s64) = COPY $d2
%3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2 %3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
$d0 = COPY %3(s64) $d0 = COPY %3(s64)
RET_ReallyLR implicit $d0 RET_ReallyLR implicit $d0
... ...

test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines - id: 0
'%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4',
'%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2' ] '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2' ]
body: | body: |
; CHECK-LABEL: name: jt_test ; CHECK-LABEL: name: jt_test
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000)
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
; CHECK: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[SUBREG_TO_REG]], 0, 31 ; CHECK: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[SUBREG_TO_REG]], 0, 31
; CHECK: $xzr = SUBSXri [[UBFMXri]], 71, 0, implicit-def $nzcv ; CHECK: $xzr = SUBSXri [[UBFMXri]], 71, 0, implicit-def $nzcv
; CHECK: Bcc 8, %bb.4, implicit $nzcv ; CHECK: Bcc 8, %bb.4, implicit $nzcv
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
; CHECK: [[MOVi32imm1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[UBFMXri]], %jump-table.0 ; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[UBFMXri]], %jump-table.0
; CHECK: BR %18 ; CHECK: BR %18
; CHECK: bb.2.sw.bb: ; CHECK: bb.2.sw.bb:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 42, 0 ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 42, 0
; CHECK: B %bb.4 ; CHECK: B %bb.4
; CHECK: bb.3.sw.bb1: ; CHECK: bb.3.sw.bb1:
; CHECK: successors: %bb.4(0x80000000) ; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 3 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm2]], $wzr ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[MOVi32imm]], $wzr
; CHECK: bb.4.return: ; CHECK: bb.4.return:
; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[MOVi32imm]], %bb.0, [[MOVi32imm1]], %bb.1 ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[COPY1]], %bb.0, [[COPY2]], %bb.1
; CHECK: $w0 = COPY [[PHI]] ; CHECK: $w0 = COPY [[PHI]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
bb.1.entry: bb.1.entry:
liveins: $w0 liveins: $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%4:gpr(s32) = G_CONSTANT i32 71 %4:gpr(s32) = G_CONSTANT i32 71
%8:gpr(s32) = G_CONSTANT i32 3 %8:gpr(s32) = G_CONSTANT i32 3
Show All 32 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir

Show First 20 Lines • Show All 144 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-LABEL: name: test_fadd_v2s32_flags ; SI-LABEL: name: test_fadd_v2s32_flags
; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: %7:_(s32) = nnan G_FADD [[UV]], [[UV2]] ; SI: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[UV]], [[UV2]]
; SI: %8:_(s32) = nnan G_FADD [[UV1]], [[UV3]] ; SI: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; VI-LABEL: name: test_fadd_v2s32_flags ; VI-LABEL: name: test_fadd_v2s32_flags
; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; VI: %7:_(s32) = nnan G_FADD [[UV]], [[UV2]] ; VI: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[UV]], [[UV2]]
; VI: %8:_(s32) = nnan G_FADD [[UV1]], [[UV3]] ; VI: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fadd_v2s32_flags ; GFX9-LABEL: name: test_fadd_v2s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9: %7:_(s32) = nnan G_FADD [[UV]], [[UV2]] ; GFX9: [[FADD:%[0-9]+]]:_(s32) = nnan G_FADD [[UV]], [[UV2]]
; GFX9: %8:_(s32) = nnan G_FADD [[UV1]], [[UV3]] ; GFX9: [[FADD1:%[0-9]+]]:_(s32) = nnan G_FADD [[UV1]], [[UV3]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FADD]](s32), [[FADD1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = nnan G_FADD %0, %1 %2:_(<2 x s32>) = nnan G_FADD %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
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test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
name: test_fcmp_v2s32_flags name: test_fcmp_v2s32_flags
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GFX7-LABEL: name: test_fcmp_v2s32_flags ; GFX7-LABEL: name: test_fcmp_v2s32_flags
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX7: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX7: %8:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]] ; GFX7: [[FCMP:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]]
; GFX7: %9:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]] ; GFX7: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %8(s1) ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT %9(s1) ; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32) ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>) ; GFX7: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
; GFX7: S_NOP 0, implicit [[TRUNC]](<2 x s1>) ; GFX7: S_NOP 0, implicit [[TRUNC]](<2 x s1>)
; GFX8-LABEL: name: test_fcmp_v2s32_flags ; GFX8-LABEL: name: test_fcmp_v2s32_flags
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: %8:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]] ; GFX8: [[FCMP:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]]
; GFX8: %9:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]] ; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %8(s1) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT %9(s1) ; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32) ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX8: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>) ; GFX8: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
; GFX8: S_NOP 0, implicit [[TRUNC]](<2 x s1>) ; GFX8: S_NOP 0, implicit [[TRUNC]](<2 x s1>)
; GFX9-LABEL: name: test_fcmp_v2s32_flags ; GFX9-LABEL: name: test_fcmp_v2s32_flags
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: %8:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]] ; GFX9: [[FCMP:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]]
; GFX9: %9:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]] ; GFX9: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %8(s1) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT %9(s1) ; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>) ; GFX9: [[TRUNC:%[0-9]+]]:_(<2 x s1>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
; GFX9: S_NOP 0, implicit [[TRUNC]](<2 x s1>) ; GFX9: S_NOP 0, implicit [[TRUNC]](<2 x s1>)
%0:_(s32) = G_CONSTANT i32 0 %0:_(s32) = G_CONSTANT i32 0
%1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0 %1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0
%2:_(<2 x s32>) = COPY $vgpr0_vgpr1 %2:_(<2 x s32>) = COPY $vgpr0_vgpr1
%3:_(<2 x s1>) = nnan G_FCMP floatpred(oeq), %1, %2 %3:_(<2 x s1>) = nnan G_FCMP floatpred(oeq), %1, %2
S_NOP 0, implicit %3 S_NOP 0, implicit %3
▲ Show 20 Lines • Show All 204 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir

Show First 20 Lines • Show All 767 Lines • ▼ Show 20 Lines bb.0:
; SI-LABEL: name: test_copysign_s32_s32_flagss ; SI-LABEL: name: test_copysign_s32_s32_flagss
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI: %2:_(s32) = nnan G_OR [[AND]], [[AND1]] ; SI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; SI: $vgpr0 = COPY %2(s32) ; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_copysign_s32_s32_flagss ; VI-LABEL: name: test_copysign_s32_s32_flagss
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; VI: %2:_(s32) = nnan G_OR [[AND]], [[AND1]] ; VI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; VI: $vgpr0 = COPY %2(s32) ; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_copysign_s32_s32_flagss ; GFX9-LABEL: name: test_copysign_s32_s32_flagss
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX9: %2:_(s32) = nnan G_OR [[AND]], [[AND1]] ; GFX9: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND1]]
; GFX9: $vgpr0 = COPY %2(s32) ; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = nnan G_FCOPYSIGN %0, %1 %2:_(s32) = nnan G_FCOPYSIGN %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_copysign_s32_s16_flags name: test_copysign_s32_s16_flags
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_copysign_s32_s16_flags ; SI-LABEL: name: test_copysign_s32_s16_flags
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]] ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI: %3:_(s32) = nnan G_OR [[AND]], [[AND2]] ; SI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
; SI: $vgpr0 = COPY %3(s32) ; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_copysign_s32_s16_flags ; VI-LABEL: name: test_copysign_s32_s16_flags
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]] ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI: %3:_(s32) = nnan G_OR [[AND]], [[AND2]] ; VI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
; VI: $vgpr0 = COPY %3(s32) ; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_copysign_s32_s16_flags ; GFX9-LABEL: name: test_copysign_s32_s16_flags
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]] ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; GFX9: %3:_(s32) = nnan G_OR [[AND]], [[AND2]] ; GFX9: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
; GFX9: $vgpr0 = COPY %3(s32) ; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1 %2:_(s16) = G_TRUNC %1
%3:_(s32) = nnan G_FCOPYSIGN %0, %2 %3:_(s32) = nnan G_FCOPYSIGN %0, %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
Show All 9 Lines bb.0:
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]] ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]] ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; SI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]] ; SI: [[OR:%[0-9]+]]:_(s16) = nnan G_OR [[AND]], [[AND1]]
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16) ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: $vgpr0 = COPY [[ANYEXT]](s32) ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s32_flags ; VI-LABEL: name: test_copysign_s16_s32_flags
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]] ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]] ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; VI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]] ; VI: [[OR:%[0-9]+]]:_(s16) = nnan G_OR [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16) ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32) ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s32_flags ; GFX9-LABEL: name: test_copysign_s16_s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]] ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32) ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]] ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: %3:_(s16) = nnan G_OR [[AND]], [[AND1]] ; GFX9: [[OR:%[0-9]+]]:_(s16) = nnan G_OR [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = nnan G_FCOPYSIGN %2, %1 %3:_(s16) = nnan G_FCOPYSIGN %2, %1
%4:_(s32) = G_ANYEXT %3 %4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir

Show First 20 Lines • Show All 517 Lines • ▼ Show 20 Lines
name: test_fcos_s32_flags name: test_fcos_s32_flags
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; SI-LABEL: name: test_fcos_s32_flags ; SI-LABEL: name: test_fcos_s32_flags
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 ; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
; SI: %3:_(s32) = nnan G_FMUL [[COPY]], [[C]] ; SI: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; SI: %4:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %3(s32) ; SI: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI: %1:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %4(s32) ; SI: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
; SI: $vgpr0 = COPY %1(s32) ; SI: $vgpr0 = COPY [[INT1]](s32)
; VI-LABEL: name: test_fcos_s32_flags ; VI-LABEL: name: test_fcos_s32_flags
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
; VI: %3:_(s32) = nnan G_FMUL [[COPY]], [[C]] ; VI: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; VI: %4:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %3(s32) ; VI: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI: %1:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %4(s32) ; VI: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
; VI: $vgpr0 = COPY %1(s32) ; VI: $vgpr0 = COPY [[INT1]](s32)
; GFX9-LABEL: name: test_fcos_s32_flags ; GFX9-LABEL: name: test_fcos_s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
; GFX9: %3:_(s32) = nnan G_FMUL [[COPY]], [[C]] ; GFX9: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; GFX9: %1:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %3(s32) ; GFX9: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[FMUL]](s32)
; GFX9: $vgpr0 = COPY %1(s32) ; GFX9: $vgpr0 = COPY [[INT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = nnan G_FCOS %0 %1:_(s32) = nnan G_FCOS %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
name: test_fminnum_s32_nnan name: test_fminnum_s32_nnan
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan ; SI-LABEL: name: test_fminnum_s32_nnan
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: %2:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; SI: $vgpr0 = COPY %2(s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan ; VI-LABEL: name: test_fminnum_s32_nnan
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: %2:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; VI: $vgpr0 = COPY %2(s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan ; GFX9-LABEL: name: test_fminnum_s32_nnan
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: %2:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9: $vgpr0 = COPY %2(s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = nnan G_FMINNUM %0, %1 %2:_(s32) = nnan G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_fminnum_s32_nnan_lhs name: test_fminnum_s32_nnan_lhs
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan_lhs ; SI-LABEL: name: test_fminnum_s32_nnan_lhs
; SI: %0:_(s32) = nnan COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, [[FCANONICALIZE]] ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan_lhs ; VI-LABEL: name: test_fminnum_s32_nnan_lhs
; VI: %0:_(s32) = nnan COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, [[FCANONICALIZE]] ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs ; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs
; GFX9: %0:_(s32) = nnan COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, [[FCANONICALIZE]] ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = nnan COPY $vgpr0 %0:_(s32) = nnan COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FMINNUM %0, %1 %2:_(s32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_fminnum_s32_nnan_rhs name: test_fminnum_s32_nnan_rhs
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan_rhs ; SI-LABEL: name: test_fminnum_s32_nnan_rhs
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: %1:_(s32) = nnan COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], %1 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan_rhs ; VI-LABEL: name: test_fminnum_s32_nnan_rhs
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: %1:_(s32) = nnan COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], %1 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan_rhs ; GFX9-LABEL: name: test_fminnum_s32_nnan_rhs
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: %1:_(s32) = nnan COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], %1 ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = nnan COPY $vgpr1 %1:_(s32) = nnan COPY $vgpr1
%2:_(s32) = G_FMINNUM %0, %1 %2:_(s32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_fminnum_s32_nnan_lhs_rhs name: test_fminnum_s32_nnan_lhs_rhs
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs ; SI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; SI: %0:_(s32) = nnan COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; SI: %1:_(s32) = nnan COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, %1 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs ; VI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; VI: %0:_(s32) = nnan COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; VI: %1:_(s32) = nnan COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, %1 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs_rhs ; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; GFX9: %0:_(s32) = nnan COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; GFX9: %1:_(s32) = nnan COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, %1 ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = nnan COPY $vgpr0 %0:_(s32) = nnan COPY $vgpr0
%1:_(s32) = nnan COPY $vgpr1 %1:_(s32) = nnan COPY $vgpr1
%2:_(s32) = G_FMINNUM %0, %1 %2:_(s32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 435 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
name: test_fminnum_s32_nnan name: test_fminnum_s32_nnan
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan ; SI-LABEL: name: test_fminnum_s32_nnan
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: %2:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; SI: $vgpr0 = COPY %2(s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan ; VI-LABEL: name: test_fminnum_s32_nnan
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: %2:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; VI: $vgpr0 = COPY %2(s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan ; GFX9-LABEL: name: test_fminnum_s32_nnan
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: %2:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]] ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9: $vgpr0 = COPY %2(s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = nnan G_FMINNUM %0, %1 %2:_(s32) = nnan G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_fminnum_s32_nnan_lhs name: test_fminnum_s32_nnan_lhs
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan_lhs ; SI-LABEL: name: test_fminnum_s32_nnan_lhs
; SI: %0:_(s32) = nnan COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, [[FCANONICALIZE]] ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan_lhs ; VI-LABEL: name: test_fminnum_s32_nnan_lhs
; VI: %0:_(s32) = nnan COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, [[FCANONICALIZE]] ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs ; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs
; GFX9: %0:_(s32) = nnan COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY1]]
; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, [[FCANONICALIZE]] ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[FCANONICALIZE]]
; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = nnan COPY $vgpr0 %0:_(s32) = nnan COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FMINNUM %0, %1 %2:_(s32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_fminnum_s32_nnan_rhs name: test_fminnum_s32_nnan_rhs
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan_rhs ; SI-LABEL: name: test_fminnum_s32_nnan_rhs
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: %1:_(s32) = nnan COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; SI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], %1 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan_rhs ; VI-LABEL: name: test_fminnum_s32_nnan_rhs
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: %1:_(s32) = nnan COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; VI: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], %1 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan_rhs ; GFX9-LABEL: name: test_fminnum_s32_nnan_rhs
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: %1:_(s32) = nnan COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]] ; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[COPY]]
; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], %1 ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]]
; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = nnan COPY $vgpr1 %1:_(s32) = nnan COPY $vgpr1
%2:_(s32) = G_FMINNUM %0, %1 %2:_(s32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: test_fminnum_s32_nnan_lhs_rhs name: test_fminnum_s32_nnan_lhs_rhs
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; SI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs ; SI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; SI: %0:_(s32) = nnan COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; SI: %1:_(s32) = nnan COPY $vgpr1 ; SI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, %1 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; SI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; VI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs ; VI-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; VI: %0:_(s32) = nnan COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; VI: %1:_(s32) = nnan COPY $vgpr1 ; VI: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, %1 ; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; VI: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs_rhs ; GFX9-LABEL: name: test_fminnum_s32_nnan_lhs_rhs
; GFX9: %0:_(s32) = nnan COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = nnan COPY $vgpr0
; GFX9: %1:_(s32) = nnan COPY $vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = nnan COPY $vgpr1
; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE %0, %1 ; GFX9: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[COPY]], [[COPY1]]
; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) ; GFX9: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
%0:_(s32) = nnan COPY $vgpr0 %0:_(s32) = nnan COPY $vgpr0
%1:_(s32) = nnan COPY $vgpr1 %1:_(s32) = nnan COPY $vgpr1
%2:_(s32) = G_FMINNUM %0, %1 %2:_(s32) = G_FMINNUM %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 435 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-LABEL: name: test_fmul_v2s32_flags ; SI-LABEL: name: test_fmul_v2s32_flags
; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: %7:_(s32) = nnan G_FMUL [[UV]], [[UV2]] ; SI: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV]], [[UV2]]
; SI: %8:_(s32) = nnan G_FMUL [[UV1]], [[UV3]] ; SI: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV1]], [[UV3]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; VI-LABEL: name: test_fmul_v2s32_flags ; VI-LABEL: name: test_fmul_v2s32_flags
; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; VI: %7:_(s32) = nnan G_FMUL [[UV]], [[UV2]] ; VI: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV]], [[UV2]]
; VI: %8:_(s32) = nnan G_FMUL [[UV1]], [[UV3]] ; VI: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV1]], [[UV3]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fmul_v2s32_flags ; GFX9-LABEL: name: test_fmul_v2s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9: %7:_(s32) = nnan G_FMUL [[UV]], [[UV2]] ; GFX9: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV]], [[UV2]]
; GFX9: %8:_(s32) = nnan G_FMUL [[UV1]], [[UV3]] ; GFX9: [[FMUL1:%[0-9]+]]:_(s32) = nnan G_FMUL [[UV1]], [[UV3]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FMUL]](s32), [[FMUL1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = nnan G_FMUL %0, %1 %2:_(<2 x s32>) = nnan G_FMUL %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 348 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir

Show All 25 Lines bb.0:
; CHECK-LABEL: name: test_fpext_v2f16_to_v2f32 ; CHECK-LABEL: name: test_fpext_v2f16_to_v2f32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: %4:_(s32) = nnan G_FPEXT [[TRUNC]](s16) ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC]](s16)
; CHECK: %5:_(s32) = nnan G_FPEXT [[TRUNC1]](s16) ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC1]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPEXT]](s32), [[FPEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = nnan G_FPEXT %0 %1:_(<2 x s32>) = nnan G_FPEXT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_fpext_v2f16_to_v2f32_w_flags name: test_fpext_v2f16_to_v2f32_w_flags
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_fpext_v2f16_to_v2f32_w_flags ; CHECK-LABEL: name: test_fpext_v2f16_to_v2f32_w_flags
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: %4:_(s32) = nnan G_FPEXT [[TRUNC]](s16) ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC]](s16)
; CHECK: %5:_(s32) = nnan G_FPEXT [[TRUNC1]](s16) ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = nnan G_FPEXT [[TRUNC1]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPEXT]](s32), [[FPEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0 %0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = nnan G_FPEXT %0 %1:_(<2 x s32>) = nnan G_FPEXT %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: test_fpext_v3f16_to_v3f32 name: test_fpext_v3f16_to_v3f32
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir

Show First 20 Lines • Show All 517 Lines • ▼ Show 20 Lines
name: test_fsin_s32_flags name: test_fsin_s32_flags
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; SI-LABEL: name: test_fsin_s32_flags ; SI-LABEL: name: test_fsin_s32_flags
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 ; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
; SI: %3:_(s32) = nnan G_FMUL [[COPY]], [[C]] ; SI: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; SI: %4:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %3(s32) ; SI: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; SI: %1:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %4(s32) ; SI: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
; SI: $vgpr0 = COPY %1(s32) ; SI: $vgpr0 = COPY [[INT1]](s32)
; VI-LABEL: name: test_fsin_s32_flags ; VI-LABEL: name: test_fsin_s32_flags
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
; VI: %3:_(s32) = nnan G_FMUL [[COPY]], [[C]] ; VI: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; VI: %4:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %3(s32) ; VI: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
; VI: %1:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %4(s32) ; VI: [[INT1:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
; VI: $vgpr0 = COPY %1(s32) ; VI: $vgpr0 = COPY [[INT1]](s32)
; GFX9-LABEL: name: test_fsin_s32_flags ; GFX9-LABEL: name: test_fsin_s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 ; GFX9: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000
; GFX9: %3:_(s32) = nnan G_FMUL [[COPY]], [[C]] ; GFX9: [[FMUL:%[0-9]+]]:_(s32) = nnan G_FMUL [[COPY]], [[C]]
; GFX9: %1:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %3(s32) ; GFX9: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FMUL]](s32)
; GFX9: $vgpr0 = COPY %1(s32) ; GFX9: $vgpr0 = COPY [[INT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = nnan G_FSIN %0 %1:_(s32) = nnan G_FSIN %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...

test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-LABEL: name: test_fsub_s64_fmf ; SI-LABEL: name: test_fsub_s64_fmf
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] ; SI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; SI: %2:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]] ; SI: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
; SI: $vgpr0_vgpr1 = COPY %2(s64) ; SI: $vgpr0_vgpr1 = COPY [[FADD]](s64)
; VI-LABEL: name: test_fsub_s64_fmf ; VI-LABEL: name: test_fsub_s64_fmf
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] ; VI: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; VI: %2:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]] ; VI: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
; VI: $vgpr0_vgpr1 = COPY %2(s64) ; VI: $vgpr0_vgpr1 = COPY [[FADD]](s64)
; GFX9-LABEL: name: test_fsub_s64_fmf ; GFX9-LABEL: name: test_fsub_s64_fmf
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]] ; GFX9: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; GFX9: %2:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]] ; GFX9: [[FADD:%[0-9]+]]:_(s64) = nnan nsz G_FADD [[COPY]], [[FNEG]]
; GFX9: $vgpr0_vgpr1 = COPY %2(s64) ; GFX9: $vgpr0_vgpr1 = COPY [[FADD]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3 %1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = nnan nsz G_FSUB %0, %1 %2:_(s64) = nnan nsz G_FSUB %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
name: test_fsub_s16 name: test_fsub_s16
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; SI-LABEL: name: test_fsub_v2s32_flags ; SI-LABEL: name: test_fsub_v2s32_flags
; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; SI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: %7:_(s32) = nnan G_FSUB [[UV]], [[UV2]] ; SI: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV]], [[UV2]]
; SI: %8:_(s32) = nnan G_FSUB [[UV1]], [[UV3]] ; SI: [[FSUB1:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV1]], [[UV3]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; VI-LABEL: name: test_fsub_v2s32_flags ; VI-LABEL: name: test_fsub_v2s32_flags
; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; VI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; VI: %7:_(s32) = nnan G_FSUB [[UV]], [[UV2]] ; VI: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV]], [[UV2]]
; VI: %8:_(s32) = nnan G_FSUB [[UV1]], [[UV3]] ; VI: [[FSUB1:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV1]], [[UV3]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fsub_v2s32_flags ; GFX9-LABEL: name: test_fsub_v2s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9: %7:_(s32) = nnan G_FSUB [[UV]], [[UV2]] ; GFX9: [[FSUB:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV]], [[UV2]]
; GFX9: %8:_(s32) = nnan G_FSUB [[UV1]], [[UV3]] ; GFX9: [[FSUB1:%[0-9]+]]:_(s32) = nnan G_FSUB [[UV1]], [[UV3]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR %7(s32), %8(s32) ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSUB]](s32), [[FSUB1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s32>) = nnan G_FSUB %0, %1 %2:_(<2 x s32>) = nnan G_FSUB %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
--- ---
▲ Show 20 Lines • Show All 404 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir

Show All 30 Lines
name: test_amdgcn_fdiv_fast_propagate_flags name: test_amdgcn_fdiv_fast_propagate_flags
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_amdgcn_fdiv_fast_propagate_flags ; CHECK-LABEL: name: test_amdgcn_fdiv_fast_propagate_flags
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: %3:_(s32) = nsz G_FABS [[COPY1]] ; CHECK: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1870659584 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1870659584
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 796917760 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 796917760
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216
; CHECK: %7:_(s1) = nsz G_FCMP floatpred(ogt), %3(s32), [[C]] ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
; CHECK: %8:_(s32) = nsz G_SELECT %7(s1), [[C1]], [[C2]] ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
; CHECK: %9:_(s32) = nsz G_FMUL [[COPY1]], %8 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY1]], [[SELECT]]
; CHECK: %10:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %9(s32) ; CHECK: [[INT:%[0-9]+]]:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FMUL]](s32)
; CHECK: %11:_(s32) = nsz G_FMUL [[COPY]], %10 ; CHECK: [[FMUL1:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY]], [[INT]]
; CHECK: %2:_(s32) = nsz G_FMUL %8, %11 ; CHECK: [[FMUL2:%[0-9]+]]:_(s32) = nsz G_FMUL [[SELECT]], [[FMUL1]]
; CHECK: $vgpr0 = COPY %2(s32) ; CHECK: $vgpr0 = COPY [[FMUL2]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %1 %2:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...

test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir

Show All 30 Lines bb.1.entry:
; MIPS32: liveins: $a0, $a1 ; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C]]
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ADD]], [[C]] ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ADD]], [[C]]
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; MIPS32: %8:_(s32) = nuw G_ADD [[MUL]], [[C2]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C2]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8 ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND %8, [[C3]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C3]]
; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $sp ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $sp
; MIPS32: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0) ; MIPS32: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[PTRTOINT]], [[AND]] ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[PTRTOINT]], [[AND]]
; MIPS32: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s32) ; MIPS32: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[SUB]](s32)
; MIPS32: $sp = COPY [[INTTOPTR]](p0) ; MIPS32: $sp = COPY [[INTTOPTR]](p0)
; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0) ; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp ; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY3]](p0) ; MIPS32: $a0 = COPY [[COPY3]](p0)
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utils/update_mir_test_checks.py

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import sys import sys
from UpdateTestChecks import common from UpdateTestChecks import common
MIR_FUNC_NAME_RE = re.compile(r' *name: *(?P<func>[A-Za-z0-9_.-]+)') MIR_FUNC_NAME_RE = re.compile(r' *name: *(?P<func>[A-Za-z0-9_.-]+)')
MIR_BODY_BEGIN_RE = re.compile(r' *body: *\|') MIR_BODY_BEGIN_RE = re.compile(r' *body: *\|')
MIR_BASIC_BLOCK_RE = re.compile(r' *bb\.[0-9]+.*:$') MIR_BASIC_BLOCK_RE = re.compile(r' *bb\.[0-9]+.*:$')
VREG_RE = re.compile(r'(%[0-9]+)(?::[a-z0-9_]+)?(?:\([<>a-z0-9 ]+\))?') VREG_RE = re.compile(r'(%[0-9]+)(?::[a-z0-9_]+)?(?:\([<>a-z0-9 ]+\))?')
MI_FLAGS_STR= (
r'(frame-setup |frame-destroy |nnan |ninf |nsz |arcp |contract |afn '
r'|reassoc |nuw |nsw |exact |fpexcept )*')
bognerUnsubmitted
Done
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It'd be kind of nice if we could ensure this list stays up to date somehow, but I suppose it really doesn't change much and we'll notice the first time someone updates a test with a flag that's missing here.

bogner: It'd be kind of nice if we could ensure this list stays up to date somehow, but I suppose it…
rtereshinAuthorUnsubmitted
Done
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Also, the list of flags in the MI def itself, the MIRParser part that handles them, as well as MIRPrinter are all hand-written and kept in sync manually at the moment. I think it's all good enough for now, if it becomes a problem, we will probably be looking into bigger fish to fry when it comes to keeping in sync everything that has to do with MIR syntax.

rtereshin: Also, the list of flags in the MI def itself, the MIRParser part that handles them, as well as…
VREG_DEF_RE = re.compile( VREG_DEF_RE = re.compile(
r'^ *(?P<vregs>{0}(?:, {0})*) ' r'^ *(?P<vregs>{0}(?:, {0})*) = '
r'= (?P<opcode>[A-Zt][A-Za-z0-9_]+)'.format(VREG_RE.pattern)) r'{1}(?P<opcode>[A-Zt][A-Za-z0-9_]+)'.format(VREG_RE.pattern, MI_FLAGS_STR))
MIR_PREFIX_DATA_RE = re.compile(r'^ *(;|bb.[0-9].*: *$|[a-z]+:( |$)|$)') MIR_PREFIX_DATA_RE = re.compile(r'^ *(;|bb.[0-9].*: *$|[a-z]+:( |$)|$)')
IR_FUNC_NAME_RE = re.compile( IR_FUNC_NAME_RE = re.compile(
r'^\s*define\s+(?:internal\s+)?[^@]*@(?P<func>[A-Za-z0-9_.]+)\s*\(') r'^\s*define\s+(?:internal\s+)?[^@]*@(?P<func>[A-Za-z0-9_.]+)\s*\(')
IR_PREFIX_DATA_RE = re.compile(r'^ *(;|$)') IR_PREFIX_DATA_RE = re.compile(r'^ *(;|$)')
MIR_FUNC_RE = re.compile( MIR_FUNC_RE = re.compile(
r'^---$' r'^---$'
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