[Alignment] Get DataLayout::StackAlignment as Align

[gchatelet]

Summary

Internally it is needed to know if StackAlignment is set but we can
expose it as llvm::Align.

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

[courbet]

Can you please explain why the switch from MaybeAlign to Align is fine ? ARMTargetLowering::getABIAlignmentForCallingConv can switch from non-zero to 0 it seems.

I see another call in the WebAsm backend.

[gchatelet]

In D67852#1678482, @courbet wrote:

Can you please explain why the switch from MaybeAlign to Align is fine ? ARMTargetLowering::getABIAlignmentForCallingConv can switch from non-zero to 0 it seems.

I see another call in the WebAsm backend.

TL;DR: call sites use std::min between two alignments which wouldn't make sense in case one of the two alignments is 0 or undefined.

Careful inspection of all call sites (including the one in WebAssembly) expect an alignment of at least 1.
Tests are still passing with this patch.

llvm/include/llvm/IR/DataLayout.h

public:
 
   bool isIllegalInteger(uint64_t Width) const { return !isLegalInteger(Width); }
 
   /// Returns true if the given alignment exceeds the natural stack alignment.
   bool exceedsNaturalStackAlignment(llvm::Align Align) const {
     return StackNaturalAlign && (Align > StackNaturalAlign);
   }
 
-  unsigned getStackAlignment() const { return StackNaturalAlign ? StackNaturalAlign->value() : 0; }
+  llvm::Align getStackAlignment() const {
+    assert(StackNaturalAlign && "StackNaturalAlign must be defined");
+    return *StackNaturalAlign;
+  }
+
   unsigned getAllocaAddrSpace() const { return AllocaAddrSpace; }
 
   /// Returns the alignment of function pointers, which may or may not be
   /// related to the alignment of functions.
   /// \see getFunctionPtrAlignType
   MaybeAlign getFunctionPtrAlign() const { return FunctionPtrAlign; }
 
   /// Return the type of function pointer alignment.

llvm/lib/Target/AArch64/AArch64CallingConvention.cpp

 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
                                      AArch64::Q3, AArch64::Q4, AArch64::Q5,
                                      AArch64::Q6, AArch64::Q7};
 
 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
                              MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
                              CCState &State, unsigned SlotAlign) {
   unsigned Size = LocVT.getSizeInBits() / 8;
-  unsigned StackAlign =
+  const llvm::Align StackAlign =
       State.getMachineFunction().getDataLayout().getStackAlignment();
-  unsigned Align = std::min(ArgFlags.getOrigAlign(), StackAlign);
+  const llvm::Align OrigAlign(ArgFlags.getOrigAlign());
+  const llvm::Align Align = std::min(OrigAlign, StackAlign);
 
   for (auto &It : PendingMembers) {
-    It.convertToMem(State.AllocateStack(Size, std::max(Align, SlotAlign)));
+    It.convertToMem(State.AllocateStack(
+        Size, std::max((unsigned)Align.value(), SlotAlign)));
     State.addLoc(It);
     SlotAlign = 1;
   }
 
   // All pending members have now been allocated
   PendingMembers.clear();
   return true;
 }

llvm/lib/Target/ARM/ARMCallingConv.cpp

PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo,
                                                    ArgFlags.getOrigAlign()));
 
   if (!ArgFlags.isInConsecutiveRegsLast())
     return true;
 
   // Try to allocate a contiguous block of registers, each of the correct
   // size to hold one member.
   auto &DL = State.getMachineFunction().getDataLayout();
-  unsigned StackAlign = DL.getStackAlignment();
+  unsigned StackAlign = DL.getStackAlignment().value();
   unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign);
 
   ArrayRef<MCPhysReg> RegList;
   switch (LocVT.SimpleTy) {
   case MVT::i32: {
     RegList = RRegList;
     unsigned RegIdx = State.getFirstUnallocated(RegList);
 

llvm/lib/Target/ARM/ARMISelLowering.cpp

 unsigned
 ARMTargetLowering::getABIAlignmentForCallingConv(Type *ArgTy,
                                                  DataLayout DL) const {
   if (!ArgTy->isVectorTy())
     return DL.getABITypeAlignment(ArgTy);
 
   // Avoid over-aligning vector parameters. It would require realigning the
   // stack and waste space for no real benefit.
-  return std::min(DL.getABITypeAlignment(ArgTy), DL.getStackAlignment());
+  return std::min(DL.getABITypeAlignment(ArgTy),
+                  (unsigned)DL.getStackAlignment().value());
 }
 
 /// Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
 /// passing according to AAPCS rules.
 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
     Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
   if (getEffectiveCallingConv(CallConv, isVarArg) !=