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Differential D67441

[MIPS GlobalISel] Select indirect branch
ClosedPublic

Authored by Petar.Avramovic on Sep 11 2019, 5:56 AM.

Details

Reviewers
atanasyan
petarj
Commits
rGff6ac1eb5f30: [MIPS GlobalISel] Select indirect branch
rL371730: [MIPS GlobalISel] Select indirect branch
Summary

Select G_BRINDIRECT for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Sep 11 2019, 5:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 11 2019, 5:56 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 2 others. · View Herald Transcript
atanasyan accepted this revision.Sep 11 2019, 10:00 AM

LGTM

This revision is now accepted and ready to land.Sep 11 2019, 10:00 AM
Closed by commit rL371730: [MIPS GlobalISel] Select indirect branch (authored by Petar.Avramovic). · Explain WhySep 12 2019, 4:44 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
5 lines
3 lines
1 line
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
56 lines
legalizer/
53 lines
llvm-ir/
33 lines
regbankselect/
54 lines

Diff 219886

llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 332 Lines • ▼ Show 20 Lines MachineInstr *Branch =
BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
.addUse(Dest); .addUse(Dest);
if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
return false; return false;
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
} }
case G_BRINDIRECT: {
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
.add(I.getOperand(0));
break;
}
case G_PHI: { case G_PHI: {
const Register DestReg = I.getOperand(0).getReg(); const Register DestReg = I.getOperand(0).getReg();
const unsigned OpSize = MRI.getType(DestReg).getSizeInBits(); const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
const TargetRegisterClass *DefRC = nullptr; const TargetRegisterClass *DefRC = nullptr;
if (Register::isPhysicalRegister(DestReg)) if (Register::isPhysicalRegister(DestReg))
DefRC = TRI.getRegClass(DestReg); DefRC = TRI.getRegClass(DestReg);
else else
▲ Show 20 Lines • Show All 437 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder(G_BRCOND) getActionDefinitionsBuilder(G_BRCOND)
.legalFor({s32}) .legalFor({s32})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_BRJT) getActionDefinitionsBuilder(G_BRJT)
.legalFor({{p0, s32}}); .legalFor({{p0, s32}});
getActionDefinitionsBuilder(G_BRINDIRECT)
.legalFor({p0});
getActionDefinitionsBuilder(G_PHI) getActionDefinitionsBuilder(G_PHI)
.legalFor({p0, s32, s64}) .legalFor({p0, s32, s64})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({s32}) .legalFor({s32})
.clampScalar(0, s32, s32); .clampScalar(0, s32, s32);
▲ Show 20 Lines • Show All 169 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 396 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case G_XOR: case G_XOR:
case G_SHL: case G_SHL:
case G_ASHR: case G_ASHR:
case G_LSHR: case G_LSHR:
case G_SDIV: case G_SDIV:
case G_UDIV: case G_UDIV:
case G_SREM: case G_SREM:
case G_UREM: case G_UREM:
case G_BRINDIRECT:
OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
break; break;
case G_LOAD: { case G_LOAD: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
InstType InstTy = InstType::Integer; InstType InstTy = InstType::Integer;
if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) { if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
InstTy = TI.determineInstType(&MI); InstTy = TI.determineInstType(&MI);
} }
▲ Show 20 Lines • Show All 294 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @indirectbr(i8* %addr) {
entry:
indirectbr i8* %addr, [label %L1, label %L2]
L1:
ret i32 0
L2:
ret i32 1
}
...
---
name: indirectbr
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: indirectbr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 0
; MIPS32: PseudoIndirectBranch [[COPY]]
; MIPS32: bb.1.L1:
; MIPS32: $v0 = COPY [[ORi1]]
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.L2:
; MIPS32: $v0 = COPY [[ORi]]
; MIPS32: RetRA implicit $v0
bb.1.entry:
successors: %bb.2, %bb.3
liveins: $a0
%0:gprb(p0) = COPY $a0
%1:gprb(s32) = G_CONSTANT i32 1
%2:gprb(s32) = G_CONSTANT i32 0
G_BRINDIRECT %0(p0)
bb.2.L1:
$v0 = COPY %2(s32)
RetRA implicit $v0
bb.3.L2:
$v0 = COPY %1(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @indirectbr(i8* %addr) {
entry:
indirectbr i8* %addr, [label %L1, label %L2]
L1:
ret i32 0
L2:
ret i32 1
}
...
---
name: indirectbr
alignment: 4
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: indirectbr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: G_BRINDIRECT [[COPY]](p0)
; MIPS32: bb.1.L1:
; MIPS32: $v0 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.L2:
; MIPS32: $v0 = COPY [[C]](s32)
; MIPS32: RetRA implicit $v0
bb.1.entry:
successors: %bb.2, %bb.3
liveins: $a0
%0:_(p0) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 0
G_BRINDIRECT %0(p0)
bb.2.L1:
$v0 = COPY %2(s32)
RetRA implicit $v0
bb.3.L2:
$v0 = COPY %1(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i32 @indirectbr(i8 *%addr) {
; MIPS32-LABEL: indirectbr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jr $4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %L1
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %L2
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
indirectbr i8* %addr, [label %L1, label %L2]
L1:
ret i32 0
L2:
ret i32 1
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define i32 @indirectbr(i8* %addr) {
entry:
indirectbr i8* %addr, [label %L1, label %L2]
L1:
ret i32 0
L2:
ret i32 1
}
...
---
name: indirectbr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
; MIPS32-LABEL: name: indirectbr
; MIPS32: bb.0.entry:
; MIPS32: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
; MIPS32: G_BRINDIRECT [[COPY]](p0)
; MIPS32: bb.1.L1:
; MIPS32: $v0 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32: bb.2.L2:
; MIPS32: $v0 = COPY [[C]](s32)
; MIPS32: RetRA implicit $v0
bb.1.entry:
successors: %bb.2, %bb.3
liveins: $a0
%0:_(p0) = COPY $a0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_CONSTANT i32 0
G_BRINDIRECT %0(p0)
bb.2.L1:
$v0 = COPY %2(s32)
RetRA implicit $v0
bb.3.L2:
$v0 = COPY %1(s32)
RetRA implicit $v0
...