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Differential D67439

[MIPS GlobalISel] Select G_IMPLICIT_DEF
ClosedPublic

Authored by Petar.Avramovic on Sep 11 2019, 5:53 AM.

Details

Reviewers
atanasyan
petarj
Commits
rG75e43a607c8b: [MIPS GlobalISel] Select G_IMPLICIT_DEF
rL371727: [MIPS GlobalISel] Select G_IMPLICIT_DEF
Summary

G_IMPLICIT_DEF is used for both integer and floating point implicit-def.
Handle G_IMPLICIT_DEF as ambiguous opcode in MipsRegisterBankInfo.
Select G_IMPLICIT_DEF for MIPS32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Sep 11 2019, 5:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 11 2019, 5:53 AM
Herald added subscribers: llvm-commits, jrtc27, arichardson and 2 others. · View Herald Transcript
atanasyan accepted this revision.Sep 11 2019, 9:49 AM

LGTM

This revision is now accepted and ready to land.Sep 11 2019, 9:49 AM
Closed by commit rL371727: [MIPS GlobalISel] Select G_IMPLICIT_DEF (authored by Petar.Avramovic). · Explain WhySep 12 2019, 4:31 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
12 lines
3 lines
25 lines
test/
CodeGen/
Mips/
GlobalISel/
instruction-select/
114 lines
legalizer/
105 lines
llvm-ir/
83 lines
regbankselect/
110 lines

Diff 219883

llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 Lines case G_SELECT: {
// Handle operands with pointer type. // Handle operands with pointer type.
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
.add(I.getOperand(0)) .add(I.getOperand(0))
.add(I.getOperand(2)) .add(I.getOperand(2))
.add(I.getOperand(1)) .add(I.getOperand(1))
.add(I.getOperand(3)); .add(I.getOperand(3));
break; break;
} }
case G_IMPLICIT_DEF: {
MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
.add(I.getOperand(0));
// Set class based on register bank, there can be fpr and gpr implicit def.
MRI.setRegClass(MI->getOperand(0).getReg(),
getRegClassForTypeOnBank(
MRI.getType(I.getOperand(0).getReg()).getSizeInBits(),
*RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI),
RBI));
break;
}
case G_CONSTANT: { case G_CONSTANT: {
MachineIRBuilder B(I); MachineIRBuilder B(I);
if (!materialize32BitImm(I.getOperand(0).getReg(), if (!materialize32BitImm(I.getOperand(0).getReg(),
I.getOperand(1).getCImm()->getValue(), B)) I.getOperand(1).getCImm()->getValue(), B))
return false; return false;
I.eraseFromParent(); I.eraseFromParent();
return true; return true;
▲ Show 20 Lines • Show All 327 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 37 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder({G_LOAD, G_STORE}) getActionDefinitionsBuilder({G_LOAD, G_STORE})
.legalForTypesWithMemDesc({{s32, p0, 8, 8}, .legalForTypesWithMemDesc({{s32, p0, 8, 8},
{s32, p0, 16, 8}, {s32, p0, 16, 8},
{s32, p0, 32, 8}, {s32, p0, 32, 8},
{s64, p0, 64, 8}, {s64, p0, 64, 8},
{p0, p0, 32, 8}}) {p0, p0, 32, 8}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_IMPLICIT_DEF)
.legalFor({s32, s64});
getActionDefinitionsBuilder(G_UNMERGE_VALUES) getActionDefinitionsBuilder(G_UNMERGE_VALUES)
.legalFor({{s32, s64}}); .legalFor({{s32, s64}});
getActionDefinitionsBuilder(G_MERGE_VALUES) getActionDefinitionsBuilder(G_MERGE_VALUES)
.legalFor({{s64, s32}}); .legalFor({{s64, s32}});
getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD}) getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
.legalForTypesWithMemDesc({{s32, p0, 8, 8}, .legalForTypesWithMemDesc({{s32, p0, 8, 8},
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
} }
static bool isAmbiguous(unsigned Opc) { static bool isAmbiguous(unsigned Opc) {
switch (Opc) { switch (Opc) {
case TargetOpcode::G_LOAD: case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE: case TargetOpcode::G_STORE:
case TargetOpcode::G_PHI: case TargetOpcode::G_PHI:
case TargetOpcode::G_SELECT: case TargetOpcode::G_SELECT:
case TargetOpcode::G_IMPLICIT_DEF:
return true; return true;
default: default:
return false; return false;
} }
} }
void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses( void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(
Register Reg, const MachineRegisterInfo &MRI) { Register Reg, const MachineRegisterInfo &MRI) {
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 LinesMipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(
} }
if (MI->getOpcode() == TargetOpcode::G_SELECT) { if (MI->getOpcode() == TargetOpcode::G_SELECT) {
addDefUses(MI->getOperand(0).getReg(), MRI); addDefUses(MI->getOperand(0).getReg(), MRI);
addUseDef(MI->getOperand(2).getReg(), MRI); addUseDef(MI->getOperand(2).getReg(), MRI);
addUseDef(MI->getOperand(3).getReg(), MRI); addUseDef(MI->getOperand(3).getReg(), MRI);
} }
if (MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
addDefUses(MI->getOperand(0).getReg(), MRI);
} }
bool MipsRegisterBankInfo::TypeInfoForMF::visit( bool MipsRegisterBankInfo::TypeInfoForMF::visit(
const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI) { const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI) {
assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n"); assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n");
if (wasVisited(MI)) if (wasVisited(MI))
return true; // InstType has already been determined for MI. return true; // InstType has already been determined for MI.
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines if (InstTy == InstType::FloatingPoint ||
: &Mips::ValueMappings[Mips::DPRIdx]; : &Mips::ValueMappings[Mips::DPRIdx];
OperandsMapping = getOperandsMapping( OperandsMapping = getOperandsMapping(
{Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank}); {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank});
if (Size == 64) if (Size == 64)
MappingID = CustomMappingID; MappingID = CustomMappingID;
} }
break; break;
} }
case G_IMPLICIT_DEF: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
InstType InstTy = InstType::Integer;
if (!MRI.getType(MI.getOperand(0).getReg()).isPointer()) {
InstTy = TI.determineInstType(&MI);
}
if (InstTy == InstType::FloatingPoint) { // fprb
OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx];
} else { // gprb
OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::GPRIdx]
: &Mips::ValueMappings[Mips::DPRIdx];
if (Size == 64)
MappingID = CustomMappingID;
}
break;
}
case G_UNMERGE_VALUES: { case G_UNMERGE_VALUES: {
OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::GPRIdx],
&Mips::ValueMappings[Mips::DPRIdx]}); &Mips::ValueMappings[Mips::DPRIdx]});
MappingID = CustomMappingID; MappingID = CustomMappingID;
break; break;
} }
case G_MERGE_VALUES: { case G_MERGE_VALUES: {
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Linesvoid MipsRegisterBankInfo::applyMappingImpl(
LegalizerHelper Helper(*MF, WrapperObserver, B); LegalizerHelper Helper(*MF, WrapperObserver, B);
LegalizationArtifactCombiner ArtCombiner( LegalizationArtifactCombiner ArtCombiner(
B, MF->getRegInfo(), *MF->getSubtarget().getLegalizerInfo()); B, MF->getRegInfo(), *MF->getSubtarget().getLegalizerInfo());
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
case TargetOpcode::G_LOAD: case TargetOpcode::G_LOAD:
case TargetOpcode::G_STORE: case TargetOpcode::G_STORE:
case TargetOpcode::G_PHI: case TargetOpcode::G_PHI:
case TargetOpcode::G_SELECT: { case TargetOpcode::G_SELECT:
case TargetOpcode::G_IMPLICIT_DEF: {
Helper.narrowScalar(MI, 0, LLT::scalar(32)); Helper.narrowScalar(MI, 0, LLT::scalar(32));
// Handle new instructions. // Handle new instructions.
while (!NewInstrs.empty()) { while (!NewInstrs.empty()) {
MachineInstr *NewMI = NewInstrs.pop_back_val(); MachineInstr *NewMI = NewInstrs.pop_back_val();
// This is new G_UNMERGE that was created during narrowScalar and will // This is new G_UNMERGE that was created during narrowScalar and will
// not be considered for regbank selection. RegBankSelect for mips // not be considered for regbank selection. RegBankSelect for mips
// visits/makes corresponding G_MERGE first. Combine them here. // visits/makes corresponding G_MERGE first. Combine them here.
if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) { if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) {
Show All 34 Lines

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/implicit_def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare void @f_i32(i32)
define void @g_i32() {entry: ret void}
declare void @f_i64(i64)
define void @g_i64() {entry: ret void}
declare void @f_float(float)
define void @g_float() {entry: ret void}
declare void @f_double(double)
define void @g_double() {entry: ret void}
...
---
name: g_i32
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i32
; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[DEF]]
; MIPS32: JAL @f_i32, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:gprb(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %0(s32)
JAL @f_i32, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_i64
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i64
; MIPS32: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MIPS32: [[DEF1:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[DEF]]
; MIPS32: $a1 = COPY [[DEF1]]
; MIPS32: JAL @f_i64, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%3:gprb(s32) = G_IMPLICIT_DEF
%4:gprb(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %3(s32)
$a1 = COPY %4(s32)
JAL @f_i64, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_float
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_float
; MIPS32: [[DEF:%[0-9]+]]:fgr32 = IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $f12 = COPY [[DEF]]
; MIPS32: JAL @f_float, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:fprb(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$f12 = COPY %0(s32)
JAL @f_float, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_double
alignment: 2
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_double
; MIPS32: [[DEF:%[0-9]+]]:afgr64 = IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $d6 = COPY [[DEF]]
; MIPS32: JAL @f_double, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:fprb(s64) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$d6 = COPY %0(s64)
JAL @f_double, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/implicit_def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare void @f_i32(i32)
define void @g_i32() {entry: ret void}
declare void @f_i64(i64)
define void @g_i64() {entry: ret void}
declare void @f_float(float)
define void @g_float() {entry: ret void}
declare void @f_double(double)
define void @g_double() {entry: ret void}
...
---
name: g_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i32
; MIPS32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[DEF]](s32)
; MIPS32: JAL @f_i32, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %0(s32)
JAL @f_i32, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_i64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i64
; MIPS32: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; MIPS32: $a0 = COPY [[UV]](s32)
; MIPS32: $a1 = COPY [[UV1]](s32)
; MIPS32: JAL @f_i64, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s64) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
$a0 = COPY %1(s32)
$a1 = COPY %2(s32)
JAL @f_i64, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_float
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_float
; MIPS32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $f12 = COPY [[DEF]](s32)
; MIPS32: JAL @f_float, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$f12 = COPY %0(s32)
JAL @f_float, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_double
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_double
; MIPS32: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $d6 = COPY [[DEF]](s64)
; MIPS32: JAL @f_double, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s64) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$d6 = COPY %0(s64)
JAL @f_double, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/implicit_def.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
declare void @f_i32(i32)
define void @g_i32() {
; MIPS32-LABEL: g_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: # implicit-def: $a0
; MIPS32-NEXT: jal f_i32
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
call void @f_i32(i32 undef)
ret void
}
declare void @f_i64(i64)
define void @g_i64() {
; MIPS32-LABEL: g_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: # implicit-def: $a0
; MIPS32-NEXT: # implicit-def: $a1
; MIPS32-NEXT: jal f_i64
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
call void @f_i64(i64 undef)
ret void
}
declare void @f_float(float)
define void @g_float() {
; MIPS32-LABEL: g_float:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: # implicit-def: $f12
; MIPS32-NEXT: jal f_float
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
call void @f_float(float undef)
ret void
}
declare void @f_double(double)
define void @g_double() {
; MIPS32-LABEL: g_double:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: # implicit-def: $d6
; MIPS32-NEXT: jal f_double
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
call void @f_double(double undef)
ret void
}

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/implicit_def.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
declare void @f_i32(i32)
define void @g_i32() {entry: ret void}
declare void @f_i64(i64)
define void @g_i64() {entry: ret void}
declare void @f_float(float)
define void @g_float() {entry: ret void}
declare void @f_double(double)
define void @g_double() {entry: ret void}
...
---
name: g_i32
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i32
; MIPS32: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[DEF]](s32)
; MIPS32: JAL @f_i32, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$a0 = COPY %0(s32)
JAL @f_i32, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_i64
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_i64
; MIPS32: [[DEF:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
; MIPS32: [[DEF1:%[0-9]+]]:gprb(s32) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[DEF]](s32)
; MIPS32: $a1 = COPY [[DEF1]](s32)
; MIPS32: JAL @f_i64, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s64) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
$a0 = COPY %1(s32)
$a1 = COPY %2(s32)
JAL @f_i64, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_float
alignment: 2
legalized: true
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_float
; MIPS32: [[DEF:%[0-9]+]]:fprb(s32) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $f12 = COPY [[DEF]](s32)
; MIPS32: JAL @f_float, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s32) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$f12 = COPY %0(s32)
JAL @f_float, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...
---
name: g_double
alignment: 2
legalized: true
tracksRegLiveness: true
registers:
body: |
bb.1.entry:
; MIPS32-LABEL: name: g_double
; MIPS32: [[DEF:%[0-9]+]]:fprb(s64) = G_IMPLICIT_DEF
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $d6 = COPY [[DEF]](s64)
; MIPS32: JAL @f_double, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: RetRA
%0:_(s64) = G_IMPLICIT_DEF
ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
$d6 = COPY %0(s64)
JAL @f_double, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6
ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
RetRA
...