[ARM][MVE] VCTP instruction selection

[samparker]

Summary

Add codegen support for vctp{8,16,32}.

[samparker]

I'm also wondering how this fits in with D67085...

[dmgreen]

In D67344#1662801, @samparker wrote:

I'm also wondering how this fits in with D67085...

Should be fine so long as they are not loading or storing anything (or can get it to not load or store anything!)

lib/Target/ARM/ARMInstrMVE.td

3946

Nitpicking: Indent!

test/CodeGen/Thumb2/mve-vctp.ll

2

Might as well add -verify-machineinstrs. Should the triple be in full (-none-eabi)? I'm not sure it matters a lot, but may default to linux otherwise.

Also I would just run the update script on a file this size.

25

It's probably best to use the <4 x i1> as opposed to returning it (in a vselect or something).

I'm not sure if the calling convention for a v4i1 is super very well defined. It's not defined from C, so only comes up in llvm test and if we can just sidestep that problem...

[samparker]

Thanks. Addressed comments.

[dmgreen]

LGTM

test/CodeGen/Thumb2/mve-vctp.ll

14

If you add arm_aapcs_vfpcc, you can pass the <16 x i8> vectors sanely are args/return values, if you want to remove the extra vldrs and vstrs.

lib/Target/ARM/ARMInstrMVE.td

   let DecoderMethod = "DecodeMveVCTP";
 }
 
 def MVE_VCTP8  : MVE_VCTP<"8",  0b00>;
 def MVE_VCTP16 : MVE_VCTP<"16", 0b01>;
 def MVE_VCTP32 : MVE_VCTP<"32", 0b10>;
 def MVE_VCTP64 : MVE_VCTP<"64", 0b11>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(int_arm_vctp8 rGPR:$Rn),
+            (v16i1 (MVE_VCTP8 rGPR:$Rn))>;
+  def : Pat<(int_arm_vctp16 rGPR:$Rn),
+            (v8i1 (MVE_VCTP16 rGPR:$Rn))>;
+  def : Pat<(int_arm_vctp32 rGPR:$Rn),
+            (v4i1 (MVE_VCTP32 rGPR:$Rn))>;
+}
+
 // end of mve_qDest_rSrc
 
 // start of coproc mov
 
 class MVE_VMOV_64bit<dag oops, dag iops, bit to_qreg, string ops, string cstr>
   : MVE_VMOV_lane_base<oops, !con(iops, (ins MVEPairVectorIndex2:$idx,
                                              MVEPairVectorIndex0:$idx2)),
                        NoItinerary, "vmov", "", ops, cstr, []> {

test/CodeGen/Thumb2/mve-vctp.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s
+
+define void @vctp8(i32 %arg, <16 x i8> *%in, <16 x i8>* %out) {
+; CHECK-LABEL: vctp8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q1, [r1]
+; CHECK-NEXT:    vctp.8 r0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vstrw.32 q0, [r2]
+; CHECK-NEXT:    bx lr
+  %pred = call <16 x i1> @llvm.arm.vctp8(i32 %arg)
+  %ld = load <16 x i8>, <16 x i8>* %in
+  %res = select <16 x i1> %pred, <16 x i8> %ld, <16 x i8> zeroinitializer
+  store <16 x i8> %res, <16 x i8>* %out
+  ret void
+}
+
+define void @vctp16(i32 %arg, <8 x i16> *%in, <8 x i16>* %out) {
+; CHECK-LABEL: vctp16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q1, [r1]
+; CHECK-NEXT:    vctp.16 r0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vstrw.32 q0, [r2]
+; CHECK-NEXT:    bx lr
+  %pred = call <8 x i1> @llvm.arm.vctp16(i32 %arg)
+  %ld = load <8 x i16>, <8 x i16>* %in
+  %res = select <8 x i1> %pred, <8 x i16> %ld, <8 x i16> zeroinitializer
+  store <8 x i16> %res, <8 x i16>* %out
+  ret void
+}
+
+define void @vctp32(i32 %arg, <4 x i32> *%in, <4 x i32>* %out) {
+; CHECK-LABEL: vctp32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q1, [r1]
+; CHECK-NEXT:    vctp.32 r0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vstrw.32 q0, [r2]
+; CHECK-NEXT:    bx lr
+  %pred = call <4 x i1> @llvm.arm.vctp32(i32 %arg)
+  %ld = load <4 x i32>, <4 x i32>* %in
+  %res = select <4 x i1> %pred, <4 x i32> %ld, <4 x i32> zeroinitializer
+  store <4 x i32> %res, <4 x i32>* %out
+  ret void
+}
+
+declare <16 x i1> @llvm.arm.vctp8(i32)
+declare <8 x i1> @llvm.arm.vctp16(i32)
+declare <4 x i1> @llvm.arm.vctp32(i32)