[GlobalISel][AArch64] Handle tail calls with non-void return types

[paquette]

Summary

Just return once you emit the call, which is exactly what SelectionDAG does in this situation.

Update call-translator-tail-call.ll to show that we now do this properly.

Also update dllimport.ll to show that we tail call here in GISel again. Add -verify-machineinstrs to the GISel line too, to defend against verifier failures.

[aemerson]

LGTM.

llvm/trunk/lib/Target/AArch64/AArch64CallLowering.cpp

if (Info.SwiftErrorVReg) {
     // TODO: We should handle this.
     // Note that this is also handled by the check for no outgoing arguments.
     // Proactively disabling this though, because the swifterror handling in
     // lowerCall inserts a COPY *after* the location of the call.
     LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
     return false;
   }
 
-  if (!Info.OrigRet.Ty->isVoidTy()) {
-    // TODO: lowerCall will insert COPYs to handle the call's return value.
-    // This needs some refactoring to avoid this with tail call returns. For
-    // now, just don't handle that case.
-    LLVM_DEBUG(dbgs() << "... Cannot handle non-void return types yet.\n");
-    return false;
-  }
-
   if (!mayTailCallThisCC(CalleeCC)) {
     LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
     return false;
   }
 
   if (Info.IsVarArg) {
     LLVM_DEBUG(dbgs() << "... Tail calling varargs not supported yet.\n");
     return false;
bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
   // instruction, it must have a register class matching the
   // constraint of that instruction.
   if (Info.Callee.isReg())
     MIB->getOperand(0).setReg(constrainOperandRegClass(
         MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
         0));
 
+  // If we're tail calling, then we're the return from the block. So, we don't
+  // want to copy anything.
+  if (IsSibCall)
+    return true;
+
   // Finally we can copy the returned value back into its virtual-register. In
   // symmetry with the arugments, the physical register must be an
   // implicit-define of the call instruction.
   CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
   if (!Info.OrigRet.Ty->isVoidTy()) {
     SplitArgs.clear();
 
     splitToValueTypes(Info.OrigRet, SplitArgs, DL, MRI, F.getCallingConv());
 
     CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
     if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
       return false;
   }
 
   if (Info.SwiftErrorVReg) {
     MIB.addDef(AArch64::X21, RegState::Implicit);
     MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
   }
 
-  if (!IsSibCall) {
-    // If we aren't sibcalling, we need to move the stack.
-    CallSeqStart.addImm(Handler.StackSize).addImm(0);
-    MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
-        .addImm(Handler.StackSize)
-        .addImm(0);
-  }
 
   return true;
 }

llvm/trunk/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll

 
 ; Right now, we don't want to tail call callees with nonvoid return types, since
 ; call lowering will insert COPYs after the call.
 ; TODO: Support this.
 declare i32 @nonvoid_ret()
 define i32 @test_nonvoid_ret() {
   ; COMMON-LABEL: name: test_nonvoid_ret
   ; COMMON: bb.1 (%ir-block.0):
-  ; COMMON:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
-  ; COMMON:   BL @nonvoid_ret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
-  ; COMMON:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
-  ; COMMON:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
-  ; COMMON:   $w0 = COPY [[COPY]](s32)
-  ; COMMON:   RET_ReallyLR implicit $w0
+  ; COMMON:   TCRETURNdi @nonvoid_ret, 0, csr_aarch64_aapcs, implicit $sp
   %call = tail call i32 @nonvoid_ret()
   ret i32 %call
 }
 
 ; Don't want to handle swifterror at all right now, since lowerCall will
 ; insert a COPY after the call right now.
 ; TODO: Support this.
 %swift_error = type {i64, i8}

llvm/trunk/test/CodeGen/AArch64/dllimport.ll

 ; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,DAG-ISEL
 ; RUN: llc -mtriple aarch64-unknown-windows-msvc -fast-isel -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,FAST-ISEL
-; RUN: llc -mtriple aarch64-unknown-windows-msvc -O0 -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,GLOBAL-ISEL,GLOBAL-ISEL-FALLBACK
+; RUN: llc -mtriple aarch64-unknown-windows-msvc -verify-machineinstrs -O0 -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,GLOBAL-ISEL,GLOBAL-ISEL-FALLBACK
 
 @var = external dllimport global i32
 @ext = external global i32
 declare dllimport i32 @external()
 declare i32 @internal()
 
 define i32 @get_var() {
   %1 = load i32, i32* @var, align 4

 define i32 @call_internal() {
   %call = tail call i32 @internal()
   ret i32 %call
 }
 
 ; CHECK-LABEL: call_internal
 ; DAG-ISEL: b internal
 ; FAST-ISEL: b internal
-; GLOBAL-ISEL: bl internal
+; GLOBAL-ISEL: b internal