AMDGPU: Make VReg_1 size be 1

[arsenm]

Summary

This was getting chosen as the preferred 32-bit register class based
on how TableGen selects subregister classes.

[rampitec]

lib/Target/AMDGPU/SILowerI1Copies.cpp

497

SReg_1 is also 1 bit, but not necessarily 32 on spill.

lib/Target/AMDGPU/SIRegisterInfo.td

685

This is spill size. How does that work when spill size if 1?

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.td

685

VReg_1 should never be seen by a spill. This could also be rounded when spilling

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.td

685

Why are you sure it will never be spilled?
Also if it is never spilled why is this field even matter?

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.td

685

Because this is a hack that exists for SelectionDAG. All uses should be eliminated in SILowerI1Copies. It matters because TableGen uses this as one of the sort and selection field. Without it, it picks VReg_1 instead of VGPR_32 as the preferred 32-bit register class

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.td

685

OK, makes sense. What about SReg_1 handling in the comment above, in the isRegister32()?

[arsenm]

lib/Target/AMDGPU/SIRegisterInfo.td

685

Contextually, I think that would already be illegal so I don't think this assert should worry about it. That would be a VGPR->SGPR copy that would error elsewhere

[rampitec]

lib/Target/AMDGPU/SIRegisterInfo.td

685

Assert probably fine, but the function is called isRegister32 and someone may eventually want to reuse it with unexpected consequences.

[arsenm]

Rename assert function

[rampitec]

LGTM

[arsenm]

r371438

lib/Target/AMDGPU/SILowerI1Copies.cpp

bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) {
 
   for (unsigned Reg : ConstrainRegs)
     MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass);
   ConstrainRegs.clear();
 
   return true;
 }
 
+#ifndef NDEBUG
+static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
+                                const MachineRegisterInfo &MRI,
+                                Register Reg) {
+  unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
+  return Size == 1 || Size == 32;
+}
+#endif
+
 void SILowerI1Copies::lowerCopiesFromI1() {
   SmallVector<MachineInstr *, 4> DeadCopies;
 
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB) {
       if (MI.getOpcode() != AMDGPU::COPY)
         continue;
 
       Register DstReg = MI.getOperand(0).getReg();
       Register SrcReg = MI.getOperand(1).getReg();
       if (!isVreg1(SrcReg))
         continue;
 
       if (isLaneMaskReg(DstReg) || isVreg1(DstReg))
         continue;
 
       // Copy into a 32-bit vector register.
       LLVM_DEBUG(dbgs() << "Lower copy from i1: " << MI);
       DebugLoc DL = MI.getDebugLoc();
 
-      assert(TII->getRegisterInfo().getRegSizeInBits(DstReg, *MRI) == 32);
+      assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));
       assert(!MI.getOperand(0).getSubReg());
 
       ConstrainRegs.insert(SrcReg);
       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
           .addImm(0)
           .addImm(0)
           .addImm(0)
           .addImm(-1)

lib/Target/AMDGPU/SIRegisterInfo.cpp

const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
   }
   return nullptr;
 }
 
 // TODO: It might be helpful to have some target specific flags in
 // TargetRegisterClass to mark which classes are VGPRs to make this trivial.
 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
   unsigned Size = getRegSizeInBits(*RC);
-  if (Size < 32)
-    return false;
   switch (Size) {
   case 32:
     return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
   case 64:
     return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr;
   case 96:
     return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr;
   case 128:
     return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr;
   case 160:
     return getCommonSubClass(&AMDGPU::VReg_160RegClass, RC) != nullptr;
   case 256:
     return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr;
   case 512:
     return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr;
   case 1024:
     return getCommonSubClass(&AMDGPU::VReg_1024RegClass, RC) != nullptr;
+  case 1:
+    return getCommonSubClass(&AMDGPU::VReg_1RegClass, RC) != nullptr;
   default:
-    llvm_unreachable("Invalid register class size");
+    assert(Size < 32 && "Invalid register class size");
+    return false;
   }
 }
 
 bool SIRegisterInfo::hasAGPRs(const TargetRegisterClass *RC) const {
   unsigned Size = getRegSizeInBits(*RC);
   if (Size < 32)
     return false;
   switch (Size) {
const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
   case 160:
     return &AMDGPU::VReg_160RegClass;
   case 256:
     return &AMDGPU::VReg_256RegClass;
   case 512:
     return &AMDGPU::VReg_512RegClass;
   case 1024:
     return &AMDGPU::VReg_1024RegClass;
+  case 1:
+    return &AMDGPU::VReg_1RegClass;
   default:
     llvm_unreachable("Invalid register class size");
   }
 }
 
 const TargetRegisterClass *SIRegisterInfo::getEquivalentAGPRClass(
                                          const TargetRegisterClass *SRC) const {
   switch (getRegSizeInBits(*SRC)) {

lib/Target/AMDGPU/SIRegisterInfo.td

 def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
                               (add AGPR_1024)> {
   let Size = 1024;
   let CopyCost = 65;
   let AllocationPriority = 8;
 }
 
 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
-  let Size = 32;
+  let Size = 1;
 }
 
 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
                           (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> {
   let isAllocatable = 0;
 }
 
 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {

test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir

bb.6:
     %12:vreg_128 = COPY %10
     S_BRANCH %bb.9
 
   bb.7:
     successors: %bb.8, %bb.10
     %25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
     %26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
     %27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    %28:vreg_1 = COPY %27
+    %28:vgpr_32 = COPY %27
     %29:sreg_64 = COPY $exec, implicit-def $exec
     %30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
     $exec = S_MOV_B64_term %30
     SI_MASK_BRANCH %bb.10, implicit $exec
     S_BRANCH %bb.8
 
   bb.8:
     successors: %bb.10
     %31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
     %34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
     %35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec
-    %28:vreg_1 = COPY %35
+    %28:vgpr_32 = COPY %35
     S_BRANCH %bb.10
 
   bb.9:
     successors: %bb.11
     S_BRANCH %bb.11
 
   bb.10:
     successors: %bb.9
     $exec = S_OR_B64 $exec, %29, implicit-def $scc
-    %36:vreg_1 = COPY %28
+    %36:vgpr_32 = COPY %28
     %37:sreg_64_xexec = V_CMP_NE_U32_e64 0, %36, implicit $exec
     %38:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %37, implicit $exec
     %39:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     undef %40.sub0:vreg_128 = COPY %39
     %40.sub1:vreg_128 = COPY %39
     %40.sub2:vreg_128 = COPY %38
     %41:vreg_128 = COPY %40
     %12:vreg_128 = COPY %41

test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir

bb.4:
     %33.sub1:vreg_128 = COPY undef %32
     %34:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
     %35:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %36:sreg_64 = COPY %24
     %37:vreg_128 = COPY %23
     %38:vreg_128 = IMPLICIT_DEF
     %39:vreg_128 = IMPLICIT_DEF
     %40:vgpr_32 = IMPLICIT_DEF
-    %41:vreg_1 = COPY killed %35
-    %42:vreg_1 = COPY killed %34
+    %41:vgpr_32 = COPY killed %35
+    %42:vgpr_32 = COPY killed %34
     %43:sreg_64 = COPY $exec, implicit-def $exec
     %44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
     %45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %44
     SI_MASK_BRANCH %bb.9, implicit $exec
     S_BRANCH %bb.8
 
   bb.5:
     successors: %bb.9(0x80000000)
     $exec = S_OR_B64 $exec, %46, implicit-def $scc
-    %47:vreg_1 = COPY killed %48
+    %47:vgpr_32 = COPY killed %48
     %49:vgpr_32 = COPY killed %50
     %51:vreg_128 = COPY killed %52
     %53:vreg_128 = COPY killed %54
     %55:sreg_64 = COPY killed %56
     %57:sreg_64 = S_AND_B64 $exec, %46, implicit-def $scc
     %57:sreg_64 = S_OR_B64 %57, killed %55, implicit-def $scc
     %58:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %36:sreg_64 = COPY killed %57
     %37:vreg_128 = COPY killed %53
     %38:vreg_128 = COPY killed %59
     %39:vreg_128 = COPY killed %51
     %40:vgpr_32 = COPY killed %49
-    %41:vreg_1 = COPY killed %47
-    %42:vreg_1 = COPY killed %58
+    %41:vgpr_32 = COPY killed %47
+    %42:vgpr_32 = COPY killed %58
     S_BRANCH %bb.9
 
   bb.6:
     successors: %bb.7(0x40000000), %bb.13(0x40000000)
     $exec = S_OR_B64 $exec, killed %60, implicit-def $scc
     %61:sreg_64 = V_CMP_NE_U32_e64 0, killed %62, implicit $exec
     %63:vreg_128 = COPY killed %64
-    %65:vreg_1 = COPY killed %66
+    %65:vgpr_32 = COPY killed %66
     %67:sreg_64 = COPY $exec, implicit-def $exec
     %68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %68
     SI_MASK_BRANCH %bb.13, implicit $exec
     S_BRANCH %bb.7
 
   bb.7:
     successors: %bb.13(0x80000000)
     %69:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
     %70:vreg_128 = COPY killed %33
     %63:vreg_128 = COPY killed %70
-    %65:vreg_1 = COPY killed %69
+    %65:vgpr_32 = COPY killed %69
     S_BRANCH %bb.13
 
   bb.8:
     successors: %bb.10(0x80000000)
     %71:sreg_64 = S_MOV_B64 0
     %72:vreg_128 = COPY %33
     %73:sreg_64 = COPY killed %71
     %74:vreg_128 = COPY killed %72
     %75:vreg_128 = COPY killed %29
     S_BRANCH %bb.10
 
   bb.9:
     successors: %bb.6(0x04000000), %bb.4(0x7c000000)
     $exec = S_OR_B64 $exec, %45, implicit-def $scc
-    %62:vreg_1 = COPY killed %42
-    %66:vreg_1 = COPY killed %41
+    %62:vgpr_32 = COPY killed %42
+    %66:vgpr_32 = COPY killed %41
     %76:vgpr_32 = COPY killed %40
     %77:vreg_128 = COPY killed %39
     %64:vreg_128 = COPY killed %38
     %78:vreg_128 = COPY killed %37
     %79:sreg_64 = COPY killed %36
     %60:sreg_64 = S_AND_B64 $exec, %45, implicit-def $scc
     %60:sreg_64 = S_OR_B64 %60, killed %79, implicit-def $scc
     %80:vreg_128 = COPY %78
bb.12:
     successors: %bb.15(0x40000000), %bb.5(0x40000000)
     $exec = S_OR_B64 $exec, killed %85, implicit-def $scc
     %87:sreg_64 = V_CMP_LT_U32_e64 11, killed %28, implicit $exec
     %88:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
     %56:sreg_64 = COPY %24
     %54:vreg_128 = COPY killed %23
     %52:vreg_128 = IMPLICIT_DEF
     %50:vgpr_32 = IMPLICIT_DEF
-    %48:vreg_1 = COPY killed %88
+    %48:vgpr_32 = COPY killed %88
     %89:sreg_64 = COPY $exec, implicit-def $exec
     %90:sreg_64 = S_AND_B64 %89, %87, implicit-def dead $scc
     %46:sreg_64 = S_XOR_B64 %90, %89, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %90
     SI_MASK_BRANCH %bb.5, implicit $exec
     S_BRANCH %bb.15
 
   bb.13:
     successors: %bb.14(0x40000000), %bb.16(0x40000000)
     $exec = S_OR_B64 $exec, killed %67, implicit-def $scc
-    %91:vreg_1 = COPY killed %65
+    %91:vgpr_32 = COPY killed %65
     %92:vreg_128 = COPY killed %63
     %93:sreg_64 = V_CMP_NE_U32_e64 0, killed %91, implicit $exec
     %94:vreg_128 = COPY killed %78
     %95:sreg_64 = COPY $exec, implicit-def $exec
     %96:sreg_64 = S_AND_B64 %95, %93, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %96
     SI_MASK_BRANCH %bb.16, implicit $exec
     S_BRANCH %bb.14
bb.15:
     %99:sreg_64 = V_CMP_NE_U32_e64 0, killed %22, implicit $exec
     %100:sreg_64 = S_OR_B64 killed %99, killed %24, implicit-def $scc
     %101:vreg_128 = COPY %59
     %102:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     %56:sreg_64 = COPY killed %100
     %54:vreg_128 = COPY killed %101
     %52:vreg_128 = COPY %59
     %50:vgpr_32 = COPY killed %102
-    %48:vreg_1 = COPY killed %98
+    %48:vgpr_32 = COPY killed %98
     S_BRANCH %bb.5
 
   bb.16:
     successors: %bb.3(0x80000000)
     $exec = S_OR_B64 $exec, killed %95, implicit-def $scc
     %103:vreg_128 = COPY killed %94
     %104:vreg_128 = COPY killed %103
     %5:vreg_128 = COPY killed %104

test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir

bb.2:
     dead %10:vgpr_32 = V_MAC_F32_e32 undef %11:vgpr_32, undef %12:vgpr_32, undef %10, implicit $exec
     undef %13.sub0:vreg_128 = COPY %9
     %14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
     S_CBRANCH_SCC0 %bb.4, implicit undef $scc
 
   bb.3:
     successors: %bb.6(0x80000000)
     %15:vreg_128 = IMPLICIT_DEF
-    %16:vreg_1 = COPY killed %14
+    %16:vgpr_32 = COPY killed %14
     S_BRANCH %bb.6
 
   bb.4:
     successors: %bb.5(0x40000000), %bb.7(0x40000000)
     %17:vgpr_32 = V_MAD_F32 0, killed %9, 0, 0, 0, 0, 0, 0, implicit $exec
     %18:vgpr_32 = V_MIN_F32_e32 1065353216, killed %17, implicit $exec
     %19:sreg_64_xexec = V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $exec
     %20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
     %21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, killed %20, killed %19, implicit $exec
     %22:sreg_64 = V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
     %23:sreg_64 = COPY $exec, implicit-def $exec
     %24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %24
     SI_MASK_BRANCH %bb.7, implicit $exec
     S_BRANCH %bb.5
 
   bb.5:
     successors: %bb.7(0x80000000)
     S_BRANCH %bb.7
 
   bb.6:
     successors: %bb.8(0x40000000), %bb.10(0x40000000)
-    %25:vreg_1 = COPY killed %16
+    %25:vgpr_32 = COPY killed %16
     %26:vreg_128 = COPY killed %15
     %27:sreg_64 = V_CMP_NE_U32_e64 0, killed %25, implicit $exec
     %28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
     $vcc = COPY killed %28
     %29:vreg_128 = COPY killed %26
     S_CBRANCH_VCCNZ %bb.8, implicit killed $vcc
     S_BRANCH %bb.10
 
   bb.7:
     successors: %bb.6(0x80000000)
     $exec = S_OR_B64 $exec, killed %23, implicit-def $scc
     %30:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %15:vreg_128 = COPY %13
-    %16:vreg_1 = COPY killed %30
+    %16:vgpr_32 = COPY killed %30
     S_BRANCH %bb.6
 
   bb.8:
     successors: %bb.9(0x40000000), %bb.11(0x40000000)
     %31:vreg_128 = COPY killed %13
     S_CBRANCH_SCC1 %bb.11, implicit undef $scc
     S_BRANCH %bb.9