[mips] Fix expanding `lw/sw $reg1, symbol($reg2)` instruction

[atanasyan]

Summary

When a "base" in the lw/sw $reg1, symbol($reg2) instruction is a register and generated code is position independent, backend does not add the "base" value to the symbol address.

lw     $reg1, %got(symbol)($gp)
lw/sw  $reg1, 0($reg1)

This patch fixes the bug and adds the missed addu instruction by passing BaseReg into the loadAndAddSymbolAddress routine and handles the case when the BaseReg is the zero register to escape redundant move reg, reg instruction:

lw     $reg1, %got(symbol)($gp)
addu   $reg1, $reg1, $reg2
lw/sw  $reg1, 0($reg1)

[Petar.Avramovic]

LGTM.

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 
 bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
                                             unsigned DstReg, unsigned SrcReg,
                                             bool Is32BitSym, SMLoc IDLoc,
                                             MCStreamer &Out,
                                             const MCSubtargetInfo *STI) {
   // FIXME: These expansions do not respect -mxgot.
   MipsTargetStreamer &TOut = getTargetStreamer();
-  bool UseSrcReg = SrcReg != Mips::NoRegister;
+  bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&
+                   SrcReg != Mips::ZERO_64;
   warnIfNoMacro(IDLoc);
 
   if (inPicMode() && ABI.IsO32()) {
     MCValue Res;
     if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
       Error(IDLoc, "expected relocatable expression");
       return true;
     }
if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
                    BaseReg, IDLoc, STI);
     TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI);
     return;
   }
 
   if (OffsetOp.isExpr()) {
     if (inPicMode()) {
       // FIXME:
-      // a) Fix lw/sw $reg, symbol($reg) instruction expanding.
       // c) Check that immediates of R_MIPS_GOT16/R_MIPS_LO16 relocations
       //    do not exceed 16-bit.
       // d) Use R_MIPS_GOT_PAGE/R_MIPS_GOT_OFST relocations instead
       //    of R_MIPS_GOT_DISP in appropriate cases to reduce number
       //    of GOT entries.
       MCValue Res;
       if (!OffsetOp.getExpr()->evaluateAsRelocatable(Res, nullptr, nullptr)) {
         Error(IDLoc, "expected relocatable expression");
         return;
       }
       if (Res.getSymB() != nullptr) {
         Error(IDLoc, "expected relocatable expression with only one symbol");
         return;
       }
 
-      loadAndAddSymbolAddress(Res.getSymA(), TmpReg, Mips::NoRegister,
+      loadAndAddSymbolAddress(Res.getSymA(), TmpReg, BaseReg,
                               !ABI.ArePtrs64bit(), IDLoc, Out, STI);
       TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, Res.getConstant(), IDLoc,
                    STI);
     } else {
       const MCExpr *ExprOffset = OffsetOp.getExpr();
       MCOperand LoOperand = MCOperand::createExpr(
           MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
       MCOperand HiOperand = MCOperand::createExpr(

llvm/trunk/test/MC/Mips/mips-expansions.s

 # CHECK-LE: sdc1    $f0, %lo(symbol)($1)
 
 # PIC code
   .option pic2
   .set noat
   lw $10, symbol($4)
 # CHECK-LE: lw      $10, %got(symbol)($gp)    # encoding: [A,A,0x8a,0x8f]
 # CHECK-LE:                                   #   fixup A - offset: 0, value: %got(symbol), kind: fixup_Mips_GOT
-# CHECK-LE-FIXME: addu    $10, $10, $4        # encoding: [0x21,0x50,0x44,0x01]
+# CHECK-LE: addu    $10, $10, $4              # encoding: [0x21,0x50,0x44,0x01]
 # CHECK-LE: lw      $10, 0($10)               # encoding: [0x00,0x00,0x4a,0x8d]
   .set at
   sw $10, symbol($9)
 # CHECK-LE: lw      $1, %got(symbol)($gp)     # encoding: [A,A,0x81,0x8f]
 # CHECK-LE:                                   #   fixup A - offset: 0, value: %got(symbol), kind: fixup_Mips_GOT
-# CHECK-LE-FIXME: addu    $1, $1, $9          # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: addu    $1, $1, $9                # encoding: [0x21,0x08,0x29,0x00]
 # CHECK-LE: sw      $10, 0($1)                # encoding: [0x00,0x00,0x2a,0xac]
 
   lw $8, 1f+8
 # CHECK-LE:      lw    $8, %got($tmp0)($gp)   # encoding: [A,A,0x88,0x8f]
 # CHECK-LE-NEXT:                              #   fixup A - offset: 0, value: %got($tmp0), kind: fixup_Mips_GOT
 # CHECK-LE-NEXT: addiu $8, $8, %lo($tmp0)     # encoding: [A,A,0x08,0x25]
 # CHECK-LE-NEXT:                              #   fixup A - offset: 0, value: %lo($tmp0), kind: fixup_Mips_LO16
 # CHECK-LE-NEXT: lw    $8, 8($8)              # encoding: [0x08,0x00,0x08,0x8d]

llvm/trunk/test/MC/Mips/mips64-expansions.s

 # CHECK-NEXT: daddu   $4, $4, $3
 # CHECK-NEXT: lhu     $4, -32764($4)
 
 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
   .option pic2
   lw $10, symbol($4)
 # CHECK: ld      $10, %got_disp(symbol)($gp) # encoding: [A,A,0x8a,0xdf]
 # CHECK:                                    #   fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
-# CHECK-FIXME: daddu   $10, $10, $4         # encoding: [0x2d,0x50,0x44,0x01]
+# CHECK: daddu   $10, $10, $4               # encoding: [0x2d,0x50,0x44,0x01]
 # CHECK: lw      $10, 0($10)                # encoding: [0x00,0x00,0x4a,0x8d]
   sw $10, symbol($9)
 # CHECK: ld      $1, %got_disp(symbol)($gp) # encoding: [A,A,0x81,0xdf]
 # CHECK:                                    #   fixup A - offset: 0, value: %got_disp(symbol), kind: fixup_Mips_GOT_DISP
-# CHECK-FIXME: daddu    $1, $1, $9          # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: daddu   $1, $1, $9                 # encoding: [0x2d,0x08,0x29,0x00]
 # CHECK: sw      $10, 0($1)                 # encoding: [0x00,0x00,0x2a,0xac]
 
   lw $8, sym+8
 # CHECK:      ld $8, %got_disp(sym)($gp)    # encoding: [A,A,0x88,0xdf]
 # CHECK-NEXT:                               #   fixup A - offset: 0, value: %got_disp(sym), kind: fixup_Mips_GOT_DISP
 # CHECK-NEXT: lw $8, 8($8)                  # encoding: [0x08,0x00,0x08,0x8d]
   sw $8, sym+8
 # CHECK:      ld $1, %got_disp(sym)($gp)    # encoding: [A,A,0x81,0xdf]