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[mips] Fix expanding `lw/sw $reg1, symbol($reg2)` instruction
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Authored by atanasyan on Wed, Aug 28, 9:54 AM.

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Summary

When a "base" in the lw/sw $reg1, symbol($reg2) instruction is a register and generated code is position independent, backend does not add the "base" value to the symbol address.

lw     $reg1, %got(symbol)($gp)
lw/sw  $reg1, 0($reg1)

This patch fixes the bug and adds the missed addu instruction by passing BaseReg into the loadAndAddSymbolAddress routine and handles the case when the BaseReg is the zero register to escape redundant move reg, reg instruction:

lw     $reg1, %got(symbol)($gp)
addu   $reg1, $reg1, $reg2
lw/sw  $reg1, 0($reg1)

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Repository
rL LLVM

Event Timeline

atanasyan created this revision.Wed, Aug 28, 9:54 AM
This revision is now accepted and ready to land.Thu, Aug 29, 3:37 AM
This revision was automatically updated to reflect the committed changes.