AMDGPU: Fix iterator error when lowering SI_END_CF

[arsenm]

Summary

If the instruction is the last in the block, there is no next
instruction but the iteration still needs to look at the new block.

[rampitec]

LGTM

[arsenm]

r369203

lib/Target/AMDGPU/SILowerControlFlow.cpp

private:
   unsigned XorTermrOpc;
   unsigned OrSaveExecOpc;
   unsigned Exec;
 
   void emitIf(MachineInstr &MI);
   void emitElse(MachineInstr &MI);
   void emitIfBreak(MachineInstr &MI);
   void emitLoop(MachineInstr &MI);
-  void emitEndCf(MachineInstr &MI);
+  MachineBasicBlock *emitEndCf(MachineInstr &MI);
 
   void findMaskOperands(MachineInstr &MI, unsigned OpNo,
                         SmallVectorImpl<MachineOperand> &Src) const;
 
   void combineMasks(MachineInstr &MI);
 
 public:
   static char ID;
static MachineBasicBlock *insertInstWithExecFallthrough(MachineBasicBlock &MBB,
   // All live-ins are forwarded.
   for (auto &LiveIn : MBB.liveins())
     SplitMBB->addLiveIn(LiveIn);
 
   MI.eraseFromParent();
   return SplitMBB;
 }
 
-void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
+MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {
   MachineBasicBlock &MBB = *MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
 
   MachineBasicBlock::iterator InsPt = MBB.begin();
 
   // First, move the instruction. It's unnecessarily difficult to update
   // LiveIntervals when there's a change in control flow, so move the
   // instruction before changing the blocks.
   MBB.splice(InsPt, &MBB, MI.getIterator());
   if (LIS)
     LIS->handleMove(MI);
 
   MachineFunction *MF = MBB.getParent();
 
   // Create instruction without inserting it yet.
   MachineInstr *NewMI
     = BuildMI(*MF, DL, TII->get(OrTermOpc), Exec)
     .addReg(Exec)
     .add(MI.getOperand(0));
-  insertInstWithExecFallthrough(MBB, MI, NewMI, DT, LIS, MLI);
+  return insertInstWithExecFallthrough(MBB, MI, NewMI, DT, LIS, MLI);
 }
 
 // Returns replace operands for a logical operation, either single result
 // for exec or two operands if source was another equivalent operation.
 void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
        SmallVectorImpl<MachineOperand> &Src) const {
   MachineOperand &Op = MI.getOperand(OpNo);
   if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) {
for (I = MBB->begin(), Last = MBB->end(); I != MBB->end(); I = Next) {
         break;
 
       case AMDGPU::SI_END_CF: {
         MachineInstr *NextMI = nullptr;
 
         if (Next != MBB->end())
           NextMI = &*Next;
 
-        emitEndCf(MI);
+        MBB = emitEndCf(MI);
 
         if (NextMI) {
           MBB = NextMI->getParent();
           Next = NextMI->getIterator();
           Last = MBB->end();
         }
 
         NextBB = std::next(MBB->getIterator());

test/CodeGen/AMDGPU/si-lower-control-flow.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=si-lower-control-flow -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN %s
 
 # Check that assert is not triggered
 
 ...
 ---
 name: si-lower-control-flow
 body: |
   bb.0:
     ; GCN-LABEL: name: si-lower-control-flow
     ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
-    ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0
+    ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 16, 0, 0
     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[S_LOAD_DWORD_IMM]], 255, implicit-def $scc
     ; GCN: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 65535, [[S_AND_B32_]], implicit-def $scc
     ; GCN: S_ENDPGM 0
     %0:sgpr_64 = COPY $sgpr4_sgpr5
     %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0, 0
     %2:sreg_32_xm0 = S_AND_B32 %1, 255, implicit-def $scc
     %3:sreg_32_xm0 = S_AND_B32 65535, %2, implicit-def $scc
     S_ENDPGM 0
body:             |
 
   bb.1:
     successors: %bb.2
 
   bb.2:
     S_ENDPGM 0
 
 ...
+
+---
+name: si_end_cf_lower_iterator_assert
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: si_end_cf_lower_iterator_assert
+  ; GCN: bb.0:
+  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; GCN:   liveins: $sgpr30_sgpr31
+  ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY killed $sgpr30_sgpr31
+  ; GCN:   [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
+  ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; GCN:   [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, 0, 0, killed [[DEF]], 0, implicit $exec
+  ; GCN:   [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
+  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], killed [[V_CMP_NEQ_F32_e64_]], implicit-def dead $scc
+  ; GCN:   $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+  ; GCN:   SI_MASK_BRANCH %bb.2, implicit $exec
+  ; GCN:   S_BRANCH %bb.1
+  ; GCN: bb.1:
+  ; GCN:   successors: %bb.2(0x80000000)
+  ; GCN: bb.2:
+  ; GCN:   successors: %bb.6(0x80000000)
+  ; GCN:   $exec = S_OR_B64_term $exec, killed [[COPY1]], implicit-def $scc
+  ; GCN: bb.6:
+  ; GCN:   successors: %bb.3(0x80000000)
+  ; GCN:   [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[S_MOV_B64_]], 0, 0, 0 :: (load 4, addrspace 4)
+  ; GCN: bb.3:
+  ; GCN:   successors: %bb.5(0x40000000), %bb.4(0x40000000)
+  ; GCN:   S_CMP_EQ_U32 killed [[S_LOAD_DWORD_IMM]], 1, implicit-def $scc
+  ; GCN:   S_CBRANCH_SCC1 %bb.5, implicit killed $scc
+  ; GCN:   S_BRANCH %bb.4
+  ; GCN: bb.4:
+  ; GCN:   successors: %bb.5(0x80000000)
+  ; GCN:   SI_MASKED_UNREACHABLE
+  ; GCN: bb.5:
+  ; GCN:   [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY killed [[COPY]]
+  ; GCN:   S_SETPC_B64_return killed [[COPY2]]
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: $sgpr30_sgpr31
+
+    %11:sreg_64 = COPY killed $sgpr30_sgpr31
+    %3:sreg_64 = S_MOV_B64 0
+    %7:vgpr_32 = IMPLICIT_DEF
+    %9:sreg_64 = V_CMP_NEQ_F32_e64 0, 0, 0, killed %7, 0, implicit $exec
+    %2:sreg_64 = SI_IF killed %9, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.1
+
+  bb.1:
+
+  bb.2:
+    %4:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed %3, 0, 0, 0 :: (load 4, addrspace 4)
+    SI_END_CF killed %2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+
+  bb.3:
+    S_CMP_EQ_U32 killed %4, 1, implicit-def $scc
+    S_CBRANCH_SCC1 %bb.5, implicit killed $scc
+    S_BRANCH %bb.4
+
+  bb.4:
+    SI_MASKED_UNREACHABLE
+
+  bb.5:
+    %12:ccr_sgpr_64 = COPY killed %11
+    S_SETPC_B64_return killed %12
+
+...