[AArch64][WinCFI] Do not pair callee-save instructions in LoadStoreOptimizer

[sdesmalen]

Summary

Prevent the LoadStoreOptimizer from pairing any load/store instructions with instructions from
the prologue/epilogue if the CFI information has encoded the operations as separate instructions.
This would otherwise lead to a mismatch of the actual prologue size from the size as recorded
in the Windows CFI.

[efriedma]

LGTM

test/CodeGen/AArch64/wineh1.mir

45 ↗

(On Diff #213646)

Please add a comment explaining what this is testing.

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/StackMaps.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/GlobalValue.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
if (MI.modifiesRegister(BaseReg, TRI))
       return false;
   }
 
   // Check if this load/store has a hint to avoid pair formation.
   // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
   if (isLdStPairSuppressed(MI))
     return false;
 
+  // Do not pair any callee-save store/reload instructions in the
+  // prologue/epilogue if the CFI information encoded the operations as separate
+  // instructions, as that will cause the size of the actual prologue to mismatch
+  // with the prologue size recorded in the Windows CFI.
+  const MCAsmInfo *MAI = MI.getMF()->getTarget().getMCAsmInfo();
+  bool NeedsWinCFI = MAI->usesWindowsCFI() &&
+                     MI.getMF()->getFunction().needsUnwindTableEntry();
+  if (NeedsWinCFI && (MI.getFlag(MachineInstr::FrameSetup) ||
+                      MI.getFlag(MachineInstr::FrameDestroy)))
+    return false;
+
   // On some CPUs quad load/store pairs are slower than two single load/stores.
   if (Subtarget.isPaired128Slow()) {
     switch (MI.getOpcode()) {
     default:
       break;
     case AArch64::LDURQi:
     case AArch64::STURQi:
     case AArch64::LDRQui:

llvm/trunk/test/CodeGen/AArch64/wineh1.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog -filetype=obj  \
 # RUN:   | llvm-readobj --unwind | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-windows -run-pass=aarch64-ldst-opt \
+# RUN:   | FileCheck %s --check-prefix=CHECK-LDSTOPT
 # This test case checks the basic validity of the .xdata section.  It's
 # documented at:
 # https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
 
 # We expect to see the following in the .xdata section:
 
 # CHECK:   ExceptionData {
-# CHECK-NEXT:      FunctionLength: 92
+# CHECK-NEXT:      FunctionLength: 96
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
 # CHECK-NEXT:      EpilogueScopes: 1
 # CHECK-NEXT:      ByteCodeLength: 28
 # CHECK-NEXT:      Prologue [
 # CHECK-NEXT:        0xc808              ; stp x19, x20, [sp, #64]
 # CHECK-NEXT:        0xd0c7              ; str x22, [sp, #56]
 # CHECK-NEXT:        0xd086              ; str x21, [sp, #48]
 # CHECK-NEXT:        0xc904              ; stp x23, x24, [sp, #32]
 # CHECK-NEXT:        0xc982              ; stp x25, x26, [sp, #16]
 # CHECK-NEXT:        0xce09              ; stp x27, x28, [sp, #-80]!
 # CHECK-NEXT:        0xe4                ; end
 # CHECK-NEXT:      ]
 # CHECK-NEXT:      EpilogueScopes [
 # CHECK-NEXT:        EpilogueScope {
-# CHECK-NEXT:          StartOffset: 15
+# CHECK-NEXT:          StartOffset: 16
 # CHECK-NEXT:          EpilogueStartIndex: 13
 # CHECK-NEXT:          Opcodes [
 # CHECK-NEXT:            0xc808              ; ldp x19, x20, [sp, #64]
 # CHECK-NEXT:            0xd086              ; ldr x21, [sp, #48]
 # CHECK-NEXT:            0xe3                ; nop
 # CHECK-NEXT:            0xd0c7              ; ldr x22, [sp, #56]
 # CHECK-NEXT:            0xc904              ; ldp x23, x24, [sp, #32]
 # CHECK-NEXT:            0xc982              ; ldp x25, x26, [sp, #16]
 # CHECK-NEXT:            0xce09              ; ldp x27, x28, [sp], #80
 # CHECK-NEXT:            0xe4                ; end
 # CHECK-NEXT:          ]
 # CHECK-NEXT:        }
 # CHECK-NEXT:      ]
 # CHECK-NEXT:    }
+
+# Check that the load-store optimizer does not merge the two
+# callee-saved stores in the prologue.
+# CHECK-LDSTOPT: name: test
+# CHECK-LDSTOPT: frame-setup STRXui killed $x21, $sp, 6
+# CHECK-LDSTOPT: frame-setup STRXui killed $x22, $sp, 7
 ...
 ---
 name:            test
 alignment:       2
 tracksRegLiveness: true
 hasWinCFI: true
 liveins:
   - { reg: '$w0' }

llvm/trunk/test/CodeGen/AArch64/wineh2.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-after=prologepilog \
 # RUN:    -filetype=obj | llvm-readobj --unwind | FileCheck %s
 # Test that the pre/post increment save of a flating point register is correct.
 
 # CHECK:        ExceptionData {
-# CHECK-NEXT:      FunctionLength: 136
+# CHECK-NEXT:      FunctionLength: 144
 # CHECK-NEXT:      Version: 0
 # CHECK-NEXT:      ExceptionData: No
 # CHECK-NEXT:      EpiloguePacked: No
 # CHECK-NEXT:      EpilogueScopes: 1
 # CHECK-NEXT:      ByteCodeLength: 40
 # CHECK-NEXT:      Prologue [
 # CHECK-NEXT:        0xc80e              ; stp x19, x20, [sp, #112]
 # CHECK-NEXT:        0xc88c              ; stp x21, x22, [sp, #96]
 # CHECK-NEXT:        0xc90a              ; stp x23, x24, [sp, #80]
 # CHECK-NEXT:        0xc988              ; stp x25, x26, [sp, #64]
 # CHECK-NEXT:        0xca06              ; stp x27, x28, [sp, #48]
 # CHECK-NEXT:        0xdc45              ; str d9, [sp, #40]
 # CHECK-NEXT:        0xdc04              ; str d8, [sp, #32]
 # CHECK-NEXT:        0xd882              ; stp d10, d11, [sp, #16]
 # CHECK-NEXT:        0xde8f              ; str d12, [sp, #-128]!
 # CHECK-NEXT:        0xe4                ; end
 # CHECK-NEXT:      ]
 # CHECK-NEXT:      EpilogueScopes [
 # CHECK-NEXT:        EpilogueScope {
-# CHECK-NEXT:          StartOffset: 25
+# CHECK-NEXT:          StartOffset: 26
 # CHECK-NEXT:          EpilogueStartIndex: 19
 # CHECK-NEXT:          Opcodes [
 # CHECK-NEXT:            0xc80e              ; ldp x19, x20, [sp, #112]
 # CHECK-NEXT:            0xc88c              ; ldp x21, x22, [sp, #96]
 # CHECK-NEXT:            0xc90a              ; ldp x23, x24, [sp, #80]
 # CHECK-NEXT:            0xc988              ; ldp x25, x26, [sp, #64]
 # CHECK-NEXT:            0xca06              ; ldp x27, x28, [sp, #48]
 # CHECK-NEXT:            0xdc04              ; ldr d8, [sp, #32]

llvm/trunk/test/DebugInfo/COFF/AArch64/arm64-register-variables.ll

 
 ; OBJ:   DefRangeRegisterRelSym {
 ; OBJ:     Kind: S_DEFRANGE_REGISTER_REL (0x1145)
 ; OBJ:     BaseRegister: ARM64_SP (0x51)
 ; OBJ:     HasSpilledUDTMember: No
 ; OBJ:     OffsetInParent: 0
 ; OBJ:     BasePointerOffset: 12
 ; OBJ:     LocalVariableAddrRange {
-; OBJ:       OffsetStart: .text+0x10
+; OBJ:       OffsetStart: .text+0x14
 ; OBJ:       ISectStart: 0x0
-; OBJ:       Range: 0x2C
+; OBJ:       Range: 0x30
 ; OBJ:     }
 ; OBJ:   }
 
 ; ModuleID = 't.cpp'
 source_filename = "test/DebugInfo/COFF/register-variables-arm64.ll"
 target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
 target triple = "arm64-unknown-windows-msvc19.16.27023"