Use MCRegister in MCRegisterInfo's interfaces

[dsanders]

Summary

As part of this, define DenseMapInfo for MCRegister (and Register while I'm at it)

Depends on D65599

[dsanders]

Previous patch was based off an earlier attempt at this. Correct it to be based on D65599

[arsenm]

llvm/include/llvm/MC/MCRegister.h

72 ↗

(On Diff #212933)

Why *37?

llvm/lib/Target/Hexagon/BitTracker.cpp

343 ↗

(On Diff #212933)

Result should be Register?

[dsanders]

llvm/include/llvm/MC/MCRegister.h

72 ↗

(On Diff #212933)

No idea. It's copied directly from the DenseMapInfo<unsigned> implementation

llvm/lib/Target/Hexagon/BitTracker.cpp

343 ↗

(On Diff #212933)

Sure, I can make that change too. The reason I had to modify this line is because the ? operator couldn't decide whether to cast the third operand from Register to unsigned, or the second from unsigned to Register as both conversions exist

[arsenm]

llvm/include/llvm/MC/MCRegister.h

72 ↗

(On Diff #212933)

Is it possible to implement this by calling the unsigned version?

[dsanders]

• Implement DenseMapInfo<MCRegister> via DenseMapInfo<unsigned> (and likewise for Register)
• Nit in Hexagon/BitTracker.cpp

[arsenm]

LGTM

llvm/trunk/include/llvm/CodeGen/Register.h

 
 /// Wrapper class representing virtual and physical registers. Should be passed
 /// by value.
 class Register {
   unsigned Reg;
 
 public:
   Register(unsigned Val = 0): Reg(Val) {}
+  Register(MCRegister Val): Reg(Val) {}
 
   // Register numbers can represent physical registers, virtual registers, and
   // sometimes stack slots. The unsigned values are divided into these ranges:
   //
   //   0           Not a register, can be used as a sentinel.
   //   [1;2^30)    Physical registers assigned by TableGen.
   //   [2^30;2^31) Stack slots. (Rarely used.)
   //   [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
operator MCRegister() const {
     return MCRegister(Reg);
   }
 
   bool isValid() const {
     return Reg != 0;
   }
 };
 
+// Provide DenseMapInfo for Register
+template<> struct DenseMapInfo<Register> {
+  static inline unsigned getEmptyKey() {
+    return DenseMapInfo<unsigned>::getEmptyKey();
+  }
+  static inline unsigned getTombstoneKey() {
+    return DenseMapInfo<unsigned>::getTombstoneKey();
+  }
+  static unsigned getHashValue(const unsigned &Val) {
+    return DenseMapInfo<unsigned>::getHashValue(Val);
+  }
+  static bool isEqual(const unsigned &LHS, const unsigned &RHS) {
+    return DenseMapInfo<unsigned>::isEqual(LHS, RHS);
+  }
+};
+
 }
 
 #endif // ifndef LLVM_CODEGEN_REGISTER_H

llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h

public:
   bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
       ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
 
   virtual const TargetRegisterClass *
   getConstrainedRegClassForOperand(const MachineOperand &MO,
                                    const MachineRegisterInfo &MRI) const {
     return nullptr;
   }
+
+  /// Returns the physical register number of sub-register "Index"
+  /// for physical register RegNo. Return zero if the sub-register does not
+  /// exist.
+  inline Register getSubReg(MCRegister Reg, unsigned Idx) const {
+    return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
+  }
 };
 
 //===----------------------------------------------------------------------===//
 //                           SuperRegClassIterator
 //===----------------------------------------------------------------------===//
 //
 // Iterate over the possible super-registers for a given register class. The
 // iterator will visit a list of pairs (Idx, Mask) corresponding to the

llvm/trunk/include/llvm/MC/MCRegister.h

 //===-- llvm/MC/Register.h --------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_REGISTER_H
 #define LLVM_MC_REGISTER_H
 
+#include "llvm/ADT/DenseMapInfo.h"
 #include <cassert>
 
 namespace llvm {
 
 /// Wrapper class representing physical registers. Should be passed by value.
 class MCRegister {
   unsigned Reg;
 
operator unsigned() const {
     return Reg;
   }
 
   bool isValid() const {
     return Reg != 0;
   }
 };
 
+// Provide DenseMapInfo for MCRegister
+template<> struct DenseMapInfo<MCRegister> {
+  static inline unsigned getEmptyKey() {
+    return DenseMapInfo<unsigned>::getEmptyKey();
+  }
+  static inline unsigned getTombstoneKey() {
+    return DenseMapInfo<unsigned>::getTombstoneKey();
+  }
+  static unsigned getHashValue(const unsigned &Val) {
+    return DenseMapInfo<unsigned>::getHashValue(Val);
+  }
+  static bool isEqual(const unsigned &LHS, const unsigned &RHS) {
+    return DenseMapInfo<unsigned>::isEqual(LHS, RHS);
+  }
+};
+
 }
 
 #endif // ifndef LLVM_MC_REGISTER_H

llvm/trunk/include/llvm/MC/MCRegisterInfo.h

public:
   struct SubRegCoveredBits {
     uint16_t Offset;
     uint16_t Size;
   };
 
 private:
   const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
   unsigned NumRegs;                           // Number of entries in the array
-  unsigned RAReg;                             // Return address register
-  unsigned PCReg;                             // Program counter register
+  MCRegister RAReg;                           // Return address register
+  MCRegister PCReg;                           // Program counter register
   const MCRegisterClass *Classes;             // Pointer to the regclass array
   unsigned NumClasses;                        // Number of entries in the array
   unsigned NumRegUnits;                       // Number of regunits.
   const MCPhysReg (*RegUnitRoots)[2];         // Pointer to regunit root table.
   const MCPhysReg *DiffLists;                 // Pointer to the difflists array
   const LaneBitmask *RegUnitMaskSequences;    // Pointer to lane mask sequences
                                               // for register units.
   const char *RegStrings;                     // Pointer to the string table.
private:
   unsigned L2DwarfRegsSize;
   unsigned EHL2DwarfRegsSize;
   unsigned Dwarf2LRegsSize;
   unsigned EHDwarf2LRegsSize;
   const DwarfLLVMRegPair *L2DwarfRegs;        // LLVM to Dwarf regs mapping
   const DwarfLLVMRegPair *EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
   const DwarfLLVMRegPair *Dwarf2LRegs;        // Dwarf to LLVM regs mapping
   const DwarfLLVMRegPair *EHDwarf2LRegs;      // Dwarf to LLVM regs mapping EH
-  DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
-  DenseMap<unsigned, int> L2CVRegs;           // LLVM to CV regs mapping
+  DenseMap<MCRegister, int> L2SEHRegs;        // LLVM to SEH regs mapping
+  DenseMap<MCRegister, int> L2CVRegs;         // LLVM to CV regs mapping
 
 public:
   /// DiffListIterator - Base iterator class that can traverse the
   /// differentially encoded register and regunit lists in DiffLists.
   /// Don't use this class directly, use one of the specialized sub-classes
   /// defined below.
   class DiffListIterator {
     uint16_t Val = 0;
protected:
     void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
       Val = InitVal;
       List = DiffList;
     }
 
     /// advance - Move to the next list position, return the applied
     /// differential. This function does not detect the end of the list, that
     /// is the caller's responsibility (by checking for a 0 return value).
-    unsigned advance() {
+    MCRegister advance() {
       assert(isValid() && "Cannot move off the end of the list.");
       MCPhysReg D = *List++;
       Val += D;
       return D;
     }
 
   public:
     /// isValid - returns true if this iterator is not yet at the end.
     bool isValid() const { return List; }
 
     /// Dereference the iterator to get the value at the current position.
-    unsigned operator*() const { return Val; }
+    MCRegister operator*() const { return Val; }
 
     /// Pre-increment to move to the next position.
     void operator++() {
       // The end of the list is encoded as a 0 differential.
       if (!advance())
         List = nullptr;
     }
   };
void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
     }
   }
 
   /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
   /// number mapping. By default the SEH register number is just the same
   /// as the LLVM register number.
   /// FIXME: TableGen these numbers. Currently this requires target specific
   /// initialization code.
-  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
+  void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
     L2SEHRegs[LLVMReg] = SEHReg;
   }
 
-  void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
+  void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
     L2CVRegs[LLVMReg] = CVReg;
   }
 
   /// This method should return the register where the return
   /// address can be found.
-  unsigned getRARegister() const {
+  MCRegister getRARegister() const {
     return RAReg;
   }
 
   /// Return the register which is the program counter.
-  unsigned getProgramCounter() const {
+  MCRegister getProgramCounter() const {
     return PCReg;
   }
 
-  const MCRegisterDesc &operator[](unsigned RegNo) const {
+  const MCRegisterDesc &operator[](MCRegister RegNo) const {
     assert(RegNo < NumRegs &&
            "Attempting to access record for invalid register number!");
     return Desc[RegNo];
   }
 
   /// Provide a get method, equivalent to [], but more useful with a
   /// pointer to this object.
-  const MCRegisterDesc &get(unsigned RegNo) const {
+  const MCRegisterDesc &get(MCRegister RegNo) const {
     return operator[](RegNo);
   }
 
   /// Returns the physical register number of sub-register "Index"
   /// for physical register RegNo. Return zero if the sub-register does not
   /// exist.
-  unsigned getSubReg(unsigned Reg, unsigned Idx) const;
+  MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
 
   /// Return a super-register of the specified register
   /// Reg so its sub-register of index SubIdx is Reg.
-  unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
+  MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
                                  const MCRegisterClass *RC) const;
 
   /// For a given register pair, return the sub-register index
   /// if the second register is a sub-register of the first. Return zero
   /// otherwise.
-  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
+  unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
 
   /// Get the size of the bit range covered by a sub-register index.
   /// If the index isn't continuous, return the sum of the sizes of its parts.
   /// If the index is used to access subregisters of different sizes, return -1.
   unsigned getSubRegIdxSize(unsigned Idx) const;
 
   /// Get the offset of the bit range covered by a sub-register index.
   /// If an Offset doesn't make sense (the index isn't continuous, or is used to
   /// access sub-registers at different offsets), return -1.
   unsigned getSubRegIdxOffset(unsigned Idx) const;
 
   /// Return the human-readable symbolic target-specific name for the
   /// specified physical register.
-  const char *getName(unsigned RegNo) const {
+  const char *getName(MCRegister RegNo) const {
     return RegStrings + get(RegNo).Name;
   }
 
   /// Return the number of registers this target has (useful for
   /// sizing arrays holding per register information)
   unsigned getNumRegs() const {
     return NumRegs;
   }
public:
   unsigned getNumRegUnits() const {
     return NumRegUnits;
   }
 
   /// Map a target register to an equivalent dwarf register
   /// number.  Returns -1 if there is no equivalent value.  The second
   /// parameter allows targets to use different numberings for EH info and
   /// debugging info.
-  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
+  int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
 
   /// Map a dwarf register back to a target register.
   int getLLVMRegNum(unsigned RegNum, bool isEH) const;
 
   /// Map a DWARF EH register back to a target register (same as
   /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
   /// rather than asserting that there must be one.
   int getLLVMRegNumFromEH(unsigned RegNum) const;
 
   /// Map a target EH register number to an equivalent DWARF register
   /// number.
   int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
 
   /// Map a target register to an equivalent SEH register
   /// number.  Returns LLVM register number if there is no equivalent value.
-  int getSEHRegNum(unsigned RegNum) const;
+  int getSEHRegNum(MCRegister RegNum) const;
 
   /// Map a target register to an equivalent CodeView register
   /// number.
-  int getCodeViewRegNum(unsigned RegNum) const;
+  int getCodeViewRegNum(MCRegister RegNum) const;
 
   regclass_iterator regclass_begin() const { return Classes; }
   regclass_iterator regclass_end() const { return Classes+NumClasses; }
   iterator_range<regclass_iterator> regclasses() const {
     return make_range(regclass_begin(), regclass_end());
   }
 
   unsigned getNumRegClasses() const {
     return (unsigned)(regclass_end()-regclass_begin());
   }
 
   /// Returns the register class associated with the enumeration
   /// value.  See class MCOperandInfo.
   const MCRegisterClass& getRegClass(unsigned i) const {
     assert(i < getNumRegClasses() && "Register Class ID out of range");
     return Classes[i];
   }
 
   const char *getRegClassName(const MCRegisterClass *Class) const {
     return RegClassStrings + Class->NameIdx;
   }
 
    /// Returns the encoding for RegNo
-  uint16_t getEncodingValue(unsigned RegNo) const {
+  uint16_t getEncodingValue(MCRegister RegNo) const {
     assert(RegNo < NumRegs &&
            "Attempting to get encoding for invalid register number!");
     return RegEncodingTable[RegNo];
   }
 
   /// Returns true if RegB is a sub-register of RegA.
-  bool isSubRegister(unsigned RegA, unsigned RegB) const {
+  bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
     return isSuperRegister(RegB, RegA);
   }
 
   /// Returns true if RegB is a super-register of RegA.
-  bool isSuperRegister(unsigned RegA, unsigned RegB) const;
+  bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
 
   /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
-  bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
+  bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
     return isSuperRegisterEq(RegB, RegA);
   }
 
   /// Returns true if RegB is a super-register of RegA or if
   /// RegB == RegA.
-  bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
+  bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
     return RegA == RegB || isSuperRegister(RegA, RegB);
   }
 
   /// Returns true if RegB is a super-register or sub-register of RegA
   /// or if RegB == RegA.
-  bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
+  bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
     return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
   }
 };
 
 //===----------------------------------------------------------------------===//
 //                          Register List Iterators
 //===----------------------------------------------------------------------===//
 
 // MCRegisterInfo provides lists of super-registers, sub-registers, and
 // aliasing registers. Use these iterator classes to traverse the lists.
 
 /// MCSubRegIterator enumerates all sub-registers of Reg.
 /// If IncludeSelf is set, Reg itself is included in the list.
 class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
 public:
-  MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
-                     bool IncludeSelf = false) {
+  MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
     init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
     // Initially, the iterator points to Reg itself.
     if (!IncludeSelf)
       ++*this;
   }
 };
 
 /// Iterator that enumerates the sub-registers of a Reg and the associated
 /// sub-register indices.
 class MCSubRegIndexIterator {
   MCSubRegIterator SRIter;
   const uint16_t *SRIndex;
 
 public:
   /// Constructs an iterator that traverses subregisters and their
   /// associated subregister indices.
-  MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
+  MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
     : SRIter(Reg, MCRI) {
     SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
   }
 
   /// Returns current sub-register.
-  unsigned getSubReg() const {
+  MCRegister getSubReg() const {
     return *SRIter;
   }
 
   /// Returns sub-register index of the current sub-register.
   unsigned getSubRegIndex() const {
     return *SRIndex;
   }
 
   /// Returns true if this iterator is not yet at the end.
   bool isValid() const { return SRIter.isValid(); }
 
   /// Moves to the next position.
   void operator++() {
     ++SRIter;
     ++SRIndex;
   }
 };
 
 /// MCSuperRegIterator enumerates all super-registers of Reg.
 /// If IncludeSelf is set, Reg itself is included in the list.
 class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
 public:
   MCSuperRegIterator() = default;
 
-  MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
+  MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
                      bool IncludeSelf = false) {
     init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
     // Initially, the iterator points to Reg itself.
     if (!IncludeSelf)
       ++*this;
   }
 };
 
 // Definition for isSuperRegister. Put it down here since it needs the
 // iterator defined above in addition to the MCRegisterInfo class itself.
-inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
+inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{
   for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
     if (*I == RegB)
       return true;
   return false;
 }
 
 //===----------------------------------------------------------------------===//
 //                               Register Units

 // MCRegUnitIterator enumerates a list of register units for Reg. The list is
 // in ascending numerical order.
 class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
 public:
   /// MCRegUnitIterator - Create an iterator that traverses the register units
   /// in Reg.
   MCRegUnitIterator() = default;
 
-  MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
+  MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
     assert(Reg && "Null register has no regunits");
     // Decode the RegUnits MCRegisterDesc field.
     unsigned RU = MCRI->get(Reg).RegUnits;
     unsigned Scale = RU & 15;
     unsigned Offset = RU >> 4;
 
     // Initialize the iterator to Reg * Scale, and the List pointer to
     // DiffLists + Offset.
class MCRegUnitMaskIterator {
   MCRegUnitIterator RUIter;
   const LaneBitmask *MaskListIter;
 
 public:
   MCRegUnitMaskIterator() = default;
 
   /// Constructs an iterator that traverses the register units and their
   /// associated LaneMasks in Reg.
-  MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
+  MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
     : RUIter(Reg, MCRI) {
       uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
       MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
   }
 
   /// Returns a (RegUnit, LaneMask) pair.
   std::pair<unsigned,LaneBitmask> operator*() const {
     return std::make_pair(*RUIter, *MaskListIter);
public:
   }
 };
 
 /// MCRegAliasIterator enumerates all registers aliasing Reg.  If IncludeSelf is
 /// set, Reg itself is included in the list.  This iterator does not guarantee
 /// any ordering or that entries are unique.
 class MCRegAliasIterator {
 private:
-  unsigned Reg;
+  MCRegister Reg;
   const MCRegisterInfo *MCRI;
   bool IncludeSelf;
 
   MCRegUnitIterator RI;
   MCRegUnitRootIterator RRI;
   MCSuperRegIterator SI;
 
 public:
-  MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
+  MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
                      bool IncludeSelf)
     : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
     // Initialize the iterators.
     for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
       for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
         for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
           if (!(!IncludeSelf && Reg == *SI))
             return;
         }
       }
     }
   }
 
   bool isValid() const { return RI.isValid(); }
 
-  unsigned operator*() const {
+  MCRegister operator*() const {
     assert(SI.isValid() && "Cannot dereference an invalid iterator.");
     return *SI;
   }
 
   void advance() {
     // Assuming SI is valid.
     ++SI;
     if (SI.isValid()) return;

llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp

for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
     unsigned Reg = Register::index2VirtReg(i);
     if (MRI.reg_nodbg_empty(Reg))
       continue;
     VRAI.calculateSpillWeightAndHint(LIS.getInterval(Reg));
   }
 }
 
 // Return the preferred allocation register for reg, given a COPY instruction.
-static unsigned copyHint(const MachineInstr *mi, unsigned reg,
+static Register copyHint(const MachineInstr *mi, unsigned reg,
                          const TargetRegisterInfo &tri,
                          const MachineRegisterInfo &mri) {
-  unsigned sub, hreg, hsub;
+  unsigned sub, hsub;
+  Register hreg;
   if (mi->getOperand(0).getReg() == reg) {
     sub = mi->getOperand(0).getSubReg();
     hreg = mi->getOperand(1).getReg();
     hsub = mi->getOperand(1).getSubReg();
   } else {
     sub = mi->getOperand(1).getSubReg();
     hreg = mi->getOperand(0).getReg();
     hsub = mi->getOperand(0).getSubReg();
   }
 
   if (!hreg)
     return 0;
 
   if (Register::isVirtualRegister(hreg))
-    return sub == hsub ? hreg : 0;
+    return sub == hsub ? hreg : Register();
 
   const TargetRegisterClass *rc = mri.getRegClass(reg);
-  unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
+  Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
   if (rc->contains(CopiedPReg))
     return CopiedPReg;
 
   // Check if reg:sub matches so that a super register could be hinted.
   if (sub)
     return tri.getMatchingSuperReg(CopiedPReg, sub, rc);
 
   return 0;

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO,
   bool Dead = MO.isDead();
   if (!MO.getSubReg()) {
     MO.setReg(PhysReg);
     MO.setIsRenamable(true);
     return MO.isKill() || Dead;
   }
 
   // Handle subregister index.
-  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
+  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
   MO.setIsRenamable(true);
   MO.setSubReg(0);
 
   // A kill flag implies killing the full register. Add corresponding super
   // register kill.
   if (MO.isKill()) {
     MI.addRegisterKilled(PhysReg, TRI, true);
     return true;

llvm/trunk/lib/MC/MCRegisterInfo.cpp

 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 
 using namespace llvm;
 
-unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
-                                             const MCRegisterClass *RC) const {
+MCRegister
+MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
   for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
     if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
       return *Supers;
   return 0;
 }
 
-unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
+MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
   assert(Idx && Idx < getNumSubRegIndices() &&
          "This is not a subregister index");
   // Get a pointer to the corresponding SubRegIndices list. This list has the
   // name of each sub-register in the same order as MCSubRegIterator.
   const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
   for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
     if (*SRI == Idx)
       return *Subs;
   return 0;
 }
 
-unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
+unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,
+                                        MCRegister SubReg) const {
   assert(SubReg && SubReg < getNumRegs() && "This is not a register");
   // Get a pointer to the corresponding SubRegIndices list. This list has the
   // name of each sub-register in the same order as MCSubRegIterator.
   const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
   for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
     if (*Subs == SubReg)
       return *SRI;
   return 0;
 }
 
 unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
   assert(Idx && Idx < getNumSubRegIndices() &&
          "This is not a subregister index");
   return SubRegIdxRanges[Idx].Size;
 }
 
 unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
   assert(Idx && Idx < getNumSubRegIndices() &&
          "This is not a subregister index");
   return SubRegIdxRanges[Idx].Offset;
 }
 
-int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
+int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
   const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
   unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
 
   if (!M)
     return -1;
   DwarfLLVMRegPair Key = { RegNum, 0 };
   const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
   if (I == M+Size || I->FromReg != RegNum)
int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
   // EH register number to an LLVM register number, assume it's just a
   // valid DWARF register number as is.
   int LRegNum = getLLVMRegNumFromEH(RegNum);
   if (LRegNum != -1)
     return getDwarfRegNum(LRegNum, false);
   return RegNum;
 }
 
-int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const {
-  const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
+int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const {
+  const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum);
   if (I == L2SEHRegs.end()) return (int)RegNum;
   return I->second;
 }
 
-int MCRegisterInfo::getCodeViewRegNum(unsigned RegNum) const {
+int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const {
   if (L2CVRegs.empty())
     report_fatal_error("target does not implement codeview register mapping");
-  const DenseMap<unsigned, int>::const_iterator I = L2CVRegs.find(RegNum);
+  const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum);
   if (I == L2CVRegs.end())
     report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
                                                            ? getName(RegNum)
                                                            : Twine(RegNum)));
   return I->second;
 }

llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
       .addReg(ScratchOffsetReg)
       .addImm(Offset);
 
     Offset = 0;
   }
 
   for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) {
     unsigned SubReg = NumSubRegs == 1 ?
-      ValueReg : getSubReg(ValueReg, getSubRegFromChannel(i));
+      Register(ValueReg) : getSubReg(ValueReg, getSubRegFromChannel(i));
 
     unsigned SOffsetRegState = 0;
     unsigned SrcDstRegState = getDefRegState(!IsStore);
     if (i + 1 == e) {
       SOffsetRegState |= getKillRegState(Scavenged);
       // The last implicit use carries the "Kill" flag.
       SrcDstRegState |= getKillRegState(IsKill);
     }
bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
   bool SpillToVGPR = !VGPRSpills.empty();
   if (OnlyToVGPR && !SpillToVGPR)
     return false;
 
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const GCNSubtarget &ST =  MF->getSubtarget<GCNSubtarget>();
   const SIInstrInfo *TII = ST.getInstrInfo();
 
-  unsigned SuperReg = MI->getOperand(0).getReg();
+  Register SuperReg = MI->getOperand(0).getReg();
   bool IsKill = MI->getOperand(0).isKill();
   const DebugLoc &DL = MI->getDebugLoc();
 
   MachineFrameInfo &FrameInfo = MF->getFrameInfo();
 
   bool SpillToSMEM = spillSGPRToSMEM();
   if (SpillToSMEM && OnlyToVGPR)
     return false;
bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
   if (OnlyToVGPR && !SpillToVGPR)
     return false;
 
   MachineFrameInfo &FrameInfo = MF->getFrameInfo();
   const GCNSubtarget &ST =  MF->getSubtarget<GCNSubtarget>();
   const SIInstrInfo *TII = ST.getInstrInfo();
   const DebugLoc &DL = MI->getDebugLoc();
 
-  unsigned SuperReg = MI->getOperand(0).getReg();
+  Register SuperReg = MI->getOperand(0).getReg();
   bool SpillToSMEM = spillSGPRToSMEM();
   if (SpillToSMEM && OnlyToVGPR)
     return false;
 
   assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
 
   unsigned OffsetReg = AMDGPU::M0;
   unsigned M0CopyReg = AMDGPU::NoRegister;

llvm/trunk/lib/Target/Hexagon/BitTracker.cpp

uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
   // 1. find a physical register PhysR from the same class as RR.Reg,
   // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
   // 3. find a register class that contains PhysS.
   if (Register::isVirtualRegister(RR.Reg)) {
     const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
     return TRI.getRegSizeInBits(VC);
   }
   assert(Register::isPhysicalRegister(RR.Reg));
-  unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
+  Register PhysR =
+      (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub);
   return getPhysRegBitWidth(PhysR);
 }
 
 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
       const CellMapType &M) const {
   uint16_t BW = getRegBitWidth(RR);
 
   // Physical registers are assumed to be present in the map with an unknown

llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp

 
 /// Get the opcode for a conditional transfer of the value in SO (source
 /// operand). The condition (true/false) is given in Cond.
 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
       bool IfTrue) {
   using namespace Hexagon;
 
   if (SO.isReg()) {
-    unsigned PhysR;
+    Register PhysR;
     RegisterRef RS = SO;
     if (Register::isVirtualRegister(RS.Reg)) {
       const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
       assert(VC->begin() != VC->end() && "Empty register class");
       PhysR = *VC->begin();
     } else {
       assert(Register::isPhysicalRegister(RS.Reg));
       PhysR = RS.Reg;