[MCA] Add support for printing immedate values as hex. Also enable lexing of masm binary and hex literals.

[andreadb]

Summary

This patch adds a new llvm-mca flag named -print-imm-hex.

By default, the instruction printer prints immediate operands as decimals. Flag -print-imm-hex enables the instruction printer to print those operands in hex.

This patch also adds support for MASM binary and hex literal numbers (example 0FFh, 101b).
Added tests to verify the behavior of the new flag. Tests also verify that masm numeric literal operands are now recognized.

Please let me know if okay to commit.

[lebedev.ri]

tools/llvm-mca/llvm-mca.cpp

93 ↗

(On Diff #212836)

for *outputting* immediate values
This has no effect on input, right?

[andreadb]

tools/llvm-mca/llvm-mca.cpp

93 ↗

(On Diff #212836)

Correct.

I can change it to "Prefer hex format for outputting immediate values".
Alternatively, I could write "Prefer hex format when printing immediate values".
Not sure which one is better.

[lebedev.ri]

tools/llvm-mca/llvm-mca.cpp

93 ↗

(On Diff #212836)

"Prefer hex format when printing immediate values" IMHO

[andreadb]

Addressed review comment.

[lebedev.ri]

Looks ok i guess.

llvm/trunk/docs/CommandGuide/llvm-mca.rst

 
 .. option:: -output-asm-variant=<variant id>
 
  Specify the output assembly variant for the report generated by the tool.
  On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables
  the AT&T (vic. Intel) assembly format for the code printed out by the tool in
  the analysis report.
 
+.. option:: -print-imm-hex
+
+ Prefer hex format for numeric literals in the output assembly printed as part
+ of the report.
+
 .. option:: -dispatch=<width>
 
  Specify a different dispatch width for the processor. The dispatch width
  defaults to field 'IssueWidth' in the processor scheduling model.  If width is
  zero, then the default dispatch width is used.
 
 .. option:: -register-file-size=<size>
 

llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-1.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info < %s | FileCheck %s --check-prefixes=ALL,DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=false < %s | FileCheck %s --check-prefixes=ALL,DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex < %s | FileCheck %s --check-prefixes=ALL,HEX
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=true < %s | FileCheck %s --check-prefixes=ALL,HEX
+
+  shl $5,    %eax
+  shl $0x5,  %eax
+  shl $5h,   %eax
+  shl $101b, %eax
+
+# ALL:          Instruction Info:
+# ALL-NEXT:     [1]: #uOps
+# ALL-NEXT:     [2]: Latency
+# ALL-NEXT:     [3]: RThroughput
+# ALL-NEXT:     [4]: MayLoad
+# ALL-NEXT:     [5]: MayStore
+# ALL-NEXT:     [6]: HasSideEffects (U)
+
+# ALL:          [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+
+# DEFAULT-NEXT:  1      1     0.50                        shll  $5, %eax
+# DEFAULT-NEXT:  1      1     0.50                        shll  $5, %eax
+# DEFAULT-NEXT:  1      1     0.50                        shll  $5, %eax
+# DEFAULT-NEXT:  1      1     0.50                        shll  $5, %eax
+
+# HEX-NEXT:      1      1     0.50                        shll  $0x5, %eax
+# HEX-NEXT:      1      1     0.50                        shll  $0x5, %eax
+# HEX-NEXT:      1      1     0.50                        shll  $0x5, %eax
+# HEX-NEXT:      1      1     0.50                        shll  $0x5, %eax

llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-2.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info < %s | FileCheck %s --check-prefix=DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=false < %s | FileCheck %s --check-prefix=DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex < %s | FileCheck %s --check-prefix=HEX
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=true < %s | FileCheck %s --check-prefix=HEX
+
+  .intel_syntax noprefix
+  shl eax, 8
+  shl eax, 0x8
+  shl eax, 8h
+  shl eax, 1000b
+
+# DEFAULT:      Instruction Info:
+# DEFAULT-NEXT: [1]: #uOps
+# DEFAULT-NEXT: [2]: Latency
+# DEFAULT-NEXT: [3]: RThroughput
+# DEFAULT-NEXT: [4]: MayLoad
+# DEFAULT-NEXT: [5]: MayStore
+# DEFAULT-NEXT: [6]: HasSideEffects (U)
+
+# HEX:          Instruction Info:
+# HEX-NEXT:     [1]: #uOps
+# HEX-NEXT:     [2]: Latency
+# HEX-NEXT:     [3]: RThroughput
+# HEX-NEXT:     [4]: MayLoad
+# HEX-NEXT:     [5]: MayStore
+# HEX-NEXT:     [6]: HasSideEffects (U)
+
+# DEFAULT:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# DEFAULT-NEXT:  1      1     0.50                        shl eax, 8
+# DEFAULT-NEXT:  1      1     0.50                        shl eax, 8
+# DEFAULT-NEXT:  1      1     0.50                        shl eax, 8
+# DEFAULT-NEXT:  1      1     0.50                        shl eax, 8
+
+# HEX:          [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# HEX-NEXT:      1      1     0.50                        shl eax, 0x8
+# HEX-NEXT:      1      1     0.50                        shl eax, 0x8
+# HEX-NEXT:      1      1     0.50                        shl eax, 0x8
+# HEX-NEXT:      1      1     0.50                        shl eax, 0x8

llvm/trunk/tools/llvm-mca/CodeRegionGenerator.cpp

Expected<const CodeRegions &> AsmCodeRegionGenerator::parseCodeRegions() {
 
   // Create a MCAsmParser and setup the lexer to recognize llvm-mca ASM
   // comments.
   std::unique_ptr<MCAsmParser> Parser(
       createMCAsmParser(Regions.getSourceMgr(), Ctx, Str, MAI));
   MCAsmLexer &Lexer = Parser->getLexer();
   MCACommentConsumer CC(Regions);
   Lexer.setCommentConsumer(&CC);
+  // Enable support for MASM literal numbers (example: 05h, 101b).
+  Lexer.setLexMasmIntegers(true);
 
   std::unique_ptr<MCTargetAsmParser> TAP(
       TheTarget.createMCAsmParser(STI, *Parser, MCII, Opts));
   if (!TAP)
     return make_error<StringError>(
         "This target does not support assembly parsing.",
         inconvertibleErrorCode());
   Parser->setTargetParser(*TAP);

llvm/trunk/tools/llvm-mca/llvm-mca.cpp

MCPU("mcpu",
          cl::desc("Target a specific cpu type (-mcpu=help for details)"),
          cl::value_desc("cpu-name"), cl::cat(ToolOptions), cl::init("native"));
 
 static cl::opt<int>
     OutputAsmVariant("output-asm-variant",
                      cl::desc("Syntax variant to use for output printing"),
                      cl::cat(ToolOptions), cl::init(-1));
 
+static cl::opt<bool>
+    PrintImmHex("print-imm-hex", cl::cat(ToolOptions), cl::init(false),
+                cl::desc("Prefer hex format when printing immediate values"));
+
 static cl::opt<unsigned> Iterations("iterations",
                                     cl::desc("Number of iterations to run"),
                                     cl::cat(ToolOptions), cl::init(0));
 
 static cl::opt<unsigned>
     DispatchWidth("dispatch", cl::desc("Override the processor dispatch width"),
                   cl::cat(ToolOptions), cl::init(0));
 
int main(int argc, char **argv) {
   if (!IP) {
     WithColor::error()
         << "unable to create instruction printer for target triple '"
         << TheTriple.normalize() << "' with assembly variant "
         << AssemblerDialect << ".\n";
     return 1;
   }
 
+  // Set the display preference for hex vs. decimal immediates.
+  IP->setPrintImmHex(PrintImmHex);
+
   std::unique_ptr<ToolOutputFile> TOF = std::move(*OF);
 
   const MCSchedModel &SM = STI->getSchedModel();
 
   // Create an instruction builder.
   mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
 
   // Create a context to control ownership of the pipeline hardware.