[InstCombine] simplify a cmp+select using binop result equivalence

[spatel]

Summary

As discussed in PR42696:
https://bugs.llvm.org/show_bug.cgi?id=42696
...but won't help that case yet.

We have an odd situation where a select equivalence fold was implemented in InstSimplify when it could have been done more generally in InstCombine if we allow dropping of {nsw,nuw,exact} from a binop operand.

Here's an example:
https://rise4fun.com/Alive/Xplr

%cmp = icmp eq i32 %x, 2147483647
%add = add nsw i32 %x, 1
%sel = select i1 %cmp, i32 -2147483648, i32 %add
=>
%sel = add i32 %x, 1

I've left the InstSimplify code in place for now, but my guess is that we'd prefer to remove that as a follow-up to save on code duplication and compile-time.

[spatel]

Patch updated:
There was a bug in translating the code from instsimplify. Added tests (rL367577, rL367579) to make sure we are propagating the correct T/F arm of the select with swapped operands and 'ne' predicate.

[lebedev.ri]

I'm having trouble grasping all that code duplication.
Can that be generalized+parametrized a bit?
Also, please can you add the example with explanation into that function?

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

1091

Sure not <Instruction> ?

[spatel]

In D65576#1611024, @lebedev.ri wrote:

I'm having trouble grasping all that code duplication.
Can that be generalized+parametrized a bit?
Also, please can you add the example with explanation into that function?

Agree - I was afraid of introducing a bug while copy/pasting this from the InstSimplify blob, so amplified the existing mess...and managed to introduce a bug anyway.
I'll shrink it and add more comments. Interestingly, the existing tests show that we're missing some wrapping analysis by performing the transform in instsimplify (ie, the test names suggesting what is or isn't safe might be bogus).

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

1091

Yes - it's limited to BinOps for the moment, but that may change.

[spatel]

Patch updated:

1. Simplified code.
2. Added examples to code comments.
3. Changed dyn_cast from BinaryOperator to more general Instruction.

[lebedev.ri]

Thanks, now it makes sense!
Looks good to me.

llvm/lib/Analysis/InstructionSimplify.cpp

static const Value *SimplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp,
   // If this is a binary operator, try to simplify it with the replaced op.
   if (auto *B = dyn_cast<BinaryOperator>(I)) {
     // Consider:
     //   %cmp = icmp eq i32 %x, 2147483647
     //   %add = add nsw i32 %x, 1
     //   %sel = select i1 %cmp, i32 -2147483648, i32 %add
     //
     // We can't replace %sel with %add unless we strip away the flags.
+    // TODO: This is an unusual limitation because better analysis results in
+    //       worse simplifiction. InstCombine can do this fold more generally by
+    //       dropping the flags. Remove this fold to save compile-time?
     if (isa<OverflowingBinaryOperator>(B))
       if (Q.IIQ.hasNoSignedWrap(B) || Q.IIQ.hasNoUnsignedWrap(B))
         return nullptr;
     if (isa<PossiblyExactOperator>(B) && Q.IIQ.isExact(B))
       return nullptr;
 
     if (MaxRecurse) {
       if (B->getOperand(0) == Op)

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

static Instruction *canonicalizeAbsNabs(SelectInst &Sel, ICmpInst &Cmp,
   }
 
   // We are swapping the select operands, so swap the metadata too.
   Sel.swapValues();
   Sel.swapProfMetadata();
   return &Sel;
 }
 
+static Value *simplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp,
+                                     const SimplifyQuery &Q) {
+  // If this is a binary operator, try to simplify it with the replaced op.
+  if (auto *BO = dyn_cast<BinaryOperator>(V)) {
+    if (BO->getOperand(0) == Op)
+      return SimplifyBinOp(BO->getOpcode(), RepOp, BO->getOperand(1), Q);
+    if (BO->getOperand(1) == Op)
+      return SimplifyBinOp(BO->getOpcode(), BO->getOperand(0), RepOp, Q);
+  }
+
+  return nullptr;
+}
+
+/// If we have a select with an equality comparison, then we know the value in
+/// one of the arms of the select. See if substituting this value into the arm
+/// and simplifying the result yields the same value as the other arm.
+/// To make this transform safe, we must drop poison-generating flags
+/// (nsw, etc) if we simplified to a binop because the select may be guarding
+/// that poison from propagating. If the existing binop already had no
+/// poison-generating flags, then this transform can be done by instsimplify.
+static Value *foldSelectBinopEquivalence(SelectInst &Sel, ICmpInst &Cmp,
+                                         const SimplifyQuery &Q) {
+  Value *TrueVal = Sel.getTrueValue(), *FalseVal = Sel.getFalseValue();
+  Value *CmpLHS = Cmp.getOperand(0), *CmpRHS = Cmp.getOperand(1);
+  ICmpInst::Predicate Pred = Cmp.getPredicate();
+  if (Pred == ICmpInst::ICMP_EQ) {
+    if (simplifyWithOpReplaced(FalseVal, CmpLHS, CmpRHS, Q) == TrueVal ||
+        simplifyWithOpReplaced(FalseVal, CmpRHS, CmpLHS, Q) == TrueVal) {
+      if (auto *B = dyn_cast<BinaryOperator>(FalseVal))
+        B->dropPoisonGeneratingFlags();
+      return FalseVal;
+    }
+    if (simplifyWithOpReplaced(TrueVal, CmpLHS, CmpRHS, Q) == FalseVal ||
+        simplifyWithOpReplaced(TrueVal, CmpRHS, CmpLHS, Q) == FalseVal) {
+      if (auto *B = dyn_cast<BinaryOperator>(FalseVal))
+        B->dropPoisonGeneratingFlags();
+      return FalseVal;
+    }
+  } else if (Pred == ICmpInst::ICMP_NE) {
+    if (simplifyWithOpReplaced(TrueVal, CmpLHS, CmpRHS, Q) == FalseVal ||
+        simplifyWithOpReplaced(TrueVal, CmpRHS, CmpLHS, Q) == FalseVal) {
+      if (auto *B = dyn_cast<BinaryOperator>(TrueVal))
+        B->dropPoisonGeneratingFlags();
+      return TrueVal;
+    }
+    if (simplifyWithOpReplaced(FalseVal, CmpLHS, CmpRHS, Q) == TrueVal ||
+        simplifyWithOpReplaced(FalseVal, CmpRHS, CmpLHS, Q) == TrueVal) {
+      if (auto *B = dyn_cast<BinaryOperator>(TrueVal))
+        B->dropPoisonGeneratingFlags();
+      return TrueVal;
+    }
+  }
+  return nullptr;
+}
+
 /// Visit a SelectInst that has an ICmpInst as its first operand.
 Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI,
                                                   ICmpInst *ICI) {
-  Value *TrueVal = SI.getTrueValue();
-  Value *FalseVal = SI.getFalseValue();
+  if (Value *V = foldSelectBinopEquivalence(SI, *ICI, SQ))
+    return replaceInstUsesWith(SI, V);
 
   if (Instruction *NewSel = canonicalizeMinMaxWithConstant(SI, *ICI, Builder))
     return NewSel;
 
   if (Instruction *NewAbs = canonicalizeAbsNabs(SI, *ICI, Builder))
     return NewAbs;
 
   bool Changed = adjustMinMax(SI, *ICI);
 
   if (Value *V = foldSelectICmpAnd(SI, ICI, Builder))
     return replaceInstUsesWith(SI, V);
 
   // NOTE: if we wanted to, this is where to detect integer MIN/MAX
+  Value *TrueVal = SI.getTrueValue();
+  Value *FalseVal = SI.getFalseValue();
   ICmpInst::Predicate Pred = ICI->getPredicate();
   Value *CmpLHS = ICI->getOperand(0);
   Value *CmpRHS = ICI->getOperand(1);
   if (CmpRHS != CmpLHS && isa<Constant>(CmpRHS)) {
     if (CmpLHS == TrueVal && Pred == ICmpInst::ICMP_EQ) {
       // Transform (X == C) ? X : Y -> (X == C) ? C : Y
       SI.setOperand(1, CmpRHS);
       Changed = true;

llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
 define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
 ; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 15
   %2 = shl nuw nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
;
   %4 = icmp eq i32 %2, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
 ; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 60
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 60
   %2 = lshr i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
;
   %4 = icmp eq i32 %2, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
 ; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
-; CHECK-NEXT:    [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, -2147483588
   %2 = ashr i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6

llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
 define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 15
   %2 = shl nuw nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nuw__all_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 15
   %2 = shl nuw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nsw__all_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 15
   %2 = shl nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl__all_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl__all_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 15
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 60
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 15
   %2 = shl i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 1073741822
   %2 = shl nuw nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 1073741822
   %2 = shl nuw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 1073741822
   %2 = shl nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl__nuw_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 1073741822
   %2 = shl i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
-; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
-; CHECK-NEXT:    ret i32 [[TMP6]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %1 = or i32 %x, -83886080
   %2 = icmp eq i32 %1, -83886079
   %3 = shl nuw nsw i32 %1, 2
   %4 = select i1 %2, i32 -335544316, i32 %3
   %5 = mul i32 %4, %1
   %6 = mul i32 %5, %3
   ret i32 %6
 }
 
 define i32 @test_shl_nuw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_shl_nuw__nsw_is_safe(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
-; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
-; CHECK-NEXT:    ret i32 [[TMP6]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %1 = or i32 %x, -83886080
   %2 = icmp eq i32 %1, -83886079
   %3 = shl nuw i32 %1, 2
   %4 = select i1 %2, i32 -335544316, i32 %3
   %5 = mul i32 %4, %1
   %6 = mul i32 %5, %3
   ret i32 %6
 }
 
 define i32 @test_shl_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_shl_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
-; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
-; CHECK-NEXT:    ret i32 [[TMP6]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %1 = or i32 %x, -83886080
   %2 = icmp eq i32 %1, -83886079
   %3 = shl nsw i32 %1, 2
   %4 = select i1 %2, i32 -335544316, i32 %3
   %5 = mul i32 %4, %1
   %6 = mul i32 %5, %3
   ret i32 %6
 }
 
 define i32 @test_shl__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_shl__nsw_is_safe(
 ; CHECK-NEXT:    [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], -83886079
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP2]], i32 -335544316, i32 [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP1]]
-; CHECK-NEXT:    [[TMP6:%.*]] = mul i32 [[TMP5]], [[TMP3]]
-; CHECK-NEXT:    ret i32 [[TMP6]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]]
+; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %1 = or i32 %x, -83886080
   %2 = icmp eq i32 %1, -83886079
   %3 = shl i32 %1, 2
   %4 = select i1 %2, i32 -335544316, i32 %3
   %5 = mul i32 %4, %1
   %6 = mul i32 %5, %3
   ret i32 %6
 }
 
 
 define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 4294967294
   %2 = shl nuw nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nuw__none_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 4294967294
   %2 = shl nuw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_shl_nsw__none_are_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2
-; CHECK-NEXT:    [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -8
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 4294967294
   %2 = shl nsw i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
;
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_lshr_exact__exact_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 60
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 60
   %2 = lshr exact i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_lshr__exact_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 60
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 60
   %2 = lshr i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 63
-; CHECK-NEXT:    [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 15
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, 63
   %2 = lshr exact i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
;
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
-; CHECK-NEXT:    [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, -2147483588
   %2 = ashr exact i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_ashr__exact_is_safe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
-; CHECK-NEXT:    [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, -2147483588
   %2 = ashr i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
 ; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
-; CHECK-NEXT:    [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
-; CHECK-NEXT:    [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
-; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
-; CHECK-NEXT:    ret i64 [[TMP5]]
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
+; CHECK-NEXT:    ret i64 [[TMP4]]
 ;
   %1 = and i32 %x, -2147483585
   %2 = ashr exact i32 %1, 2
   %3 = zext i32 %2 to i64
   %4 = icmp eq i32 %1, 0
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
;
   %5 = ashr i64 %y, %3
   %6 = select i1 %4, i64 %y, i64 %5
   ret i64 %6
 }
 
 define i32 @test_add_nuw_nsw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw_nsw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 3
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 1073741823
   %cmp = icmp eq i32 %and, 3
   %add = add nuw nsw i32 %and, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 3
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 1073741823
   %cmp = icmp eq i32 %and, 3
   %add = add nuw i32 %and, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nsw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nsw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 3
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 1073741823
   %cmp = icmp eq i32 %and, 3
   %add = add nsw i32 %and, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 1073741823
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 3
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 1073741823
   %cmp = icmp eq i32 %and, 3
   %add = add i32 %and, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw_nsw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw_nsw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[AND]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 2147483647
   %add = add nuw nsw i32 %and, 1
   %sel = select i1 %cmp, i32 -2147483648, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 2147483647
   %add = add nuw i32 %and, 1
   %sel = select i1 %cmp, i32 -2147483648, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nsw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nsw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[AND]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 2147483647
   %add = add nsw i32 %and, 1
   %sel = select i1 %cmp, i32 -2147483648, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 2147483647
 ; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[AND]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 2147483647
   %add = add i32 %and, 1
   %sel = select i1 %cmp, i32 -2147483648, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -1
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[OR]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[OR]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -1
   %add = add nuw nsw i32 %or, 1
   %sel = select i1 %cmp, i32 0, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -1
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[OR]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[OR]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -1
   %add = add nuw i32 %or, 1
   %sel = select i1 %cmp, i32 0, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -1
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[OR]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -1
   %add = add nsw i32 %or, 1
   %sel = select i1 %cmp, i32 0, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_add__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -1
 ; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[OR]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 0, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -1
   %add = add i32 %or, 1
   %sel = select i1 %cmp, i32 0, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw_nsw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw_nsw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw nsw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %cmp = icmp eq i32 %x, 3
   %add = add nuw nsw i32 %x, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nuw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nuw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT:    [[ADD:%.*]] = add nuw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %cmp = icmp eq i32 %x, 3
   %add = add nuw i32 %x, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add_nsw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add_nsw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 3
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 4, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %cmp = icmp eq i32 %x, 3
   %add = add nsw i32 %x, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_add__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_add__none_are_safe(
 ; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], 1
 ; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %cmp = icmp eq i32 %x, 3
   %add = add i32 %x, 1
   %sel = select i1 %cmp, i32 4, i32 %add
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw_nsw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw_nsw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 6
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 6
   %sub = sub nuw nsw i32 -254, %and
   %sel = select i1 %cmp, i32 -260, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 6
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 6
   %sub = sub nuw i32 -254, %and
   %sel = select i1 %cmp, i32 -260, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nsw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nsw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 6
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 6
   %sub = sub nsw i32 -254, %and
   %sel = select i1 %cmp, i32 -260, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 6
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -260, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 6
   %sub = sub i32 -254, %and
   %sel = select i1 %cmp, i32 -260, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw_nsw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw_nsw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 1073741824
   %sub = sub nuw nsw i32 -2147483648, %and
   %sel = select i1 %cmp, i32 1073741824, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 1073741824
   %sub = sub nuw i32 -2147483648, %and
   %sel = select i1 %cmp, i32 1073741824, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nsw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nsw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 1073741824
   %sub = sub nsw i32 -2147483648, %and
   %sel = select i1 %cmp, i32 1073741824, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 1073741824
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 1073741824, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %and = and i32 %x, 2147483647
   %cmp = icmp eq i32 %and, 1073741824
   %sub = sub i32 -2147483648, %and
   %sel = select i1 %cmp, i32 1073741824, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[OR]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -2147483647
   %sub = sub nuw nsw i32 -2147483648, %or
   %sel = select i1 %cmp, i32 -1, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[OR]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -2147483647
   %sub = sub nuw i32 -2147483648, %or
   %sel = select i1 %cmp, i32 -1, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -2147483647
   %sub = sub nsw i32 -2147483648, %or
   %sel = select i1 %cmp, i32 -1, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub__nsw_is_safe(
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[OR]], -2147483647
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %or = or i32 %x, -2147483648
   %cmp = icmp eq i32 %or, -2147483647
   %sub = sub i32 -2147483648, %or
   %sel = select i1 %cmp, i32 -1, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw_nsw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw_nsw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 -2147483648, [[X]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %cmp = icmp eq i32 %x, 1
   %sub = sub nuw nsw i32 -2147483648, %x
   %sel = select i1 %cmp, i32 2147483647, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nuw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nuw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[SUB:%.*]] = sub nuw i32 -2147483648, [[X]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %cmp = icmp eq i32 %x, 1
   %sub = sub nuw i32 -2147483648, %x
   %sel = select i1 %cmp, i32 2147483647, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub_nsw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub_nsw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 -2147483648, [[X]]
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 2147483647, i32 [[SUB]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %cmp = icmp eq i32 %x, 1
   %sub = sub nsw i32 -2147483648, %x
   %sel = select i1 %cmp, i32 2147483647, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_sub__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_sub__none_are_safe(
 ; CHECK-NEXT:    [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]]
 ; CHECK-NEXT:    ret i32 [[SUB]]
 ;
   %cmp = icmp eq i32 %x, 1
   %sub = sub i32 -2147483648, %x
   %sel = select i1 %cmp, i32 2147483647, i32 %sub
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw_nsw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw_nsw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 17
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 17
   %mul = mul nuw nsw i32 %and, 9
   %sel = select i1 %cmp, i32 153, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 17
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 17
   %mul = mul nuw i32 %and, 9
   %sel = select i1 %cmp, i32 153, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nsw__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nsw__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 17
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 17
   %mul = mul nsw i32 %and, 9
   %sel = select i1 %cmp, i32 153, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul__all_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul__all_are_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 17
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 153, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 255
   %cmp = icmp eq i32 %and, 17
   %mul = mul i32 %and, 9
   %sel = select i1 %cmp, i32 153, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw_nsw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw_nsw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 268435457
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
-; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul nuw i32 [[AND]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 268435457
   %cmp = icmp eq i32 %and, 268435456
   %mul = mul nuw nsw i32 %and, 9
   %sel = select i1 %cmp, i32 -1879048192, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 268435457
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nuw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 268435457
   %cmp = icmp eq i32 %and, 268435456
   %mul = mul nuw i32 %and, 9
   %sel = select i1 %cmp, i32 -1879048192, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nsw__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nsw__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 268435457
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
-; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul nuw i32 [[AND]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 268435457
   %cmp = icmp eq i32 %and, 268435456
   %mul = mul nsw i32 %and, 9
   %sel = select i1 %cmp, i32 -1879048192, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul__nuw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul__nuw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 268435457
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 268435456
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nuw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1879048192, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = and i32 %x, 268435457
   %cmp = icmp eq i32 %and, 268435456
   %mul = mul i32 %and, 9
   %sel = select i1 %cmp, i32 -1879048192, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
-; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[AND]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = or i32 %x, -83886080
   %cmp = icmp eq i32 %and, -83886079
   %mul = mul nuw nsw i32 %and, 9
   %sel = select i1 %cmp, i32 -754974711, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw__nsw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
-; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[AND]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = or i32 %x, -83886080
   %cmp = icmp eq i32 %and, -83886079
   %mul = mul nuw i32 %and, 9
   %sel = select i1 %cmp, i32 -754974711, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nsw__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nsw__nsw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = or i32 %x, -83886080
   %cmp = icmp eq i32 %and, -83886079
   %mul = mul nsw i32 %and, 9
   %sel = select i1 %cmp, i32 -754974711, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul__nsw_is_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul__nsw_is_safe(
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[X:%.*]], -83886080
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], -83886079
 ; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[AND]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -754974711, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %and = or i32 %x, -83886080
   %cmp = icmp eq i32 %and, -83886079
   %mul = mul i32 %and, 9
   %sel = select i1 %cmp, i32 -754974711, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw_nsw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw_nsw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 805306368
-; CHECK-NEXT:    [[MUL:%.*]] = mul nuw nsw i32 [[X]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1342177280, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[X:%.*]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %cmp = icmp eq i32 %x, 805306368
   %mul = mul nuw nsw i32 %x, 9
   %sel = select i1 %cmp, i32 -1342177280, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nuw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nuw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 805306368
-; CHECK-NEXT:    [[MUL:%.*]] = mul nuw i32 [[X]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1342177280, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[X:%.*]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %cmp = icmp eq i32 %x, 805306368
   %mul = mul nuw i32 %x, 9
   %sel = select i1 %cmp, i32 -1342177280, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul_nsw__none_are_safe(i32 %x) {
 ; CHECK-LABEL: @test_mul_nsw__none_are_safe(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 805306368
-; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[X]], 9
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -1342177280, i32 [[MUL]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[X:%.*]], 9
+; CHECK-NEXT:    ret i32 [[MUL]]
 ;
   %cmp = icmp eq i32 %x, 805306368
   %mul = mul nsw i32 %x, 9
   %sel = select i1 %cmp, i32 -1342177280, i32 %mul
   ret i32 %sel
 }
 
 define i32 @test_mul__none_are_safe(i32 %x) {

llvm/test/Transforms/InstCombine/select.ll

;
   %s0 = select i1 %c0, i32 %r0, i32 %r1
   %c1 = icmp slt i32 %a, %v2
   %s1 = select i1 %c1, i32 %r0, i32 %s0
   ret i32 %s1
 }
 
 define i32 @PR23757(i32 %x) {
 ; CHECK-LABEL: @PR23757(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %cmp = icmp eq i32 %x, 2147483647
   %add = add nsw i32 %x, 1
   %sel = select i1 %cmp, i32 -2147483648, i32 %add
   ret i32 %sel
 }
 
 define i32 @PR23757_swapped(i32 %x) {
 ; CHECK-LABEL: @PR23757_swapped(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[X:%.*]], 2147483647
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -2147483648
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 -2147483648
 ;
   %cmp = icmp eq i32 %x, 2147483647
   %add = add nsw i32 %x, 1
   %sel = select i1 %cmp, i32 %add, i32 -2147483648
   ret i32 %sel
 }
 
 define i32 @PR23757_ne(i32 %x, i1* %p) {
 ; CHECK-LABEL: @PR23757_ne(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 2147483647
 ; CHECK-NEXT:    store i1 [[CMP]], i1* [[P:%.*]], align 1
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 -2147483648, i32 [[ADD]]
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    ret i32 -2147483648
 ;
   %cmp = icmp ne i32 %x, 2147483647
   store i1 %cmp, i1* %p ; thwart predicate canonicalization
   %add = add nsw i32 %x, 1
   %sel = select i1 %cmp, i32 -2147483648, i32 %add
   ret i32 %sel
 }
 
 define i32 @PR23757_ne_swapped(i32 %x, i1* %p) {
 ; CHECK-LABEL: @PR23757_ne_swapped(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 2147483647
 ; CHECK-NEXT:    store i1 [[CMP]], i1* [[P:%.*]], align 1
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[X]], 1
-; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[ADD]], i32 -2147483648
-; CHECK-NEXT:    ret i32 [[SEL]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[X]], 1
+; CHECK-NEXT:    ret i32 [[ADD]]
 ;
   %cmp = icmp ne i32 %x, 2147483647
   store i1 %cmp, i1* %p ; thwart predicate canonicalization
   %add = add nsw i32 %x, 1
   %sel = select i1 %cmp, i32 %add, i32 -2147483648
   ret i32 %sel
 }