Use the MachineBasicBlock symbol for a callbr target

[void]

Summary

Inline asm doesn't use labels when compiled as an object file.
Therefore, we shouldn't create one for the (potential) callbr
destination. Instead, use the symbol for the MachineBasicBlock.

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

case '$': {
           unsigned OpFlags = MI->getOperand(OpNo).getImm();
           ++OpNo;  // Skip over the ID number.
 
           // FIXME: Shouldn't arch-independent output template handling go into
           // PrintAsmOperand?
           if (Modifier[0] == 'l') { // Labels are target independent.
             if (MI->getOperand(OpNo).isBlockAddress()) {
               const BlockAddress *BA = MI->getOperand(OpNo).getBlockAddress();
+              const Function *Fn = BA->getFunction();
+              if (Fn == &MI->getParent()->getParent()->getFunction()) {
+                const MachineFunction *MF = MMI->getMachineFunction(*Fn);
+                const BasicBlock *BB = BA->getBasicBlock();
+                for (const MachineBasicBlock &MBB : *MF) {
+                  if (BB == MBB.getBasicBlock()) {
+                    MBB.getSymbol()->print(OS, AP->MAI);
+                    const_cast<MachineBasicBlock&>(MBB).setLabelMustBeEmitted();
+                    break;
+                  }
+                }
+              } else {
                 MCSymbol *Sym = AP->GetBlockAddressSymbol(BA);
                 Sym->print(OS, AP->MAI);
+              }
             } else if (MI->getOperand(OpNo).isMBB()) {
               const MCSymbol *Sym = MI->getOperand(OpNo).getMBB()->getSymbol();
               Sym->print(OS, AP->MAI);
             } else {
               Error = true;
             }
           } else {
             if (InlineAsm::isMemKind(OpFlags)) {

test/CodeGen/AArch64/callbr-asm-label.ll

+; RUN: llc < %s -mtriple=armv4t-unknown-linux-gnueabi | FileCheck %s
+
+@X = common local_unnamed_addr global i32 0, align 4
+
+define i32 @test1() {
+; CHECK-LABEL: test1:
+; CHECK-LABEL:   .Ltmp0:
+; CHECK:         .long b
+; CHECK-NEXT:    .long .LBB0_1
+; CHECK-LABEL: .LBB0_1:
+; CHECK-LABEL: .LBB0_2:
+entry:
+  callbr void asm sideeffect "1:\0A\09.word b, ${0:l}\0A\09", "X"(i8* blockaddress(@test1, %l_yes))
+          to label %cleanup [label %l_yes]
+
+l_yes:
+  br label %cleanup
+
+cleanup:
+  %retval.0 = phi i32 [ 1, %l_yes ], [ 0, %entry ]
+  ret i32 %retval.0
+}
+
+define void @test2() {
+; CHECK-LABEL: test2:
+; CHECK-LABEL:   .Ltmp2
+; CHECK:         .long b
+; CHECK-NEXT:    .long .LBB1_3
+; CHECK-LABEL: .LBB1_2:
+; CHECK-LABEL: .LBB1_3:
+; CHECK-LABEL: .LBB1_5:
+entry:
+  %0 = load i32, i32* @X, align 4
+  %and = and i32 %0, 1
+  %tobool = icmp eq i32 %and, 0
+  br i1 %tobool, label %if.end10, label %if.then
+
+if.then:
+  callbr void asm sideeffect "1:\0A\09.word b, ${0:l}\0A\09", "X"(i8* blockaddress(@test2, %if.end6))
+          to label %if.then4 [label %if.then9]
+
+if.then4:
+  %call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
+  br label %if.end6
+
+if.end6:
+  %.pre = load i32, i32* @X, align 4
+  %.pre13 = and i32 %.pre, 1
+  %phitmp = icmp eq i32 %.pre13, 0
+  br i1 %phitmp, label %if.end10, label %if.then9
+
+if.then9:
+  callbr void asm sideeffect "", "X"(i8* blockaddress(@test2, %l_yes))
+          to label %if.end10 [label %l_yes]
+
+if.end10:
+  br label %l_yes
+
+l_yes:
+  ret void
+}
+
+declare i32 @g(...)

test/CodeGen/X86/callbr-asm-label-addr.ll

+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+
+; CHECK-LABEL: test1:
+; CHECK:       .quad .LBB0_2
+; CHECK-NEXT:  .quad .LBB0_1
+; CHECK-LABEL: .LBB0_1:
+; CHECK-LABEL: .LBB0_2:
+
+define i32 @test1(i32 %x) {
+entry:
+  callbr void asm sideeffect ".quad ${0:l}\0A\09.quad ${1:l}", "i,X,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@test1, %baz), i8* blockaddress(@test1, %bar))
+          to label %asm.fallthrough [label %bar]
+
+asm.fallthrough:
+  br label %bar
+
+bar:
+  %call = tail call i32 @foo(i32 %x)
+  br label %baz
+
+baz:
+  %call1 = tail call i32 @mux(i32 %call)
+  ret i32 %call1
+}
+
+declare i32 @foo(i32)
+
+declare i32 @mux(i32)

test/CodeGen/X86/callbr-asm-obj-file.ll

+; RUN: llc < %s -mtriple=x86_64-linux-gnu -filetype=obj -o - \
+; RUN:  | llvm-objdump -triple x86_64-linux-gnu -d - \
+; RUN:  | FileCheck %s
+
+; CHECK: 0000000000000000 test1:
+; CHECK-NEXT:   0: 74 00 je 0 <test1+0x2>
+; CHECK-NEXT:   2: c3    retq
+
+define void @test1() {
+entry:
+  callbr void asm sideeffect "je ${0:l}", "X,~{dirflag},~{fpsr},~{flags}"(i8* blockaddress(@test1, %a.b.normal.jump))
+          to label %asm.fallthrough [label %a.b.normal.jump]
+
+asm.fallthrough:
+  ret void
+
+a.b.normal.jump:
+  ret void
+}

test/CodeGen/X86/callbr-asm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- -O3 | FileCheck %s
 
 ; Tests for using callbr as an asm-goto wrapper
 
 ; Test 1 - fallthrough label gets removed, but the fallthrough code that is
 ; unreachable due to asm ending on a jmp is still left in.
 define i32 @test1(i32 %a) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    addl $4, %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    jmp .Ltmp00
+; CHECK-NEXT:    jmp .LBB0_2
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB0_1: # %normal
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retl
 ; CHECK-NEXT:  .Ltmp0: # Block address taken
 ; CHECK-NEXT:  .LBB0_2: # %fail
+; CHECK-NEXT:  # Label of block must be emitted
 ; CHECK-NEXT:    movl $1, %eax
 ; CHECK-NEXT:    retl
 entry:
   %0 = add i32 %a, 4
   callbr void asm "xorl $0, $0; jmp ${1:l}", "r,X,~{dirflag},~{fpsr},~{flags}"(i32 %0, i8* blockaddress(@test1, %fail)) to label %normal [label %fail]
 
 normal:
   ret i32 0

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .Ltmp4: # Block address taken
 ; CHECK-NEXT:  .LBB2_4: # %label04
 ; CHECK-NEXT:    # Parent Loop BB2_1 Depth=1
 ; CHECK-NEXT:    # Parent Loop BB2_2 Depth=2
 ; CHECK-NEXT:    # Parent Loop BB2_3 Depth=3
 ; CHECK-NEXT:    # => This Inner Loop Header: Depth=4
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    jmp .Ltmp10
-; CHECK-NEXT:    jmp .Ltmp20
-; CHECK-NEXT:    jmp .Ltmp30
+; CHECK-NEXT:    jmp .LBB2_1
+; CHECK-NEXT:    jmp .LBB2_2
+; CHECK-NEXT:    jmp .LBB2_3
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB2_5: # %normal0
 ; CHECK-NEXT:    # in Loop: Header=BB2_4 Depth=4
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    jmp .Ltmp10
-; CHECK-NEXT:    jmp .Ltmp20
-; CHECK-NEXT:    jmp .Ltmp30
-; CHECK-NEXT:    jmp .Ltmp40
+; CHECK-NEXT:    jmp .LBB2_1
+; CHECK-NEXT:    jmp .LBB2_2
+; CHECK-NEXT:    jmp .LBB2_3
+; CHECK-NEXT:    jmp .LBB2_4
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB2_6: # %normal1
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    retl
 entry:
   %a.addr = alloca i32, align 4
   store i32 %a, i32* %a.addr, align 4
   br label %label01