AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting exts

[arsenm]

Summary

The G_ANYEXT handling can end up reaching selectCOPY, which mutates
the instruction in place.

[nhaehnle]

LGTM

[arsenm]

r366915

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), TmpReg)
       .addReg(SrcReg);
     BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
       .addReg(TmpReg);
 
     // The instruction operands are backwards from what you would expect.
     BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
       .addImm(0)
       .addImm(Signed ? -1 : 1);
+    I.eraseFromParent();
     return RBI.constrainGenericRegister(DstReg, *DstRC, MRI);
   }
 
   if (SrcBank->getID() == AMDGPU::VCCRegBankID && DstSize <= 32) {
     if (SrcTy != S1) // Invalid
       return false;
 
     MachineInstr *ExtI =
       BuildMI(MBB, I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
       .addImm(0)               // src0_modifiers
       .addImm(0)               // src0
       .addImm(0)               // src1_modifiers
       .addImm(Signed ? -1 : 1) // src1
       .addUse(SrcReg);
+    I.eraseFromParent();
     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
   }
 
   if (I.getOpcode() == AMDGPU::G_ANYEXT)
     return selectCOPY(I);
 
   if (SrcBank->getID() == AMDGPU::VGPRRegBankID && DstSize <= 32) {
     // 64-bit should have been split up in RegBankSelect
 
     // Try to use an and with a mask if it will save code size.
     unsigned Mask;
     if (!Signed && shouldUseAndMask(SrcSize, Mask)) {
       MachineInstr *ExtI =
       BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
         .addImm(Mask)
         .addReg(SrcReg);
+      I.eraseFromParent();
       return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
     }
 
     const unsigned BFE = Signed ? AMDGPU::V_BFE_I32 : AMDGPU::V_BFE_U32;
     MachineInstr *ExtI =
       BuildMI(MBB, I, DL, TII.get(BFE), DstReg)
       .addReg(SrcReg)
       .addImm(0) // Offset
       .addImm(SrcSize); // Width
+    I.eraseFromParent();
     return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI);
   }
 
   if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) {
     if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, MRI))
       return false;
 
     if (Signed && DstSize == 32 && (SrcSize == 8 || SrcSize == 16)) {
       const unsigned SextOpc = SrcSize == 8 ?
         AMDGPU::S_SEXT_I32_I8 : AMDGPU::S_SEXT_I32_I16;
       BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg)
         .addReg(SrcReg);
+      I.eraseFromParent();
       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
     }
 
     const unsigned BFE64 = Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64;
     const unsigned BFE32 = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;
 
     // Scalar BFE is encoded as S1[5:0] = offset, S1[22:16]= width.
     if (DstSize > 32 && SrcSize <= 32) {
       // We need a 64-bit register source, but the high bits don't matter.
       unsigned ExtReg
         = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
       unsigned UndefReg
         = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
       BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
       BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
         .addReg(SrcReg)
         .addImm(AMDGPU::sub0)
         .addReg(UndefReg)
         .addImm(AMDGPU::sub1);
 
       BuildMI(MBB, I, DL, TII.get(BFE64), DstReg)
         .addReg(ExtReg)
         .addImm(SrcSize << 16);
 
+      I.eraseFromParent();
       return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, MRI);
     }
 
     unsigned Mask;
     if (!Signed && shouldUseAndMask(SrcSize, Mask)) {
       BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg)
         .addReg(SrcReg)
         .addImm(Mask);
     } else {
       BuildMI(MBB, I, DL, TII.get(BFE32), DstReg)
         .addReg(SrcReg)
         .addImm(SrcSize << 16);
     }
 
+    I.eraseFromParent();
     return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, MRI);
   }
 
   return false;
 }
 
 bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
case TargetOpcode::G_SELECT:
     return selectG_SELECT(I);
   case TargetOpcode::G_STORE:
     return selectG_STORE(I, CoverageInfo);
   case TargetOpcode::G_TRUNC:
     return selectG_TRUNC(I);
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
   case TargetOpcode::G_ANYEXT:
-    if (selectG_SZA_EXT(I)) {
-      I.eraseFromParent();
-      return true;
-    }
-
-    return false;
+    return selectG_SZA_EXT(I);
   case TargetOpcode::G_BRCOND:
     return selectG_BRCOND(I);
   case TargetOpcode::G_FRAME_INDEX:
     return selectG_FRAME_INDEX(I);
   case TargetOpcode::G_FENCE:
     // FIXME: Tablegen importer doesn't handle the imm operands correctly, and
     // is checking for G_CONSTANT
     I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));

test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
 
 ---
 
 name: anyext_scc_s1_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:

 name: anyext_sgpr_s1_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
-    ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: $sgpr0 = COPY [[COPY]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s32) = G_ANYEXT %1
     $sgpr0 = COPY %2
 ...
 
 ---
 
 name: anyext_sgpr_s1_to_sgpr_s64
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
-    ; GCN: $sgpr0_sgpr1 = COPY %2:sreg_64_xexec
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
+    ; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s1) = G_TRUNC %0
     %2:sgpr(s64) = G_ANYEXT %1
     $sgpr0_sgpr1 = COPY %2
 ...
 
 ---
 
 name: anyext_sgpr_s8_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s8_to_sgpr_s32
-    ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: $sgpr0 = COPY [[COPY]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s8) = G_TRUNC %0
     %2:sgpr(s32) = G_ANYEXT %1
     $sgpr0 = COPY %2
 
 ...
 
 ---
 
 name: anyext_sgpr_s16_to_sgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
-    ; GCN: $sgpr0 = COPY %2:sreg_32_xm0
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: $sgpr0 = COPY [[COPY]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:sgpr(s32) = G_ANYEXT %1
     $sgpr0 = COPY %2
 
 ...
 
 ---
 
 name: anyext_sgpr_s16_to_sgpr_s64
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $sgpr0
 
     ; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
-    ; GCN: $sgpr0_sgpr1 = COPY %2:sreg_64_xexec
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    ; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]]
+    ; GCN: $sgpr0_sgpr1 = COPY [[COPY1]]
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s16) = G_TRUNC %0
     %2:sgpr(s64) = G_ANYEXT %1
     $sgpr0_sgpr1 = COPY %2
 
 ...
 
 ---

 name: anyext_vgpr_s1_to_vgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
-    ; GCN: $vgpr0 = COPY %2:vgpr_32
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: $vgpr0 = COPY [[COPY]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s1) = G_TRUNC %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 ...
 
 ---
 
 name: anyext_vgpr_s8_to_vgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: anyext_vgpr_s8_to_vgpr_s32
-    ; GCN: $vgpr0 = COPY %2:vgpr_32
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: $vgpr0 = COPY [[COPY]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s8) = G_TRUNC %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 
 ...
 
 ---
 
 name: anyext_vgpr_s16_to_vgpr_s32
 legalized:       true
 regBankSelected: true
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; GCN-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
-    ; GCN: $vgpr0 = COPY %2:vgpr_32
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: $vgpr0 = COPY [[COPY]]
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s32) = G_ANYEXT %1
     $vgpr0 = COPY %2
 
 ...