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Differential D65007

[AMDGPU] Autogenerate register sequences in tuples
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Authored by rampitec on Jul 19 2019, 11:44 AM.

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Reviewers
arsenm
Commits
rL366619: [AMDGPU] Autogenerate register sequences in tuples
rG05d9e6a2a3d2: [AMDGPU] Autogenerate register sequences in tuples

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rampitec created this revision.Jul 19 2019, 11:44 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptJul 19 2019, 11:44 AM
rampitec added a comment.Jul 19 2019, 2:23 PM

FYI, I have compared generated files before and after. They are the same.

arsenm accepted this revision.Jul 19 2019, 2:37 PM

LGTM

This revision is now accepted and ready to land.Jul 19 2019, 2:37 PM
Closed by commit rG05d9e6a2a3d2: [AMDGPU] Autogenerate register sequences in tuples (authored by rampitec). · Explain WhyJul 19 2019, 2:44 PM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptJul 19 2019, 2:44 PM
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Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
319 lines

Diff 210907

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Show All 33 Lines list<SubRegIndex> ret = !if(!eq(size, 2), ret2,
!if(!eq(size, 4), ret4, !if(!eq(size, 4), ret4,
!if(!eq(size, 5), ret5, !if(!eq(size, 5), ret5,
!if(!eq(size, 8), ret8, !if(!eq(size, 8), ret8,
!if(!eq(size, 16), ret16, ret32)))))); !if(!eq(size, 16), ret16, ret32))))));
} }
// Generates list of sequential register tuple names. // Generates list of sequential register tuple names.
// E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ] // E.g. RegSeq<3,2,2,"s">.ret -> [ "s[0:1]", "s[2:3]" ]
class RegSeq<int last_reg, int stride, int size, string prefix, int start = 0> { class RegSeqNames<int last_reg, int stride, int size, string prefix,
int start = 0> {
int next = !add(start, stride); int next = !add(start, stride);
int end_reg = !add(!add(start, size), -1); int end_reg = !add(!add(start, size), -1);
list<string> ret = list<string> ret =
!if(!le(end_reg, last_reg), !if(!le(end_reg, last_reg),
!listconcat([prefix # "[" # start # ":" # end_reg # "]"], !listconcat([prefix # "[" # start # ":" # end_reg # "]"],
RegSeq<last_reg, stride, size, prefix, next>.ret), RegSeqNames<last_reg, stride, size, prefix, next>.ret),
[]); []);
} }
// Generates list of dags for register tupless.
class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size,
int start = 0> {
dag trunc_rc = (trunc RC,
!if(!and(!eq(stride, 1), !eq(start, 0)),
!add(!add(last_reg, 2), !mul(size, -1)),
!add(last_reg, 1)));
list<dag> ret =
!if(!lt(start, size),
!listconcat([(add (decimate (shl trunc_rc, start), stride))],
RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret),
[]);
}
class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
int last_reg, int stride, int size, string prefix> :
RegisterTuples<Indices,
RegSeqDags<RC, last_reg, stride, size>.ret,
RegSeqNames<last_reg, stride, size, prefix>.ret>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Declarations that describe the SI registers // Declarations that describe the SI registers
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SIReg <string n, bits<16> regIdx = 0> : class SIReg <string n, bits<16> regIdx = 0> :
Register<n>, Register<n>,
DwarfRegNum<[!cast<int>(HWEncoding)]> { DwarfRegNum<[!cast<int>(HWEncoding)]> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add (sequence "SGPR%u", 0, 105))> { (add (sequence "SGPR%u", 0, 105))> {
// Give all SGPR classes higher priority than VGPR classes, because // Give all SGPR classes higher priority than VGPR classes, because
// we want to spill SGPRs to VGPRs. // we want to spill SGPRs to VGPRs.
let AllocationPriority = 9; let AllocationPriority = 9;
} }
// SGPR 64-bit registers // SGPR 64-bit registers
def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret, def SGPR_64Regs : SIRegisterTuples<getSubRegs<2>.ret, SGPR_32, 105, 2, 2, "s">;
[(add (decimate SGPR_32, 2)),
(add (decimate (shl SGPR_32, 1), 2))],
RegSeq<105, 2, 2, "s">.ret>;
// SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs. // SGPR 96-bit registers. No operations use these, but for symmetry with 96-bit VGPRs.
def SGPR_96Regs : RegisterTuples<getSubRegs<3>.ret, def SGPR_96Regs : SIRegisterTuples<getSubRegs<3>.ret, SGPR_32, 105, 3, 3, "s">;
[(add (decimate SGPR_32, 3)),
(add (decimate (shl SGPR_32, 1), 3)),
(add (decimate (shl SGPR_32, 2), 3))],
RegSeq<105, 3, 3, "s">.ret>;
// SGPR 128-bit registers // SGPR 128-bit registers
def SGPR_128Regs : RegisterTuples<getSubRegs<4>.ret, def SGPR_128Regs : SIRegisterTuples<getSubRegs<4>.ret, SGPR_32, 105, 4, 4, "s">;
[(add (decimate SGPR_32, 4)),
(add (decimate (shl SGPR_32, 1), 4)),
(add (decimate (shl SGPR_32, 2), 4)),
(add (decimate (shl SGPR_32, 3), 4))],
RegSeq<105, 4, 4, "s">.ret>;
// SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs. // SGPR 160-bit registers. No operations use these, but for symmetry with 160-bit VGPRs.
def SGPR_160Regs : RegisterTuples<getSubRegs<5>.ret, def SGPR_160Regs : SIRegisterTuples<getSubRegs<5>.ret, SGPR_32, 105, 4, 5, "s">;
[(add (decimate SGPR_32, 4)),
(add (decimate (shl SGPR_32, 1), 4)),
(add (decimate (shl SGPR_32, 2), 4)),
(add (decimate (shl SGPR_32, 3), 4)),
(add (decimate (shl SGPR_32, 4), 4))],
RegSeq<105, 4, 5, "s">.ret>;
// SGPR 256-bit registers // SGPR 256-bit registers
def SGPR_256Regs : RegisterTuples<getSubRegs<8>.ret, def SGPR_256Regs : SIRegisterTuples<getSubRegs<8>.ret, SGPR_32, 105, 4, 8, "s">;
[(add (decimate SGPR_32, 4)),
(add (decimate (shl SGPR_32, 1), 4)),
(add (decimate (shl SGPR_32, 2), 4)),
(add (decimate (shl SGPR_32, 3), 4)),
(add (decimate (shl SGPR_32, 4), 4)),
(add (decimate (shl SGPR_32, 5), 4)),
(add (decimate (shl SGPR_32, 6), 4)),
(add (decimate (shl SGPR_32, 7), 4))],
RegSeq<105, 4, 8, "s">.ret>;
// SGPR 512-bit registers // SGPR 512-bit registers
def SGPR_512Regs : RegisterTuples<getSubRegs<16>.ret, def SGPR_512Regs : SIRegisterTuples<getSubRegs<16>.ret, SGPR_32, 105, 4, 16, "s">;
[(add (decimate SGPR_32, 4)),
(add (decimate (shl SGPR_32, 1), 4)),
(add (decimate (shl SGPR_32, 2), 4)),
(add (decimate (shl SGPR_32, 3), 4)),
(add (decimate (shl SGPR_32, 4), 4)),
(add (decimate (shl SGPR_32, 5), 4)),
(add (decimate (shl SGPR_32, 6), 4)),
(add (decimate (shl SGPR_32, 7), 4)),
(add (decimate (shl SGPR_32, 8), 4)),
(add (decimate (shl SGPR_32, 9), 4)),
(add (decimate (shl SGPR_32, 10), 4)),
(add (decimate (shl SGPR_32, 11), 4)),
(add (decimate (shl SGPR_32, 12), 4)),
(add (decimate (shl SGPR_32, 13), 4)),
(add (decimate (shl SGPR_32, 14), 4)),
(add (decimate (shl SGPR_32, 15), 4))],
RegSeq<105, 4, 16, "s">.ret>;
// SGPR 1024-bit registers // SGPR 1024-bit registers
def SGPR_1024Regs : RegisterTuples<getSubRegs<32>.ret, def SGPR_1024Regs : SIRegisterTuples<getSubRegs<32>.ret, SGPR_32, 105, 4, 32, "s">;
[(add (decimate SGPR_32, 4)),
(add (decimate (shl SGPR_32, 1), 4)),
(add (decimate (shl SGPR_32, 2), 4)),
(add (decimate (shl SGPR_32, 3), 4)),
(add (decimate (shl SGPR_32, 4), 4)),
(add (decimate (shl SGPR_32, 5), 4)),
(add (decimate (shl SGPR_32, 6), 4)),
(add (decimate (shl SGPR_32, 7), 4)),
(add (decimate (shl SGPR_32, 8), 4)),
(add (decimate (shl SGPR_32, 9), 4)),
(add (decimate (shl SGPR_32, 10), 4)),
(add (decimate (shl SGPR_32, 11), 4)),
(add (decimate (shl SGPR_32, 12), 4)),
(add (decimate (shl SGPR_32, 13), 4)),
(add (decimate (shl SGPR_32, 14), 4)),
(add (decimate (shl SGPR_32, 15), 4)),
(add (decimate (shl SGPR_32, 16), 4)),
(add (decimate (shl SGPR_32, 17), 4)),
(add (decimate (shl SGPR_32, 18), 4)),
(add (decimate (shl SGPR_32, 19), 4)),
(add (decimate (shl SGPR_32, 20), 4)),
(add (decimate (shl SGPR_32, 21), 4)),
(add (decimate (shl SGPR_32, 22), 4)),
(add (decimate (shl SGPR_32, 23), 4)),
(add (decimate (shl SGPR_32, 24), 4)),
(add (decimate (shl SGPR_32, 25), 4)),
(add (decimate (shl SGPR_32, 26), 4)),
(add (decimate (shl SGPR_32, 27), 4)),
(add (decimate (shl SGPR_32, 28), 4)),
(add (decimate (shl SGPR_32, 29), 4)),
(add (decimate (shl SGPR_32, 30), 4)),
(add (decimate (shl SGPR_32, 31), 4))],
RegSeq<105, 4, 32, "s">.ret>;
// Trap handler TMP 32-bit registers // Trap handler TMP 32-bit registers
def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32, def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
(add (sequence "TTMP%u", 0, 15))> { (add (sequence "TTMP%u", 0, 15))> {
let isAllocatable = 0; let isAllocatable = 0;
} }
// Trap handler TMP 64-bit registers // Trap handler TMP 64-bit registers
def TTMP_64Regs : RegisterTuples<getSubRegs<2>.ret, def TTMP_64Regs : SIRegisterTuples<getSubRegs<2>.ret, TTMP_32, 15, 2, 2, "ttmp">;
[(add (decimate TTMP_32, 2)),
(add (decimate (shl TTMP_32, 1), 2))],
RegSeq<15, 2, 2, "ttmp">.ret>;
// Trap handler TMP 128-bit registers // Trap handler TMP 128-bit registers
def TTMP_128Regs : RegisterTuples<getSubRegs<4>.ret, def TTMP_128Regs : SIRegisterTuples<getSubRegs<4>.ret, TTMP_32, 15, 4, 4, "ttmp">;
[(add (decimate TTMP_32, 4)),
(add (decimate (shl TTMP_32, 1), 4)), def TTMP_256Regs : SIRegisterTuples<getSubRegs<8>.ret, TTMP_32, 15, 4, 8, "ttmp">;
(add (decimate (shl TTMP_32, 2), 4)),
(add (decimate (shl TTMP_32, 3), 4))], def TTMP_512Regs : SIRegisterTuples<getSubRegs<16>.ret, TTMP_32, 15, 4, 16, "ttmp">;
RegSeq<15, 4, 4, "ttmp">.ret>;
def TTMP_256Regs : RegisterTuples<getSubRegs<8>.ret,
[(add (decimate TTMP_32, 4)),
(add (decimate (shl TTMP_32, 1), 4)),
(add (decimate (shl TTMP_32, 2), 4)),
(add (decimate (shl TTMP_32, 3), 4)),
(add (decimate (shl TTMP_32, 4), 4)),
(add (decimate (shl TTMP_32, 5), 4)),
(add (decimate (shl TTMP_32, 6), 4)),
(add (decimate (shl TTMP_32, 7), 4))],
RegSeq<15, 4, 8, "ttmp">.ret>;
def TTMP_512Regs : RegisterTuples<getSubRegs<16>.ret,
[(add (decimate TTMP_32, 4)),
(add (decimate (shl TTMP_32, 1), 4)),
(add (decimate (shl TTMP_32, 2), 4)),
(add (decimate (shl TTMP_32, 3), 4)),
(add (decimate (shl TTMP_32, 4), 4)),
(add (decimate (shl TTMP_32, 5), 4)),
(add (decimate (shl TTMP_32, 6), 4)),
(add (decimate (shl TTMP_32, 7), 4)),
(add (decimate (shl TTMP_32, 8), 4)),
(add (decimate (shl TTMP_32, 9), 4)),
(add (decimate (shl TTMP_32, 10), 4)),
(add (decimate (shl TTMP_32, 11), 4)),
(add (decimate (shl TTMP_32, 12), 4)),
(add (decimate (shl TTMP_32, 13), 4)),
(add (decimate (shl TTMP_32, 14), 4)),
(add (decimate (shl TTMP_32, 15), 4))],
RegSeq<15, 4, 16, "ttmp">.ret>;
class TmpRegTuplesBase<int index, int size, class TmpRegTuplesBase<int index, int size,
list<Register> subRegs, list<Register> subRegs,
list<SubRegIndex> indices = getSubRegs<size>.ret, list<SubRegIndex> indices = getSubRegs<size>.ret,
int index1 = !add(index, !add(size, -1)), int index1 = !add(index, !add(size, -1)),
string name = "ttmp["#index#":"#index1#"]"> : string name = "ttmp["#index#":"#index1#"]"> :
RegisterWithSubRegs<name, subRegs> { RegisterWithSubRegs<name, subRegs> {
let HWEncoding = subRegs[0].HWEncoding; let HWEncoding = subRegs[0].HWEncoding;
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
// i16/f16 only on VI+ // i16/f16 only on VI+
def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add (sequence "VGPR%u", 0, 255))> { (add (sequence "VGPR%u", 0, 255))> {
let AllocationPriority = 1; let AllocationPriority = 1;
let Size = 32; let Size = 32;
} }
// VGPR 64-bit registers // VGPR 64-bit registers
def VGPR_64 : RegisterTuples<getSubRegs<2>.ret, def VGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, VGPR_32, 255, 1, 2, "v">;
[(add (trunc VGPR_32, 255)),
(add (shl VGPR_32, 1))],
RegSeq<255, 1, 2, "v">.ret>;
// VGPR 96-bit registers // VGPR 96-bit registers
def VGPR_96 : RegisterTuples<getSubRegs<3>.ret, def VGPR_96 : SIRegisterTuples<getSubRegs<3>.ret, VGPR_32, 255, 1, 3, "v">;
[(add (trunc VGPR_32, 254)),
(add (shl VGPR_32, 1)),
(add (shl VGPR_32, 2))],
RegSeq<255, 1, 3, "v">.ret>;
// VGPR 128-bit registers // VGPR 128-bit registers
def VGPR_128 : RegisterTuples<getSubRegs<4>.ret, def VGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, VGPR_32, 255, 1, 4, "v">;
[(add (trunc VGPR_32, 253)),
(add (shl VGPR_32, 1)),
(add (shl VGPR_32, 2)),
(add (shl VGPR_32, 3))],
RegSeq<255, 1, 4, "v">.ret>;
// VGPR 160-bit registers // VGPR 160-bit registers
def VGPR_160 : RegisterTuples<getSubRegs<5>.ret, def VGPR_160 : SIRegisterTuples<getSubRegs<5>.ret, VGPR_32, 255, 1, 5, "v">;
[(add (trunc VGPR_32, 252)),
(add (shl VGPR_32, 1)),
(add (shl VGPR_32, 2)),
(add (shl VGPR_32, 3)),
(add (shl VGPR_32, 4))],
RegSeq<255, 1, 5, "v">.ret>;
// VGPR 256-bit registers // VGPR 256-bit registers
def VGPR_256 : RegisterTuples<getSubRegs<8>.ret, def VGPR_256 : SIRegisterTuples<getSubRegs<8>.ret, VGPR_32, 255, 1, 8, "v">;
[(add (trunc VGPR_32, 249)),
(add (shl VGPR_32, 1)),
(add (shl VGPR_32, 2)),
(add (shl VGPR_32, 3)),
(add (shl VGPR_32, 4)),
(add (shl VGPR_32, 5)),
(add (shl VGPR_32, 6)),
(add (shl VGPR_32, 7))],
RegSeq<255, 1, 8, "v">.ret>;
// VGPR 512-bit registers // VGPR 512-bit registers
def VGPR_512 : RegisterTuples<getSubRegs<16>.ret, def VGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, VGPR_32, 255, 1, 16, "v">;
[(add (trunc VGPR_32, 241)),
(add (shl VGPR_32, 1)),
(add (shl VGPR_32, 2)),
(add (shl VGPR_32, 3)),
(add (shl VGPR_32, 4)),
(add (shl VGPR_32, 5)),
(add (shl VGPR_32, 6)),
(add (shl VGPR_32, 7)),
(add (shl VGPR_32, 8)),
(add (shl VGPR_32, 9)),
(add (shl VGPR_32, 10)),
(add (shl VGPR_32, 11)),
(add (shl VGPR_32, 12)),
(add (shl VGPR_32, 13)),
(add (shl VGPR_32, 14)),
(add (shl VGPR_32, 15))],
RegSeq<255, 1, 16, "v">.ret>;
// VGPR 1024-bit registers // VGPR 1024-bit registers
def VGPR_1024 : RegisterTuples<getSubRegs<32>.ret, def VGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, VGPR_32, 255, 1, 32, "v">;
[(add (trunc VGPR_32, 225)),
(add (shl VGPR_32, 1)),
(add (shl VGPR_32, 2)),
(add (shl VGPR_32, 3)),
(add (shl VGPR_32, 4)),
(add (shl VGPR_32, 5)),
(add (shl VGPR_32, 6)),
(add (shl VGPR_32, 7)),
(add (shl VGPR_32, 8)),
(add (shl VGPR_32, 9)),
(add (shl VGPR_32, 10)),
(add (shl VGPR_32, 11)),
(add (shl VGPR_32, 12)),
(add (shl VGPR_32, 13)),
(add (shl VGPR_32, 14)),
(add (shl VGPR_32, 15)),
(add (shl VGPR_32, 16)),
(add (shl VGPR_32, 17)),
(add (shl VGPR_32, 18)),
(add (shl VGPR_32, 19)),
(add (shl VGPR_32, 20)),
(add (shl VGPR_32, 21)),
(add (shl VGPR_32, 22)),
(add (shl VGPR_32, 23)),
(add (shl VGPR_32, 24)),
(add (shl VGPR_32, 25)),
(add (shl VGPR_32, 26)),
(add (shl VGPR_32, 27)),
(add (shl VGPR_32, 28)),
(add (shl VGPR_32, 29)),
(add (shl VGPR_32, 30)),
(add (shl VGPR_32, 31))],
RegSeq<255, 1, 32, "v">.ret>;
// AccVGPR 32-bit registers // AccVGPR 32-bit registers
def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add (sequence "AGPR%u", 0, 255))> { (add (sequence "AGPR%u", 0, 255))> {
let AllocationPriority = 1; let AllocationPriority = 1;
let Size = 32; let Size = 32;
} }
// AGPR 64-bit registers // AGPR 64-bit registers
def AGPR_64 : RegisterTuples<getSubRegs<2>.ret, def AGPR_64 : SIRegisterTuples<getSubRegs<2>.ret, AGPR_32, 255, 1, 2, "a">;
[(add (trunc AGPR_32, 255)),
(add (shl AGPR_32, 1))],
RegSeq<255, 1, 2, "a">.ret>;
// AGPR 128-bit registers // AGPR 128-bit registers
def AGPR_128 : RegisterTuples<getSubRegs<4>.ret, def AGPR_128 : SIRegisterTuples<getSubRegs<4>.ret, AGPR_32, 255, 1, 4, "a">;
[(add (trunc AGPR_32, 253)),
(add (shl AGPR_32, 1)),
(add (shl AGPR_32, 2)),
(add (shl AGPR_32, 3))],
RegSeq<255, 1, 4, "a">.ret>;
// AGPR 512-bit registers // AGPR 512-bit registers
def AGPR_512 : RegisterTuples<getSubRegs<16>.ret, def AGPR_512 : SIRegisterTuples<getSubRegs<16>.ret, AGPR_32, 255, 1, 16, "a">;
[(add (trunc AGPR_32, 241)),
(add (shl AGPR_32, 1)),
(add (shl AGPR_32, 2)),
(add (shl AGPR_32, 3)),
(add (shl AGPR_32, 4)),
(add (shl AGPR_32, 5)),
(add (shl AGPR_32, 6)),
(add (shl AGPR_32, 7)),
(add (shl AGPR_32, 8)),
(add (shl AGPR_32, 9)),
(add (shl AGPR_32, 10)),
(add (shl AGPR_32, 11)),
(add (shl AGPR_32, 12)),
(add (shl AGPR_32, 13)),
(add (shl AGPR_32, 14)),
(add (shl AGPR_32, 15))],
RegSeq<255, 1, 16, "a">.ret>;
// AGPR 1024-bit registers // AGPR 1024-bit registers
def AGPR_1024 : RegisterTuples<getSubRegs<32>.ret, def AGPR_1024 : SIRegisterTuples<getSubRegs<32>.ret, AGPR_32, 255, 1, 32, "a">;
[(add (trunc AGPR_32, 225)),
(add (shl AGPR_32, 1)),
(add (shl AGPR_32, 2)),
(add (shl AGPR_32, 3)),
(add (shl AGPR_32, 4)),
(add (shl AGPR_32, 5)),
(add (shl AGPR_32, 6)),
(add (shl AGPR_32, 7)),
(add (shl AGPR_32, 8)),
(add (shl AGPR_32, 9)),
(add (shl AGPR_32, 10)),
(add (shl AGPR_32, 11)),
(add (shl AGPR_32, 12)),
(add (shl AGPR_32, 13)),
(add (shl AGPR_32, 14)),
(add (shl AGPR_32, 15)),
(add (shl AGPR_32, 16)),
(add (shl AGPR_32, 17)),
(add (shl AGPR_32, 18)),
(add (shl AGPR_32, 19)),
(add (shl AGPR_32, 20)),
(add (shl AGPR_32, 21)),
(add (shl AGPR_32, 22)),
(add (shl AGPR_32, 23)),
(add (shl AGPR_32, 24)),
(add (shl AGPR_32, 25)),
(add (shl AGPR_32, 26)),
(add (shl AGPR_32, 27)),
(add (shl AGPR_32, 28)),
(add (shl AGPR_32, 29)),
(add (shl AGPR_32, 30)),
(add (shl AGPR_32, 31))],
RegSeq<255, 1, 32, "a">.ret>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register classes used as source and destination // Register classes used as source and destination
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> { (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
let isAllocatable = 0; let isAllocatable = 0;
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