[MIPS GlobalISel] ClampScalar and select pointer G_ICMP

[Petar.Avramovic]

Summary

Add narrowScalar to half of original size for G_ICMP.
ClampScalar G_ICMP's operands 2 and 3 to to s32.
Select G_ICMP for pointers for MIPS32. Pointer compare is same
as for integers, it is enough to declare them as legal type.

[atanasyan]

LGTM

[brzycki]

Hello @Petar.Avramovic , this commit is causing a compiler assert when I perform the following:

1. Build clang for aarch64-unknown-linux-gnu
2. Use this new compiler to build a shared library version of LLVM's libcxx library, specifically the filesystem/operations.cpp source file.

Here is the CMake for clang:

/tools/build/cmake-3.14.5/bin/cmake \
  -D CCACHE_PROGRAM=/tools/build/ccache-3.2.5/usr/bin/ccache \
  -D LLVM_CCACHE_BUILD=ON \
  -G Ninja \
  -D CMAKE_MAKE_PROGRAM=/tools/build/ninja-1.9.0/ninja \
  -D 'LLVM_TARGETS_TO_BUILD=X86;AArch64;ARM' \
  -D CMAKE_BUILD_TYPE=Release \
  -D CMAKE_INSTALL_PREFIX=/work/bmr/bisect \
  -D LLVM_PARALLEL_LINK_JOBS=1 \
  -D BUILD_SHARED_LIBS=ON \
  -D LLVM_ENABLE_ASSERTIONS=ON \
  -D LLVM_BINUTILS_INCDIR=/tools/cross/aarch64/buildroot/2019.02_sysroot/lib/gcc/aarch64-samsung-linux-gnu/8.3.0/plugin/include \
  -D LIBCXX_ENABLE_SHARED=OFF \
  -D LIBCXX_ENABLE_STATIC_ABI_LIBRARY=ON \
  -D LINK_POLLY_INTO_TOOLS=ON \
  -D LLVM_OPTIMIZED_TABLEGEN=ON \
  /tmp/tmp.QeEQpbu86Y/src/llvm

This compiler successfully compiles. Next I attempt to build libcxx with this newly-created compiler:

xport CC=/work/bmr/bisect/bin/aarch64-linux-clang
export CXX=/work/bmr/bisect/bin/aarch64-linux-clang++
/tools/build/cmake-3.14.5/bin/cmake \
  -D CCACHE_PROGRAM=/tools/build/ccache-3.2.5/usr/bin/ccache \
  -D LLVM_CCACHE_BUILD=ON \
  -D LIBCXX_ENABLE_SHARED=ON \
  -G Ninja \
  -D CMAKE_MAKE_PROGRAM=/tools/build/ninja-1.9.0/ninja \
  -D CMAKE_INSTALL_PREFIX=/work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot \
  -D LLVM_PATH=/tmp/tmp.QeEQpbu86Y/src/llvm \
  -D LIBCXX_TARGET_TRIPLE=aarch64-samsung-linux-gnu \
  -D LIBCXX_CXX_ABI=libcxxabi \
  -D LIBCXX_CXX_ABI_INCLUDE_PATHS=/tmp/tmp.QeEQpbu86Y/src/libcxxabi/include \
  -D LIBCXX_SYSROOT=/work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot \
  -D LIBCXX_GCC_TOOLCHAIN=/work/bmr/bisect/bin \
  -D CMAKE_C_FLAGS= \
  -D CMAKE_CXX_FLAGS= /tmp/tmp.QeEQpbu86Y/src/libcxx

At step 73 the Assert(..) occurs:

[73/79] /work/bmr/bisect/bin/aarch64-linux-clang++  -DNDEBUG -D_LIBCPP_BUILDING_LIBRARY -D_LIBCPP_HAS_COMMENT_LIB_PRAGMA -D_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER -Iinclude/c++build -I/tmp/tmp.QeEQpbu86Y/src/libcxx/include --target=aarch64-samsung-linux-gnu --sysroot=/work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot --gcc-toolchain=/work/bmr/bisect/bin -fPIC   --target=aarch64-samsung-linux-gnu --sysroot=/work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot--gcc-toolchain=/work/bmr/bisect/bin -DLIBCXX_BUILDING_LIBCXXABI -std=c++11 -nostdinc++ -fvisibility-inlines-hidden -Wall -Wextra -W -Wwrite-strings -Wno-unused-parameter -Wno-long-long -Werror=return-type -Wextra-semi -Wno-user-defined-literals -Wno-covered-switch-default -Wno-ignored-attributes -Wno-error -MD -MT src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o -MF src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o.d -o src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o -c /tmp/tmp.QeEQpbu86Y/src/libcxx/src/filesystem/operations.cppFAILED: src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o
FAILED: src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o

clang-9: /tmp/tmp.QeEQpbu86Y/src/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:904: void llvm::MachineIRBuilder::validateSelectOp(const llvm::LLT &, const llvm::LLT &, const llvm::LLT &, const llvm::LLT &): Assertion `(ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch"' failed.
Stack dump:
0.      Program arguments: /work/bmr/bisect/bin/clang-9 -cc1 -triple aarch64-samsung-linux-gnu -emit-obj -mrelax-all -disable-free -main-file-name operations.cpp -mrelocation-model pic -pic-level 2 -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -fuse-init-array -target-cpu generic -target-feature +neon -target-abi aapcs -fallow-half-arguments-and-returns -dwarf-column-info -debugger-tuning=gdb -coverage-notes-file /tmp/tmp.QeEQpbu86Y/build/libcxx-shared/src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.gcno -nostdinc++ -resource-dir /work/bmr/bisect/lib/clang/9.0.0 -dependency-file src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o.d -sys-header-deps -MT src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o -cxx-isystem /work/bmr/bisect/aarch64-samsung-linux-gnu/include/c++/8.3.0 -cxx-isystem /work/bmr/bisect/aarch64-samsung-linux-gnu/include/c++/8.3.0/aarch64-samsung-linux-gnu -D _GLIBCXX_INCLUDE_NEXT_C_HEADERS -D NDEBUG -D _LIBCPP_BUILDING_LIBRARY -D _LIBCPP_HAS_COMMENT_LIB_PRAGMA -D _LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER -I include/c++build -I /tmp/tmp.QeEQpbu86Y/src/libcxx/include -D LIBCXX_BUILDING_LIBCXXABI -isysroot /work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot -internal-isystem /work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot/usr/local/include -internal-isystem /work/bmr/bisect/lib/clang/9.0.0/include -internal-externc-isystem /work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot/include -internal-externc-isystem /work/bmr/bisect/aarch64-samsung-linux-gnu/sysroot/usr/include -Wall -Wextra -W -Wwrite-strings -Wno-unused-parameter -Wno-long-long -Werror=return-type -Wextra-semi -Wno-user-defined-literals -Wno-covered-switch-default -Wno-ignored-attributes -Wno-error -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /tmp/tmp.QeEQpbu86Y/build/libcxx-shared -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fno-signed-char -fobjc-runtime=gcc -fcxx-exceptions -fexceptions -fdiagnostics-show-option -faddrsig -o src/CMakeFiles/cxx_shared.dir/filesystem/operations.cpp.o -x c++ /tmp/tmp.QeEQpbu86Y/src/libcxx/src/filesystem/operations.cpp
1.      <eof> parser at end of file
2.      Code generation
3.      Running pass 'Function Pass Manager' on module '/tmp/tmp.QeEQpbu86Y/src/libcxx/src/filesystem/operations.cpp'.
4.      Running pass 'Legalizer' on function '@_ZNSt3__14__fs10filesystem6detail12_GLOBAL__N_19time_utilINS_6chrono10time_pointINS1_16_FilesystemClockENS5_8durationInNS_5ratioILl1ELl1000000000EEEEEEEl8timespecE16is_representableESD_'
 #0 0x00007f075ada8014 PrintStackTraceSignalHandler(void*) (/work/bmr/bisect/lib/libLLVMSupport.so.9svn+0x17b014)
 #1 0x00007f075ada5c9e llvm::sys::RunSignalHandlers() (/work/bmr/bisect/lib/libLLVMSupport.so.9svn+0x178c9e)
 #2 0x00007f075ada82c8 SignalHandler(int) (/work/bmr/bisect/lib/libLLVMSupport.so.9svn+0x17b2c8)
 #3 0x00007f075f130890 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x12890)
 #4 0x00007f075821ee97 raise /build/glibc-OTsEL5/glibc-2.27/signal/../sysdeps/unix/sysv/linux/raise.c:51:0
 #5 0x00007f0758220801 abort /build/glibc-OTsEL5/glibc-2.27/stdlib/abort.c:81:0
 #6 0x00007f075821039a __assert_fail_base /build/glibc-OTsEL5/glibc-2.27/assert/assert.c:89:0
 #7 0x00007f0758210412 (/lib/x86_64-linux-gnu/libc.so.6+0x30412)
 #8 0x00007f0757c66bd4 llvm::MachineIRBuilder::validateSelectOp(llvm::LLT const&, llvm::LLT const&, llvm::LLT const&, llvm::LLT const&) (/work/bmr/bisect/lib/libLLVMGlobalISel.so.9svn+0x7bbd4)
 #9 0x00007f0757c67edb llvm::MachineIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, llvm::Optional<unsigned int>) (/work/bmr/bisect/lib/libLLVMGlobalISel.so.9svn+0x7cedb)
#10 0x00007f0757c1010d llvm::CSEMIRBuilder::buildInstr(unsigned int, llvm::ArrayRef<llvm::DstOp>, llvm::ArrayRef<llvm::SrcOp>, llvm::Optional<unsigned int>) (/work/bmr/bisect/lib/libLLVMGlobalISel.so.9svn+0x2510d)
#11 0x00007f0757c65b8a llvm::MachineIRBuilder::buildSelect(llvm::DstOp const&, llvm::SrcOp const&, llvm::SrcOp const&, llvm::SrcOp const&) (/work/bmr/bisect/lib/libLLVMGlobalISel.so.9svn+0x7ab8a)
#12 0x00007f0757c3f949 llvm::LegalizerHelper::narrowScalar(llvm::MachineInstr&, unsigned int, llvm::LLT) (/work/bmr/bisect/lib/libLLVMGlobalISel.so.9svn+0x54949)
#13 0x00007f0757c380f0 llvm::Legalizer::runOnMachineFunction(llvm::MachineFunction&) (/work/bmr/bisect/lib/libLLVMGlobalISel.so.9svn+0x4d0f0)
#14 0x00007f075ff057ca llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/work/bmr/bisect/lib/libLLVMCodeGen.so.9svn+0x22a7ca)
#15 0x00007f075c45e6fa llvm::FPPassManager::runOnFunction(llvm::Function&) (/work/bmr/bisect/lib/libLLVMCore.so.9svn+0x1de6fa)
#16 0x00007f075c45ea73 llvm::FPPassManager::runOnModule(llvm::Module&) (/work/bmr/bisect/lib/libLLVMCore.so.9svn+0x1dea73)
#17 0x00007f075c45f0dd llvm::legacy::PassManagerImpl::run(llvm::Module&) (/work/bmr/bisect/lib/libLLVMCore.so.9svn+0x1df0dd)
#18 0x00007f075e31b70c clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::HeaderSearchOptions const&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::DataLayout const&, llvm::Module*, clang::BackendAction, std::unique_ptr<llvm::raw_pwrite_stream, std::default_delete<llvm::raw_pwrite_stream> >) (/work/bmr/bisect/lib/libclangCodeGen.so.9svn+0x9570c)
#19 0x00007f075e5d1763 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) (/work/bmr/bisect/lib/libclangCodeGen.so.9svn+0x34b763)
#20 0x00007f075519ae93 clang::ParseAST(clang::Sema&, bool, bool) (/work/bmr/bisect/lib/libclangParse.so.9svn+0x2ee93)
#21 0x00007f075dba0538 clang::FrontendAction::Execute() (/work/bmr/bisect/lib/libclangFrontend.so.9svn+0xe9538)
#22 0x00007f075db3b538 clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) (/work/bmr/bisect/lib/libclangFrontend.so.9svn+0x84538)
#23 0x00007f075d8b402e clang::ExecuteCompilerInvocation(clang::CompilerInstance*) (/work/bmr/bisect/lib/libclangFrontendTool.so.9svn+0x402e)
#24 0x0000000000410def cc1_main(llvm::ArrayRef<char const*>, char const*, void*) (/work/bmr/bisect/bin/clang-9+0x410def)
#25 0x000000000040eb35 main (/work/bmr/bisect/bin/clang-9+0x40eb35)
#26 0x00007f0758201b97 __libc_start_main /build/glibc-OTsEL5/glibc-2.27/csu/../csu/libc-start.c:344:0
#27 0x000000000040bcfa _start (/work/bmr/bisect/bin/clang-9+0x40bcfa)
clang-9: error: unable to execute command: Aborted (core dumped)
clang-9: error: clang frontend command failed due to signal (use -v to see invocation)
clang version 9.0.0 (/samsung-c/compiler/git/tools/llvm-project.git 1e62635d0551578bf3899d2a1f4c835e30f2eed8)
Target: aarch64-samsung-linux-gnu
Thread model: posix
InstalledDir: /work/bmr/bisect/bin
clang-9: note: diagnostic msg: PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace, preprocessed source, and associated run script.
clang-9: note: diagnostic msg:
********************

PLEASE ATTACH THE FOLLOWING FILES TO THE BUG REPORT:
Preprocessed source(s) and associated run script(s) are located at:
clang-9: note: diagnostic msg: /tmp/operations-e9c9c2.cpp
clang-9: note: diagnostic msg: /tmp/operations-e9c9c2.sh
clang-9: note: diagnostic msg:

I am attaching the emitted shell script and .cpp file here if that helps.

D64856.tar.xz395 KBDownload

[Petar.Avramovic]

Hello @brzycki, I will take a closer look on Monday.
Quick guess is that swapping lines 310,311 in AArch64LegalizerInfo.cpp (rules for G_ICMP) could fix the problem:
i.e. to change

.clampScalar(0, s32, s32)
.clampScalar(1, s32, s64)

into this:

.clampScalar(1, s32, s64)
.clampScalar(0, s32, s32)

I assumed that G_ICMP gets narrowScalared in default form with s1 as a result, but it looks like that is not always the case.
I will try to fix this in narrow scalar so that there is no need for specific ordering of legalization rules for some generic opcodes.

[brzycki]

Hi @Petar.Avramovic , I replied to your testing query in D65079. Thank you again for looking into this.

llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

if (TypeIdx != 2)
       return UnableToLegalize;
 
     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
     Observer.changingInstr(MI);
     narrowScalarSrc(MI, NarrowTy, OpIdx);
     Observer.changedInstr(MI);
     return Legalized;
   }
+  case TargetOpcode::G_ICMP: {
+    uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
+    if (NarrowSize * 2 != SrcSize)
+      return UnableToLegalize;
+
+    Observer.changingInstr(MI);
+    Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
+    Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
+    MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
+
+    Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
+    Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
+    MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
+
+    CmpInst::Predicate Pred =
+        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
+
+    if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
+      MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
+      MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
+      MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
+      MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
+      MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
+    } else {
+      const LLT s1 = LLT::scalar(1);
+      MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, s1, LHSH, RHSH);
+      MachineInstrBuilder CmpHEQ =
+          MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, s1, LHSH, RHSH);
+      MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
+          ICmpInst::getUnsignedPredicate(Pred), s1, LHSL, RHSL);
+      MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
+    }
+    Observer.changedInstr(MI);
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }
 
 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
                                      unsigned OpIdx, unsigned ExtOpcode) {
   MachineOperand &MO = MI.getOperand(OpIdx);
   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
   MO.setReg(ExtB->getOperand(0).getReg());

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UREM, G_UDIV})
       .minScalar(0, s32)
       .libcallFor({s64});
 
   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
     .legalFor({s32, s32})
     .minScalar(1, s32);
 
   getActionDefinitionsBuilder(G_ICMP)
-      .legalFor({{s32, s32}})
+      .legalForCartesianProduct({s32}, {s32, p0})
+      .clampScalar(1, s32, s32)
       .minScalar(0, s32);
 
   getActionDefinitionsBuilder(G_CONSTANT)
       .legalFor({s32})
       .clampScalar(0, s32, s32);
 
   getActionDefinitionsBuilder(G_GEP)
       .legalFor({{p0, s32}});

llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @eq() {entry: ret void}
-  define void @ne() {entry: ret void}
-  define void @sgt() {entry: ret void}
-  define void @sge() {entry: ret void}
-  define void @slt() {entry: ret void}
-  define void @sle() {entry: ret void}
-  define void @ugt() {entry: ret void}
-  define void @uge() {entry: ret void}
-  define void @ult() {entry: ret void}
-  define void @ule() {entry: ret void}
+  define void @eq_i32() {entry: ret void}
+  define void @ne_i32() {entry: ret void}
+  define void @sgt_i32() {entry: ret void}
+  define void @sge_i32() {entry: ret void}
+  define void @slt_i32() {entry: ret void}
+  define void @sle_i32() {entry: ret void}
+  define void @ugt_i32() {entry: ret void}
+  define void @uge_i32() {entry: ret void}
+  define void @ult_i32() {entry: ret void}
+  define void @ule_i32() {entry: ret void}
+  define void @eq_ptr() {entry: ret void}
+
 
 ...
 ---
-name:            eq
+name:            eq_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: eq
+    ; MIPS32-LABEL: name: eq_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
     ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTiu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTiu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ne
+name:            ne_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ne
+    ; MIPS32-LABEL: name: ne_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ne), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sgt
+name:            sgt_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sgt
+    ; MIPS32-LABEL: name: sgt_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLT]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sgt), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sge
+name:            sge_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sge
+    ; MIPS32-LABEL: name: sge_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sge), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            slt
+name:            slt_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: slt
+    ; MIPS32-LABEL: name: slt_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLT]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(slt), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sle
+name:            sle_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sle
+    ; MIPS32-LABEL: name: sle_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sle), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ugt
+name:            ugt_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ugt
+    ; MIPS32-LABEL: name: ugt_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ugt), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            uge
+name:            uge_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: uge
+    ; MIPS32-LABEL: name: uge_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(uge), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ult
+name:            ult_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ult
+    ; MIPS32-LABEL: name: ult_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ult), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ule
+name:            ule_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ule
+    ; MIPS32-LABEL: name: ule_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ule), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            eq_ptr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: eq_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
+    ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
+    ; MIPS32: $v0 = COPY [[SLTiu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(eq), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @eq() {entry: ret void}
-  define void @ne() {entry: ret void}
-  define void @sgt() {entry: ret void}
-  define void @sge() {entry: ret void}
-  define void @slt() {entry: ret void}
-  define void @sle() {entry: ret void}
-  define void @ugt() {entry: ret void}
-  define void @uge() {entry: ret void}
-  define void @ult() {entry: ret void}
-  define void @ule() {entry: ret void}
+  define void @ne_i32() {entry: ret void}
+  define void @eq_ptr() {entry: ret void}
+  define void @ult_i8() {entry: ret void}
+  define void @slt_i16() {entry: ret void}
+  define void @eq_i64() {entry: ret void}
+  define void @ne_i64() {entry: ret void}
+  define void @sgt_i64() {entry: ret void}
+  define void @sge_i64() {entry: ret void}
+  define void @slt_i64() {entry: ret void}
+  define void @sle_i64() {entry: ret void}
+  define void @ugt_i64() {entry: ret void}
+  define void @uge_i64() {entry: ret void}
+  define void @ult_i64() {entry: ret void}
+  define void @ule_i64() {entry: ret void}
 
 ...
 ---
-name:            eq
+name:            ne_i32
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: eq
+    ; MIPS32-LABEL: name: ne_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
     %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(eq), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
+    %2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
+    %3:_(s32) = G_ANYEXT %2(s1)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ne
+name:            eq_ptr
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ne
+    ; MIPS32-LABEL: name: eq_ptr
     ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s1) = G_ICMP intpred(eq), %0(p0), %1
+    %3:_(s32) = G_ANYEXT %2(s1)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sgt
+name:            ult_i8
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sgt
+    ; MIPS32-LABEL: name: ult_i8
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(sgt), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %2(s32)
+    %3:_(s32) = COPY $a1
+    %1:_(s8) = G_TRUNC %3(s32)
+    %4:_(s1) = G_ICMP intpred(ult), %0(s8), %1
+    %5:_(s32) = G_ANYEXT %4(s1)
+    $v0 = COPY %5(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sge
+name:            slt_i16
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sge
+    ; MIPS32-LABEL: name: slt_i16
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+    ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %2(s32)
+    %3:_(s32) = COPY $a1
+    %1:_(s16) = G_TRUNC %3(s32)
+    %4:_(s1) = G_ICMP intpred(slt), %0(s16), %1
+    %5:_(s32) = G_ANYEXT %4(s1)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            eq_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: eq_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
+    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
+    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(eq), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ne_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ne_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
+    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
+    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ne), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            sgt_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: sgt_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(sge), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            slt
+name:            sge_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: slt
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: sge_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(slt), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(sge), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sle
+name:            slt_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: sle
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: slt_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(sle), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(slt), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ugt
+name:            sle_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: ugt
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: sle_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ugt), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(sle), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            uge
+name:            ugt_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: uge
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: ugt_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(uge), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ult
+name:            uge_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: ult
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: uge_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ult), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(uge), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ule
+name:            ult_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: ule
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: ult_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ule), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ult), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            ule_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
 
+    ; MIPS32-LABEL: name: ule_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ule), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
-define i32 @eq(i32 %a, i32 %b){
-; MIPS32-LABEL: eq:
+define i1 @eq_i32(i32 %a, i32 %b){
+; MIPS32-LABEL: eq_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $1, $4, $5
-; MIPS32-NEXT:    sltiu $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltiu $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp eq i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ne(i32 %a, i32 %b) {
-; MIPS32-LABEL: ne:
+define i1 @ne_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ne_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $1, $4, $5
-; MIPS32-NEXT:    sltu $1, $zero, $1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltu $2, $zero, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ne i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @sgt(i32 %a, i32 %b) {
-; MIPS32-LABEL: sgt:
+define i1 @sgt_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: sgt_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    slt $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    slt $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sgt i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @sge(i32 %a, i32 %b) {
-; MIPS32-LABEL: sge:
+define i1 @sge_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: sge_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $4, $5
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sge i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @slt(i32 %a, i32 %b) {
-; MIPS32-LABEL: slt:
+define i1 @slt_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: slt_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    slt $1, $4, $5
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    slt $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp slt i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @sle(i32 %a, i32 %b) {
-; MIPS32-LABEL: sle:
+define i1 @sle_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: sle_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $5, $4
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sle i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ugt(i32 %a, i32 %b) {
-; MIPS32-LABEL: ugt:
+define i1 @ugt_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ugt_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    sltu $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltu $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ugt i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @uge(i32 %a, i32 %b) {
-; MIPS32-LABEL: uge:
+define i1 @uge_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: uge_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $4, $5
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp uge i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ult(i32 %a, i32 %b) {
-; MIPS32-LABEL: ult:
+define i1 @ult_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ult_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    sltu $1, $4, $5
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltu $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ult i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ule(i32 %a, i32 %b) {
-; MIPS32-LABEL: ule:
+define i1 @ule_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ule_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $5, $4
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ule i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
+}
+
+define i1 @eq_ptr(i32* %a, i32* %b){
+; MIPS32-LABEL: eq_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $5
+; MIPS32-NEXT:    sltiu $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp eq i32* %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ult_i8(i8 %a, i8 %b) {
+; MIPS32-LABEL: ult_i8:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    ori $1, $zero, 255
+; MIPS32-NEXT:    and $2, $4, $1
+; MIPS32-NEXT:    and $1, $5, $1
+; MIPS32-NEXT:    sltu $2, $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ult i8 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @slt_i16(i16 %a, i16 %b) {
+; MIPS32-LABEL: slt_i16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $1, $4, 16
+; MIPS32-NEXT:    sra $1, $1, 16
+; MIPS32-NEXT:    sll $2, $5, 16
+; MIPS32-NEXT:    sra $2, $2, 16
+; MIPS32-NEXT:    slt $2, $1, $2
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp slt i16 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @eq_i64(i64 %a, i64 %b){
+; MIPS32-LABEL: eq_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $6
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    ori $2, $zero, 0
+; MIPS32-NEXT:    xor $1, $1, $2
+; MIPS32-NEXT:    sltiu $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp eq i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ne_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ne_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $6
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    ori $2, $zero, 0
+; MIPS32-NEXT:    xor $1, $1, $2
+; MIPS32-NEXT:    sltu $2, $zero, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ne i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @sgt_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: sgt_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $7, $5
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @sge_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: sge_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $5, $7
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp sge i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @slt_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: slt_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $5, $7
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp slt i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @sle_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: sle_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $7, $5
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp sle i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ugt_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ugt_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $7, $5
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @uge_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: uge_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $5, $7
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp uge i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ult_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ult_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $5, $7
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ult i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ule_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ule_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $7, $5
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ule i64 %a, %b
+  ret i1 %cmp
 }

llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @eq() {entry: ret void}
-  define void @ne() {entry: ret void}
-  define void @sgt() {entry: ret void}
-  define void @sge() {entry: ret void}
-  define void @slt() {entry: ret void}
-  define void @sle() {entry: ret void}
-  define void @ugt() {entry: ret void}
-  define void @uge() {entry: ret void}
-  define void @ult() {entry: ret void}
-  define void @ule() {entry: ret void}
+  define void @ne_i32() {entry: ret void}
+  define void @eq_ptr() {entry: ret void}
 
 ...
 ---
-name:            eq
+name:            ne_i32
 alignment:       2
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: eq
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(eq), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            ne
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: ne
+    ; MIPS32-LABEL: name: ne_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
     ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
     ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
     %1:_(s32) = COPY $a1
     %4:_(s32) = G_ICMP intpred(ne), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            sgt
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: sgt
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(sgt), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            sge
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: sge
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(sge), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(sge), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            slt
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: slt
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(slt), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            sle
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: sle
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(sle), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(sle), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            ugt
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: ugt
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(ugt), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            uge
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: uge
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(uge), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
+    %3:_(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ult
+name:            eq_ptr
 alignment:       2
 legalized:       true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ult
+    ; MIPS32-LABEL: name: eq_ptr
     ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
     ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(ult), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            ule
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: ule
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(ule), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_ICMP intpred(eq), %0(p0), %1
+    %3:_(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...