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Differential D64839

[AMDGPU] Autogenerate register asm names
ClosedPublic

Authored by rampitec on Jul 16 2019, 4:09 PM.

Details

Reviewers
arsenm
Commits
rGe5012ab30820: [AMDGPU] Autogenerate register asm names
rL366283: [AMDGPU] Autogenerate register asm names

Diff Detail

Event Timeline

rampitec created this revision.Jul 16 2019, 4:09 PM
Herald added subscribers: t-tye, tpr, dstuttard and 6 others. · View Herald TranscriptJul 16 2019, 4:09 PM
rampitec added a comment.Jul 16 2019, 4:13 PM

With that we can also simplify AMDGPUInstPrinter::printRegOperand(). Also the next step is to rename flat_scr into flat_scratch.

arsenm added inline comments.Jul 16 2019, 4:18 PM
lib/Target/AMDGPU/SIRegisterInfo.td
61

So this generates too many names, and then the extra SGPR ones just don't work?

634

This probably shouldn't have a set name, but should be Reg128

rampitec marked 2 inline comments as done.Jul 16 2019, 4:29 PM
rampitec added inline comments.
lib/Target/AMDGPU/SIRegisterInfo.td
61

It generates a practical minimum of used names with exception of:

  1. It generates overflow names, like v[255:0]. We do not use overflow regs, but in fact we could.
  2. It generates dups for special registers, but there are not too much of them.

Generic names can be dropped in a separate patch in favor of Reg32, but that will be a separate huge tests update. I thought of that but do not want to mix everything into a single change. I am also not sure how mir will live with square brackets and colons.

634

Thanks, Reg128 indeed.

arsenm accepted this revision.Jul 16 2019, 4:31 PM

LGTM

This revision is now accepted and ready to land.Jul 16 2019, 4:31 PM
rampitec updated this revision to Diff 210217.Jul 16 2019, 4:33 PM

Fixed Reg128.

Closed by commit rL366283: [AMDGPU] Autogenerate register asm names (authored by rampitec). · Explain WhyJul 16 2019, 4:44 PM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2019, 4:44 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
1 line
MCTargetDesc/
4 lines
79 lines
183 lines

Diff 210214

lib/Target/AMDGPU/AMDGPURegAsmNames.inc.cpp

  • This file was deleted.
//===-- AMDGPURegAsmNames.inc - Register asm names ----------*- C++ -*-----===//
#ifdef AMDGPU_REG_ASM_NAMES
static const char *const VGPR32RegNames[] = {
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8",
"v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
"v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26",
"v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35",
"v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44",
"v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53",
"v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62",
"v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
"v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80",
"v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89",
"v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98",
"v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107",
"v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116",
"v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125",
"v126", "v127", "v128", "v129", "v130", "v131", "v132", "v133", "v134",
"v135", "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
"v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", "v152",
"v153", "v154", "v155", "v156", "v157", "v158", "v159", "v160", "v161",
"v162", "v163", "v164", "v165", "v166", "v167", "v168", "v169", "v170",
"v171", "v172", "v173", "v174", "v175", "v176", "v177", "v178", "v179",
"v180", "v181", "v182", "v183", "v184", "v185", "v186", "v187", "v188",
"v189", "v190", "v191", "v192", "v193", "v194", "v195", "v196", "v197",
"v198", "v199", "v200", "v201", "v202", "v203", "v204", "v205", "v206",
"v207", "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
"v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", "v224",
"v225", "v226", "v227", "v228", "v229", "v230", "v231", "v232", "v233",
"v234", "v235", "v236", "v237", "v238", "v239", "v240", "v241", "v242",
"v243", "v244", "v245", "v246", "v247", "v248", "v249", "v250", "v251",
"v252", "v253", "v254", "v255"
};
static const char *const SGPR32RegNames[] = {
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9",
"s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19",
"s20", "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29",
"s30", "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
"s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49",
"s50", "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59",
"s60", "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69",
"s70", "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
"s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89",
"s90", "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99",
"s100", "s101", "s102", "s103", "s104", "s105"
};
static const char *const VGPR64RegNames[] = {
"v[0:1]", "v[1:2]", "v[2:3]", "v[3:4]", "v[4:5]",
"v[5:6]", "v[6:7]", "v[7:8]", "v[8:9]", "v[9:10]",
"v[10:11]", "v[11:12]", "v[12:13]", "v[13:14]", "v[14:15]",
"v[15:16]", "v[16:17]", "v[17:18]", "v[18:19]", "v[19:20]",
"v[20:21]", "v[21:22]", "v[22:23]", "v[23:24]", "v[24:25]",
"v[25:26]", "v[26:27]", "v[27:28]", "v[28:29]", "v[29:30]",
"v[30:31]", "v[31:32]", "v[32:33]", "v[33:34]", "v[34:35]",
"v[35:36]", "v[36:37]", "v[37:38]", "v[38:39]", "v[39:40]",
"v[40:41]", "v[41:42]", "v[42:43]", "v[43:44]", "v[44:45]",
"v[45:46]", "v[46:47]", "v[47:48]", "v[48:49]", "v[49:50]",
"v[50:51]", "v[51:52]", "v[52:53]", "v[53:54]", "v[54:55]",
"v[55:56]", "v[56:57]", "v[57:58]", "v[58:59]", "v[59:60]",
"v[60:61]", "v[61:62]", "v[62:63]", "v[63:64]", "v[64:65]",
"v[65:66]", "v[66:67]", "v[67:68]", "v[68:69]", "v[69:70]",
"v[70:71]", "v[71:72]", "v[72:73]", "v[73:74]", "v[74:75]",
"v[75:76]", "v[76:77]", "v[77:78]", "v[78:79]", "v[79:80]",
"v[80:81]", "v[81:82]", "v[82:83]", "v[83:84]", "v[84:85]",
"v[85:86]", "v[86:87]", "v[87:88]", "v[88:89]", "v[89:90]",
"v[90:91]", "v[91:92]", "v[92:93]", "v[93:94]", "v[94:95]",
"v[95:96]", "v[96:97]", "v[97:98]", "v[98:99]", "v[99:100]",
"v[100:101]", "v[101:102]", "v[102:103]", "v[103:104]", "v[104:105]",
"v[105:106]", "v[106:107]", "v[107:108]", "v[108:109]", "v[109:110]",
"v[110:111]", "v[111:112]", "v[112:113]", "v[113:114]", "v[114:115]",
"v[115:116]", "v[116:117]", "v[117:118]", "v[118:119]", "v[119:120]",
"v[120:121]", "v[121:122]", "v[122:123]", "v[123:124]", "v[124:125]",
"v[125:126]", "v[126:127]", "v[127:128]", "v[128:129]", "v[129:130]",
"v[130:131]", "v[131:132]", "v[132:133]", "v[133:134]", "v[134:135]",
"v[135:136]", "v[136:137]", "v[137:138]", "v[138:139]", "v[139:140]",
"v[140:141]", "v[141:142]", "v[142:143]", "v[143:144]", "v[144:145]",
"v[145:146]", "v[146:147]", "v[147:148]", "v[148:149]", "v[149:150]",
"v[150:151]", "v[151:152]", "v[152:153]", "v[153:154]", "v[154:155]",
"v[155:156]", "v[156:157]", "v[157:158]", "v[158:159]", "v[159:160]",
"v[160:161]", "v[161:162]", "v[162:163]", "v[163:164]", "v[164:165]",
"v[165:166]", "v[166:167]", "v[167:168]", "v[168:169]", "v[169:170]",
"v[170:171]", "v[171:172]", "v[172:173]", "v[173:174]", "v[174:175]",
"v[175:176]", "v[176:177]", "v[177:178]", "v[178:179]", "v[179:180]",
"v[180:181]", "v[181:182]", "v[182:183]", "v[183:184]", "v[184:185]",
"v[185:186]", "v[186:187]", "v[187:188]", "v[188:189]", "v[189:190]",
"v[190:191]", "v[191:192]", "v[192:193]", "v[193:194]", "v[194:195]",
"v[195:196]", "v[196:197]", "v[197:198]", "v[198:199]", "v[199:200]",
"v[200:201]", "v[201:202]", "v[202:203]", "v[203:204]", "v[204:205]",
"v[205:206]", "v[206:207]", "v[207:208]", "v[208:209]", "v[209:210]",
"v[210:211]", "v[211:212]", "v[212:213]", "v[213:214]", "v[214:215]",
"v[215:216]", "v[216:217]", "v[217:218]", "v[218:219]", "v[219:220]",
"v[220:221]", "v[221:222]", "v[222:223]", "v[223:224]", "v[224:225]",
"v[225:226]", "v[226:227]", "v[227:228]", "v[228:229]", "v[229:230]",
"v[230:231]", "v[231:232]", "v[232:233]", "v[233:234]", "v[234:235]",
"v[235:236]", "v[236:237]", "v[237:238]", "v[238:239]", "v[239:240]",
"v[240:241]", "v[241:242]", "v[242:243]", "v[243:244]", "v[244:245]",
"v[245:246]", "v[246:247]", "v[247:248]", "v[248:249]", "v[249:250]",
"v[250:251]", "v[251:252]", "v[252:253]", "v[253:254]", "v[254:255]"
};
static const char *const VGPR96RegNames[] = {
"v[0:2]", "v[1:3]", "v[2:4]", "v[3:5]", "v[4:6]",
"v[5:7]", "v[6:8]", "v[7:9]", "v[8:10]", "v[9:11]",
"v[10:12]", "v[11:13]", "v[12:14]", "v[13:15]", "v[14:16]",
"v[15:17]", "v[16:18]", "v[17:19]", "v[18:20]", "v[19:21]",
"v[20:22]", "v[21:23]", "v[22:24]", "v[23:25]", "v[24:26]",
"v[25:27]", "v[26:28]", "v[27:29]", "v[28:30]", "v[29:31]",
"v[30:32]", "v[31:33]", "v[32:34]", "v[33:35]", "v[34:36]",
"v[35:37]", "v[36:38]", "v[37:39]", "v[38:40]", "v[39:41]",
"v[40:42]", "v[41:43]", "v[42:44]", "v[43:45]", "v[44:46]",
"v[45:47]", "v[46:48]", "v[47:49]", "v[48:50]", "v[49:51]",
"v[50:52]", "v[51:53]", "v[52:54]", "v[53:55]", "v[54:56]",
"v[55:57]", "v[56:58]", "v[57:59]", "v[58:60]", "v[59:61]",
"v[60:62]", "v[61:63]", "v[62:64]", "v[63:65]", "v[64:66]",
"v[65:67]", "v[66:68]", "v[67:69]", "v[68:70]", "v[69:71]",
"v[70:72]", "v[71:73]", "v[72:74]", "v[73:75]", "v[74:76]",
"v[75:77]", "v[76:78]", "v[77:79]", "v[78:80]", "v[79:81]",
"v[80:82]", "v[81:83]", "v[82:84]", "v[83:85]", "v[84:86]",
"v[85:87]", "v[86:88]", "v[87:89]", "v[88:90]", "v[89:91]",
"v[90:92]", "v[91:93]", "v[92:94]", "v[93:95]", "v[94:96]",
"v[95:97]", "v[96:98]", "v[97:99]", "v[98:100]", "v[99:101]",
"v[100:102]", "v[101:103]", "v[102:104]", "v[103:105]", "v[104:106]",
"v[105:107]", "v[106:108]", "v[107:109]", "v[108:110]", "v[109:111]",
"v[110:112]", "v[111:113]", "v[112:114]", "v[113:115]", "v[114:116]",
"v[115:117]", "v[116:118]", "v[117:119]", "v[118:120]", "v[119:121]",
"v[120:122]", "v[121:123]", "v[122:124]", "v[123:125]", "v[124:126]",
"v[125:127]", "v[126:128]", "v[127:129]", "v[128:130]", "v[129:131]",
"v[130:132]", "v[131:133]", "v[132:134]", "v[133:135]", "v[134:136]",
"v[135:137]", "v[136:138]", "v[137:139]", "v[138:140]", "v[139:141]",
"v[140:142]", "v[141:143]", "v[142:144]", "v[143:145]", "v[144:146]",
"v[145:147]", "v[146:148]", "v[147:149]", "v[148:150]", "v[149:151]",
"v[150:152]", "v[151:153]", "v[152:154]", "v[153:155]", "v[154:156]",
"v[155:157]", "v[156:158]", "v[157:159]", "v[158:160]", "v[159:161]",
"v[160:162]", "v[161:163]", "v[162:164]", "v[163:165]", "v[164:166]",
"v[165:167]", "v[166:168]", "v[167:169]", "v[168:170]", "v[169:171]",
"v[170:172]", "v[171:173]", "v[172:174]", "v[173:175]", "v[174:176]",
"v[175:177]", "v[176:178]", "v[177:179]", "v[178:180]", "v[179:181]",
"v[180:182]", "v[181:183]", "v[182:184]", "v[183:185]", "v[184:186]",
"v[185:187]", "v[186:188]", "v[187:189]", "v[188:190]", "v[189:191]",
"v[190:192]", "v[191:193]", "v[192:194]", "v[193:195]", "v[194:196]",
"v[195:197]", "v[196:198]", "v[197:199]", "v[198:200]", "v[199:201]",
"v[200:202]", "v[201:203]", "v[202:204]", "v[203:205]", "v[204:206]",
"v[205:207]", "v[206:208]", "v[207:209]", "v[208:210]", "v[209:211]",
"v[210:212]", "v[211:213]", "v[212:214]", "v[213:215]", "v[214:216]",
"v[215:217]", "v[216:218]", "v[217:219]", "v[218:220]", "v[219:221]",
"v[220:222]", "v[221:223]", "v[222:224]", "v[223:225]", "v[224:226]",
"v[225:227]", "v[226:228]", "v[227:229]", "v[228:230]", "v[229:231]",
"v[230:232]", "v[231:233]", "v[232:234]", "v[233:235]", "v[234:236]",
"v[235:237]", "v[236:238]", "v[237:239]", "v[238:240]", "v[239:241]",
"v[240:242]", "v[241:243]", "v[242:244]", "v[243:245]", "v[244:246]",
"v[245:247]", "v[246:248]", "v[247:249]", "v[248:250]", "v[249:251]",
"v[250:252]", "v[251:253]", "v[252:254]", "v[253:255]"
};
static const char *const VGPR128RegNames[] = {
"v[0:3]", "v[1:4]", "v[2:5]", "v[3:6]", "v[4:7]",
"v[5:8]", "v[6:9]", "v[7:10]", "v[8:11]", "v[9:12]",
"v[10:13]", "v[11:14]", "v[12:15]", "v[13:16]", "v[14:17]",
"v[15:18]", "v[16:19]", "v[17:20]", "v[18:21]", "v[19:22]",
"v[20:23]", "v[21:24]", "v[22:25]", "v[23:26]", "v[24:27]",
"v[25:28]", "v[26:29]", "v[27:30]", "v[28:31]", "v[29:32]",
"v[30:33]", "v[31:34]", "v[32:35]", "v[33:36]", "v[34:37]",
"v[35:38]", "v[36:39]", "v[37:40]", "v[38:41]", "v[39:42]",
"v[40:43]", "v[41:44]", "v[42:45]", "v[43:46]", "v[44:47]",
"v[45:48]", "v[46:49]", "v[47:50]", "v[48:51]", "v[49:52]",
"v[50:53]", "v[51:54]", "v[52:55]", "v[53:56]", "v[54:57]",
"v[55:58]", "v[56:59]", "v[57:60]", "v[58:61]", "v[59:62]",
"v[60:63]", "v[61:64]", "v[62:65]", "v[63:66]", "v[64:67]",
"v[65:68]", "v[66:69]", "v[67:70]", "v[68:71]", "v[69:72]",
"v[70:73]", "v[71:74]", "v[72:75]", "v[73:76]", "v[74:77]",
"v[75:78]", "v[76:79]", "v[77:80]", "v[78:81]", "v[79:82]",
"v[80:83]", "v[81:84]", "v[82:85]", "v[83:86]", "v[84:87]",
"v[85:88]", "v[86:89]", "v[87:90]", "v[88:91]", "v[89:92]",
"v[90:93]", "v[91:94]", "v[92:95]", "v[93:96]", "v[94:97]",
"v[95:98]", "v[96:99]", "v[97:100]", "v[98:101]", "v[99:102]",
"v[100:103]", "v[101:104]", "v[102:105]", "v[103:106]", "v[104:107]",
"v[105:108]", "v[106:109]", "v[107:110]", "v[108:111]", "v[109:112]",
"v[110:113]", "v[111:114]", "v[112:115]", "v[113:116]", "v[114:117]",
"v[115:118]", "v[116:119]", "v[117:120]", "v[118:121]", "v[119:122]",
"v[120:123]", "v[121:124]", "v[122:125]", "v[123:126]", "v[124:127]",
"v[125:128]", "v[126:129]", "v[127:130]", "v[128:131]", "v[129:132]",
"v[130:133]", "v[131:134]", "v[132:135]", "v[133:136]", "v[134:137]",
"v[135:138]", "v[136:139]", "v[137:140]", "v[138:141]", "v[139:142]",
"v[140:143]", "v[141:144]", "v[142:145]", "v[143:146]", "v[144:147]",
"v[145:148]", "v[146:149]", "v[147:150]", "v[148:151]", "v[149:152]",
"v[150:153]", "v[151:154]", "v[152:155]", "v[153:156]", "v[154:157]",
"v[155:158]", "v[156:159]", "v[157:160]", "v[158:161]", "v[159:162]",
"v[160:163]", "v[161:164]", "v[162:165]", "v[163:166]", "v[164:167]",
"v[165:168]", "v[166:169]", "v[167:170]", "v[168:171]", "v[169:172]",
"v[170:173]", "v[171:174]", "v[172:175]", "v[173:176]", "v[174:177]",
"v[175:178]", "v[176:179]", "v[177:180]", "v[178:181]", "v[179:182]",
"v[180:183]", "v[181:184]", "v[182:185]", "v[183:186]", "v[184:187]",
"v[185:188]", "v[186:189]", "v[187:190]", "v[188:191]", "v[189:192]",
"v[190:193]", "v[191:194]", "v[192:195]", "v[193:196]", "v[194:197]",
"v[195:198]", "v[196:199]", "v[197:200]", "v[198:201]", "v[199:202]",
"v[200:203]", "v[201:204]", "v[202:205]", "v[203:206]", "v[204:207]",
"v[205:208]", "v[206:209]", "v[207:210]", "v[208:211]", "v[209:212]",
"v[210:213]", "v[211:214]", "v[212:215]", "v[213:216]", "v[214:217]",
"v[215:218]", "v[216:219]", "v[217:220]", "v[218:221]", "v[219:222]",
"v[220:223]", "v[221:224]", "v[222:225]", "v[223:226]", "v[224:227]",
"v[225:228]", "v[226:229]", "v[227:230]", "v[228:231]", "v[229:232]",
"v[230:233]", "v[231:234]", "v[232:235]", "v[233:236]", "v[234:237]",
"v[235:238]", "v[236:239]", "v[237:240]", "v[238:241]", "v[239:242]",
"v[240:243]", "v[241:244]", "v[242:245]", "v[243:246]", "v[244:247]",
"v[245:248]", "v[246:249]", "v[247:250]", "v[248:251]", "v[249:252]",
"v[250:253]", "v[251:254]", "v[252:255]"
};
static const char *const VGPR256RegNames[] = {
"v[0:7]", "v[1:8]", "v[2:9]", "v[3:10]", "v[4:11]",
"v[5:12]", "v[6:13]", "v[7:14]", "v[8:15]", "v[9:16]",
"v[10:17]", "v[11:18]", "v[12:19]", "v[13:20]", "v[14:21]",
"v[15:22]", "v[16:23]", "v[17:24]", "v[18:25]", "v[19:26]",
"v[20:27]", "v[21:28]", "v[22:29]", "v[23:30]", "v[24:31]",
"v[25:32]", "v[26:33]", "v[27:34]", "v[28:35]", "v[29:36]",
"v[30:37]", "v[31:38]", "v[32:39]", "v[33:40]", "v[34:41]",
"v[35:42]", "v[36:43]", "v[37:44]", "v[38:45]", "v[39:46]",
"v[40:47]", "v[41:48]", "v[42:49]", "v[43:50]", "v[44:51]",
"v[45:52]", "v[46:53]", "v[47:54]", "v[48:55]", "v[49:56]",
"v[50:57]", "v[51:58]", "v[52:59]", "v[53:60]", "v[54:61]",
"v[55:62]", "v[56:63]", "v[57:64]", "v[58:65]", "v[59:66]",
"v[60:67]", "v[61:68]", "v[62:69]", "v[63:70]", "v[64:71]",
"v[65:72]", "v[66:73]", "v[67:74]", "v[68:75]", "v[69:76]",
"v[70:77]", "v[71:78]", "v[72:79]", "v[73:80]", "v[74:81]",
"v[75:82]", "v[76:83]", "v[77:84]", "v[78:85]", "v[79:86]",
"v[80:87]", "v[81:88]", "v[82:89]", "v[83:90]", "v[84:91]",
"v[85:92]", "v[86:93]", "v[87:94]", "v[88:95]", "v[89:96]",
"v[90:97]", "v[91:98]", "v[92:99]", "v[93:100]", "v[94:101]",
"v[95:102]", "v[96:103]", "v[97:104]", "v[98:105]", "v[99:106]",
"v[100:107]", "v[101:108]", "v[102:109]", "v[103:110]", "v[104:111]",
"v[105:112]", "v[106:113]", "v[107:114]", "v[108:115]", "v[109:116]",
"v[110:117]", "v[111:118]", "v[112:119]", "v[113:120]", "v[114:121]",
"v[115:122]", "v[116:123]", "v[117:124]", "v[118:125]", "v[119:126]",
"v[120:127]", "v[121:128]", "v[122:129]", "v[123:130]", "v[124:131]",
"v[125:132]", "v[126:133]", "v[127:134]", "v[128:135]", "v[129:136]",
"v[130:137]", "v[131:138]", "v[132:139]", "v[133:140]", "v[134:141]",
"v[135:142]", "v[136:143]", "v[137:144]", "v[138:145]", "v[139:146]",
"v[140:147]", "v[141:148]", "v[142:149]", "v[143:150]", "v[144:151]",
"v[145:152]", "v[146:153]", "v[147:154]", "v[148:155]", "v[149:156]",
"v[150:157]", "v[151:158]", "v[152:159]", "v[153:160]", "v[154:161]",
"v[155:162]", "v[156:163]", "v[157:164]", "v[158:165]", "v[159:166]",
"v[160:167]", "v[161:168]", "v[162:169]", "v[163:170]", "v[164:171]",
"v[165:172]", "v[166:173]", "v[167:174]", "v[168:175]", "v[169:176]",
"v[170:177]", "v[171:178]", "v[172:179]", "v[173:180]", "v[174:181]",
"v[175:182]", "v[176:183]", "v[177:184]", "v[178:185]", "v[179:186]",
"v[180:187]", "v[181:188]", "v[182:189]", "v[183:190]", "v[184:191]",
"v[185:192]", "v[186:193]", "v[187:194]", "v[188:195]", "v[189:196]",
"v[190:197]", "v[191:198]", "v[192:199]", "v[193:200]", "v[194:201]",
"v[195:202]", "v[196:203]", "v[197:204]", "v[198:205]", "v[199:206]",
"v[200:207]", "v[201:208]", "v[202:209]", "v[203:210]", "v[204:211]",
"v[205:212]", "v[206:213]", "v[207:214]", "v[208:215]", "v[209:216]",
"v[210:217]", "v[211:218]", "v[212:219]", "v[213:220]", "v[214:221]",
"v[215:222]", "v[216:223]", "v[217:224]", "v[218:225]", "v[219:226]",
"v[220:227]", "v[221:228]", "v[222:229]", "v[223:230]", "v[224:231]",
"v[225:232]", "v[226:233]", "v[227:234]", "v[228:235]", "v[229:236]",
"v[230:237]", "v[231:238]", "v[232:239]", "v[233:240]", "v[234:241]",
"v[235:242]", "v[236:243]", "v[237:244]", "v[238:245]", "v[239:246]",
"v[240:247]", "v[241:248]", "v[242:249]", "v[243:250]", "v[244:251]",
"v[245:252]", "v[246:253]", "v[247:254]", "v[248:255]"
};
static const char *const VGPR512RegNames[] = {
"v[0:15]", "v[1:16]", "v[2:17]", "v[3:18]", "v[4:19]",
"v[5:20]", "v[6:21]", "v[7:22]", "v[8:23]", "v[9:24]",
"v[10:25]", "v[11:26]", "v[12:27]", "v[13:28]", "v[14:29]",
"v[15:30]", "v[16:31]", "v[17:32]", "v[18:33]", "v[19:34]",
"v[20:35]", "v[21:36]", "v[22:37]", "v[23:38]", "v[24:39]",
"v[25:40]", "v[26:41]", "v[27:42]", "v[28:43]", "v[29:44]",
"v[30:45]", "v[31:46]", "v[32:47]", "v[33:48]", "v[34:49]",
"v[35:50]", "v[36:51]", "v[37:52]", "v[38:53]", "v[39:54]",
"v[40:55]", "v[41:56]", "v[42:57]", "v[43:58]", "v[44:59]",
"v[45:60]", "v[46:61]", "v[47:62]", "v[48:63]", "v[49:64]",
"v[50:65]", "v[51:66]", "v[52:67]", "v[53:68]", "v[54:69]",
"v[55:70]", "v[56:71]", "v[57:72]", "v[58:73]", "v[59:74]",
"v[60:75]", "v[61:76]", "v[62:77]", "v[63:78]", "v[64:79]",
"v[65:80]", "v[66:81]", "v[67:82]", "v[68:83]", "v[69:84]",
"v[70:85]", "v[71:86]", "v[72:87]", "v[73:88]", "v[74:89]",
"v[75:90]", "v[76:91]", "v[77:92]", "v[78:93]", "v[79:94]",
"v[80:95]", "v[81:96]", "v[82:97]", "v[83:98]", "v[84:99]",
"v[85:100]", "v[86:101]", "v[87:102]", "v[88:103]", "v[89:104]",
"v[90:105]", "v[91:106]", "v[92:107]", "v[93:108]", "v[94:109]",
"v[95:110]", "v[96:111]", "v[97:112]", "v[98:113]", "v[99:114]",
"v[100:115]", "v[101:116]", "v[102:117]", "v[103:118]", "v[104:119]",
"v[105:120]", "v[106:121]", "v[107:122]", "v[108:123]", "v[109:124]",
"v[110:125]", "v[111:126]", "v[112:127]", "v[113:128]", "v[114:129]",
"v[115:130]", "v[116:131]", "v[117:132]", "v[118:133]", "v[119:134]",
"v[120:135]", "v[121:136]", "v[122:137]", "v[123:138]", "v[124:139]",
"v[125:140]", "v[126:141]", "v[127:142]", "v[128:143]", "v[129:144]",
"v[130:145]", "v[131:146]", "v[132:147]", "v[133:148]", "v[134:149]",
"v[135:150]", "v[136:151]", "v[137:152]", "v[138:153]", "v[139:154]",
"v[140:155]", "v[141:156]", "v[142:157]", "v[143:158]", "v[144:159]",
"v[145:160]", "v[146:161]", "v[147:162]", "v[148:163]", "v[149:164]",
"v[150:165]", "v[151:166]", "v[152:167]", "v[153:168]", "v[154:169]",
"v[155:170]", "v[156:171]", "v[157:172]", "v[158:173]", "v[159:174]",
"v[160:175]", "v[161:176]", "v[162:177]", "v[163:178]", "v[164:179]",
"v[165:180]", "v[166:181]", "v[167:182]", "v[168:183]", "v[169:184]",
"v[170:185]", "v[171:186]", "v[172:187]", "v[173:188]", "v[174:189]",
"v[175:190]", "v[176:191]", "v[177:192]", "v[178:193]", "v[179:194]",
"v[180:195]", "v[181:196]", "v[182:197]", "v[183:198]", "v[184:199]",
"v[185:200]", "v[186:201]", "v[187:202]", "v[188:203]", "v[189:204]",
"v[190:205]", "v[191:206]", "v[192:207]", "v[193:208]", "v[194:209]",
"v[195:210]", "v[196:211]", "v[197:212]", "v[198:213]", "v[199:214]",
"v[200:215]", "v[201:216]", "v[202:217]", "v[203:218]", "v[204:219]",
"v[205:220]", "v[206:221]", "v[207:222]", "v[208:223]", "v[209:224]",
"v[210:225]", "v[211:226]", "v[212:227]", "v[213:228]", "v[214:229]",
"v[215:230]", "v[216:231]", "v[217:232]", "v[218:233]", "v[219:234]",
"v[220:235]", "v[221:236]", "v[222:237]", "v[223:238]", "v[224:239]",
"v[225:240]", "v[226:241]", "v[227:242]", "v[228:243]", "v[229:244]",
"v[230:245]", "v[231:246]", "v[232:247]", "v[233:248]", "v[234:249]",
"v[235:250]", "v[236:251]", "v[237:252]", "v[238:253]", "v[239:254]",
"v[240:255]"
};
static const char *const SGPR64RegNames[] = {
"s[0:1]", "s[2:3]", "s[4:5]", "s[6:7]", "s[8:9]", "s[10:11]",
"s[12:13]", "s[14:15]", "s[16:17]", "s[18:19]", "s[20:21]", "s[22:23]",
"s[24:25]", "s[26:27]", "s[28:29]", "s[30:31]", "s[32:33]", "s[34:35]",
"s[36:37]", "s[38:39]", "s[40:41]", "s[42:43]", "s[44:45]", "s[46:47]",
"s[48:49]", "s[50:51]", "s[52:53]", "s[54:55]", "s[56:57]", "s[58:59]",
"s[60:61]", "s[62:63]", "s[64:65]", "s[66:67]", "s[68:69]", "s[70:71]",
"s[72:73]", "s[74:75]", "s[76:77]", "s[78:79]", "s[80:81]", "s[82:83]",
"s[84:85]", "s[86:87]", "s[88:89]", "s[90:91]", "s[92:93]", "s[94:95]",
"s[96:97]", "s[98:99]", "s[100:101]", "s[102:103]", "s[104:105]"
};
static const char *const SGPR128RegNames[] = {
"s[0:3]", "s[4:7]", "s[8:11]", "s[12:15]", "s[16:19]", "s[20:23]",
"s[24:27]", "s[28:31]", "s[32:35]", "s[36:39]", "s[40:43]", "s[44:47]",
"s[48:51]", "s[52:55]", "s[56:59]", "s[60:63]", "s[64:67]", "s[68:71]",
"s[72:75]", "s[76:79]", "s[80:83]", "s[84:87]", "s[88:91]", "s[92:95]",
"s[96:99]", "s[100:103]"
};
static const char *const SGPR256RegNames[] = {
"s[0:7]", "s[4:11]", "s[8:15]", "s[12:19]", "s[16:23]",
"s[20:27]", "s[24:31]", "s[28:35]", "s[32:39]", "s[36:43]",
"s[40:47]", "s[44:51]", "s[48:55]", "s[52:59]", "s[56:63]",
"s[60:67]", "s[64:71]", "s[68:75]", "s[72:79]", "s[76:83]",
"s[80:87]", "s[84:91]", "s[88:95]", "s[92:99]", "s[96:103]"
};
static const char *const SGPR512RegNames[] = {
"s[0:15]", "s[4:19]", "s[8:23]", "s[12:27]", "s[16:31]", "s[20:35]",
"s[24:39]", "s[28:43]", "s[32:47]", "s[36:51]", "s[40:55]", "s[44:59]",
"s[48:63]", "s[52:67]", "s[56:71]", "s[60:75]", "s[64:79]", "s[68:83]",
"s[72:87]", "s[76:91]", "s[80:95]", "s[84:99]", "s[88:103]"
};
static const char *const AGPR32RegNames[] = {
"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8",
"a9", "a10", "a11", "a12", "a13", "a14", "a15", "a16", "a17",
"a18", "a19", "a20", "a21", "a22", "a23", "a24", "a25", "a26",
"a27", "a28", "a29", "a30", "a31", "a32", "a33", "a34", "a35",
"a36", "a37", "a38", "a39", "a40", "a41", "a42", "a43", "a44",
"a45", "a46", "a47", "a48", "a49", "a50", "a51", "a52", "a53",
"a54", "a55", "a56", "a57", "a58", "a59", "a60", "a61", "a62",
"a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", "a71",
"a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80",
"a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89",
"a90", "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98",
"a99", "a100", "a101", "a102", "a103", "a104", "a105", "a106", "a107",
"a108", "a109", "a110", "a111", "a112", "a113", "a114", "a115", "a116",
"a117", "a118", "a119", "a120", "a121", "a122", "a123", "a124", "a125",
"a126", "a127", "a128", "a129", "a130", "a131", "a132", "a133", "a134",
"a135", "a136", "a137", "a138", "a139", "a140", "a141", "a142", "a143",
"a144", "a145", "a146", "a147", "a148", "a149", "a150", "a151", "a152",
"a153", "a154", "a155", "a156", "a157", "a158", "a159", "a160", "a161",
"a162", "a163", "a164", "a165", "a166", "a167", "a168", "a169", "a170",
"a171", "a172", "a173", "a174", "a175", "a176", "a177", "a178", "a179",
"a180", "a181", "a182", "a183", "a184", "a185", "a186", "a187", "a188",
"a189", "a190", "a191", "a192", "a193", "a194", "a195", "a196", "a197",
"a198", "a199", "a200", "a201", "a202", "a203", "a204", "a205", "a206",
"a207", "a208", "a209", "a210", "a211", "a212", "a213", "a214", "a215",
"a216", "a217", "a218", "a219", "a220", "a221", "a222", "a223", "a224",
"a225", "a226", "a227", "a228", "a229", "a230", "a231", "a232", "a233",
"a234", "a235", "a236", "a237", "a238", "a239", "a240", "a241", "a242",
"a243", "a244", "a245", "a246", "a247", "a248", "a249", "a250", "a251",
"a252", "a253", "a254", "a255"
};
static const char *const AGPR64RegNames[] = {
"a[0:1]", "a[1:2]", "a[2:3]", "a[3:4]", "a[4:5]",
"a[5:6]", "a[6:7]", "a[7:8]", "a[8:9]", "a[9:10]",
"a[10:11]", "a[11:12]", "a[12:13]", "a[13:14]", "a[14:15]",
"a[15:16]", "a[16:17]", "a[17:18]", "a[18:19]", "a[19:20]",
"a[20:21]", "a[21:22]", "a[22:23]", "a[23:24]", "a[24:25]",
"a[25:26]", "a[26:27]", "a[27:28]", "a[28:29]", "a[29:30]",
"a[30:31]", "a[31:32]", "a[32:33]", "a[33:34]", "a[34:35]",
"a[35:36]", "a[36:37]", "a[37:38]", "a[38:39]", "a[39:40]",
"a[40:41]", "a[41:42]", "a[42:43]", "a[43:44]", "a[44:45]",
"a[45:46]", "a[46:47]", "a[47:48]", "a[48:49]", "a[49:50]",
"a[50:51]", "a[51:52]", "a[52:53]", "a[53:54]", "a[54:55]",
"a[55:56]", "a[56:57]", "a[57:58]", "a[58:59]", "a[59:60]",
"a[60:61]", "a[61:62]", "a[62:63]", "a[63:64]", "a[64:65]",
"a[65:66]", "a[66:67]", "a[67:68]", "a[68:69]", "a[69:70]",
"a[70:71]", "a[71:72]", "a[72:73]", "a[73:74]", "a[74:75]",
"a[75:76]", "a[76:77]", "a[77:78]", "a[78:79]", "a[79:80]",
"a[80:81]", "a[81:82]", "a[82:83]", "a[83:84]", "a[84:85]",
"a[85:86]", "a[86:87]", "a[87:88]", "a[88:89]", "a[89:90]",
"a[90:91]", "a[91:92]", "a[92:93]", "a[93:94]", "a[94:95]",
"a[95:96]", "a[96:97]", "a[97:98]", "a[98:99]", "a[99:100]",
"a[100:101]", "a[101:102]", "a[102:103]", "a[103:104]", "a[104:105]",
"a[105:106]", "a[106:107]", "a[107:108]", "a[108:109]", "a[109:110]",
"a[110:111]", "a[111:112]", "a[112:113]", "a[113:114]", "a[114:115]",
"a[115:116]", "a[116:117]", "a[117:118]", "a[118:119]", "a[119:120]",
"a[120:121]", "a[121:122]", "a[122:123]", "a[123:124]", "a[124:125]",
"a[125:126]", "a[126:127]", "a[127:128]", "a[128:129]", "a[129:130]",
"a[130:131]", "a[131:132]", "a[132:133]", "a[133:134]", "a[134:135]",
"a[135:136]", "a[136:137]", "a[137:138]", "a[138:139]", "a[139:140]",
"a[140:141]", "a[141:142]", "a[142:143]", "a[143:144]", "a[144:145]",
"a[145:146]", "a[146:147]", "a[147:148]", "a[148:149]", "a[149:150]",
"a[150:151]", "a[151:152]", "a[152:153]", "a[153:154]", "a[154:155]",
"a[155:156]", "a[156:157]", "a[157:158]", "a[158:159]", "a[159:160]",
"a[160:161]", "a[161:162]", "a[162:163]", "a[163:164]", "a[164:165]",
"a[165:166]", "a[166:167]", "a[167:168]", "a[168:169]", "a[169:170]",
"a[170:171]", "a[171:172]", "a[172:173]", "a[173:174]", "a[174:175]",
"a[175:176]", "a[176:177]", "a[177:178]", "a[178:179]", "a[179:180]",
"a[180:181]", "a[181:182]", "a[182:183]", "a[183:184]", "a[184:185]",
"a[185:186]", "a[186:187]", "a[187:188]", "a[188:189]", "a[189:190]",
"a[190:191]", "a[191:192]", "a[192:193]", "a[193:194]", "a[194:195]",
"a[195:196]", "a[196:197]", "a[197:198]", "a[198:199]", "a[199:200]",
"a[200:201]", "a[201:202]", "a[202:203]", "a[203:204]", "a[204:205]",
"a[205:206]", "a[206:207]", "a[207:208]", "a[208:209]", "a[209:210]",
"a[210:211]", "a[211:212]", "a[212:213]", "a[213:214]", "a[214:215]",
"a[215:216]", "a[216:217]", "a[217:218]", "a[218:219]", "a[219:220]",
"a[220:221]", "a[221:222]", "a[222:223]", "a[223:224]", "a[224:225]",
"a[225:226]", "a[226:227]", "a[227:228]", "a[228:229]", "a[229:230]",
"a[230:231]", "a[231:232]", "a[232:233]", "a[233:234]", "a[234:235]",
"a[235:236]", "a[236:237]", "a[237:238]", "a[238:239]", "a[239:240]",
"a[240:241]", "a[241:242]", "a[242:243]", "a[243:244]", "a[244:245]",
"a[245:246]", "a[246:247]", "a[247:248]", "a[248:249]", "a[249:250]",
"a[250:251]", "a[251:252]", "a[252:253]", "a[253:254]", "a[254:255]"
};
static const char *const AGPR128RegNames[] = {
"a[0:3]", "a[1:4]", "a[2:5]", "a[3:6]", "a[4:7]",
"a[5:8]", "a[6:9]", "a[7:10]", "a[8:11]", "a[9:12]",
"a[10:13]", "a[11:14]", "a[12:15]", "a[13:16]", "a[14:17]",
"a[15:18]", "a[16:19]", "a[17:20]", "a[18:21]", "a[19:22]",
"a[20:23]", "a[21:24]", "a[22:25]", "a[23:26]", "a[24:27]",
"a[25:28]", "a[26:29]", "a[27:30]", "a[28:31]", "a[29:32]",
"a[30:33]", "a[31:34]", "a[32:35]", "a[33:36]", "a[34:37]",
"a[35:38]", "a[36:39]", "a[37:40]", "a[38:41]", "a[39:42]",
"a[40:43]", "a[41:44]", "a[42:45]", "a[43:46]", "a[44:47]",
"a[45:48]", "a[46:49]", "a[47:50]", "a[48:51]", "a[49:52]",
"a[50:53]", "a[51:54]", "a[52:55]", "a[53:56]", "a[54:57]",
"a[55:58]", "a[56:59]", "a[57:60]", "a[58:61]", "a[59:62]",
"a[60:63]", "a[61:64]", "a[62:65]", "a[63:66]", "a[64:67]",
"a[65:68]", "a[66:69]", "a[67:70]", "a[68:71]", "a[69:72]",
"a[70:73]", "a[71:74]", "a[72:75]", "a[73:76]", "a[74:77]",
"a[75:78]", "a[76:79]", "a[77:80]", "a[78:81]", "a[79:82]",
"a[80:83]", "a[81:84]", "a[82:85]", "a[83:86]", "a[84:87]",
"a[85:88]", "a[86:89]", "a[87:90]", "a[88:91]", "a[89:92]",
"a[90:93]", "a[91:94]", "a[92:95]", "a[93:96]", "a[94:97]",
"a[95:98]", "a[96:99]", "a[97:100]", "a[98:101]", "a[99:102]",
"a[100:103]", "a[101:104]", "a[102:105]", "a[103:106]", "a[104:107]",
"a[105:108]", "a[106:109]", "a[107:110]", "a[108:111]", "a[109:112]",
"a[110:113]", "a[111:114]", "a[112:115]", "a[113:116]", "a[114:117]",
"a[115:118]", "a[116:119]", "a[117:120]", "a[118:121]", "a[119:122]",
"a[120:123]", "a[121:124]", "a[122:125]", "a[123:126]", "a[124:127]",
"a[125:128]", "a[126:129]", "a[127:130]", "a[128:131]", "a[129:132]",
"a[130:133]", "a[131:134]", "a[132:135]", "a[133:136]", "a[134:137]",
"a[135:138]", "a[136:139]", "a[137:140]", "a[138:141]", "a[139:142]",
"a[140:143]", "a[141:144]", "a[142:145]", "a[143:146]", "a[144:147]",
"a[145:148]", "a[146:149]", "a[147:150]", "a[148:151]", "a[149:152]",
"a[150:153]", "a[151:154]", "a[152:155]", "a[153:156]", "a[154:157]",
"a[155:158]", "a[156:159]", "a[157:160]", "a[158:161]", "a[159:162]",
"a[160:163]", "a[161:164]", "a[162:165]", "a[163:166]", "a[164:167]",
"a[165:168]", "a[166:169]", "a[167:170]", "a[168:171]", "a[169:172]",
"a[170:173]", "a[171:174]", "a[172:175]", "a[173:176]", "a[174:177]",
"a[175:178]", "a[176:179]", "a[177:180]", "a[178:181]", "a[179:182]",
"a[180:183]", "a[181:184]", "a[182:185]", "a[183:186]", "a[184:187]",
"a[185:188]", "a[186:189]", "a[187:190]", "a[188:191]", "a[189:192]",
"a[190:193]", "a[191:194]", "a[192:195]", "a[193:196]", "a[194:197]",
"a[195:198]", "a[196:199]", "a[197:200]", "a[198:201]", "a[199:202]",
"a[200:203]", "a[201:204]", "a[202:205]", "a[203:206]", "a[204:207]",
"a[205:208]", "a[206:209]", "a[207:210]", "a[208:211]", "a[209:212]",
"a[210:213]", "a[211:214]", "a[212:215]", "a[213:216]", "a[214:217]",
"a[215:218]", "a[216:219]", "a[217:220]", "a[218:221]", "a[219:222]",
"a[220:223]", "a[221:224]", "a[222:225]", "a[223:226]", "a[224:227]",
"a[225:228]", "a[226:229]", "a[227:230]", "a[228:231]", "a[229:232]",
"a[230:233]", "a[231:234]", "a[232:235]", "a[233:236]", "a[234:237]",
"a[235:238]", "a[236:239]", "a[237:240]", "a[238:241]", "a[239:242]",
"a[240:243]", "a[241:244]", "a[242:245]", "a[243:246]", "a[244:247]",
"a[245:248]", "a[246:249]", "a[247:250]", "a[248:251]", "a[249:252]",
"a[250:253]", "a[251:254]", "a[252:255]"
};
static const char *const AGPR512RegNames[] = {
"a[0:15]", "a[1:16]", "a[2:17]", "a[3:18]", "a[4:19]",
"a[5:20]", "a[6:21]", "a[7:22]", "a[8:23]", "a[9:24]",
"a[10:25]", "a[11:26]", "a[12:27]", "a[13:28]", "a[14:29]",
"a[15:30]", "a[16:31]", "a[17:32]", "a[18:33]", "a[19:34]",
"a[20:35]", "a[21:36]", "a[22:37]", "a[23:38]", "a[24:39]",
"a[25:40]", "a[26:41]", "a[27:42]", "a[28:43]", "a[29:44]",
"a[30:45]", "a[31:46]", "a[32:47]", "a[33:48]", "a[34:49]",
"a[35:50]", "a[36:51]", "a[37:52]", "a[38:53]", "a[39:54]",
"a[40:55]", "a[41:56]", "a[42:57]", "a[43:58]", "a[44:59]",
"a[45:60]", "a[46:61]", "a[47:62]", "a[48:63]", "a[49:64]",
"a[50:65]", "a[51:66]", "a[52:67]", "a[53:68]", "a[54:69]",
"a[55:70]", "a[56:71]", "a[57:72]", "a[58:73]", "a[59:74]",
"a[60:75]", "a[61:76]", "a[62:77]", "a[63:78]", "a[64:79]",
"a[65:80]", "a[66:81]", "a[67:82]", "a[68:83]", "a[69:84]",
"a[70:85]", "a[71:86]", "a[72:87]", "a[73:88]", "a[74:89]",
"a[75:90]", "a[76:91]", "a[77:92]", "a[78:93]", "a[79:94]",
"a[80:95]", "a[81:96]", "a[82:97]", "a[83:98]", "a[84:99]",
"a[85:100]", "a[86:101]", "a[87:102]", "a[88:103]", "a[89:104]",
"a[90:105]", "a[91:106]", "a[92:107]", "a[93:108]", "a[94:109]",
"a[95:110]", "a[96:111]", "a[97:112]", "a[98:113]", "a[99:114]",
"a[100:115]", "a[101:116]", "a[102:117]", "a[103:118]", "a[104:119]",
"a[105:120]", "a[106:121]", "a[107:122]", "a[108:123]", "a[109:124]",
"a[110:125]", "a[111:126]", "a[112:127]", "a[113:128]", "a[114:129]",
"a[115:130]", "a[116:131]", "a[117:132]", "a[118:133]", "a[119:134]",
"a[120:135]", "a[121:136]", "a[122:137]", "a[123:138]", "a[124:139]",
"a[125:140]", "a[126:141]", "a[127:142]", "a[128:143]", "a[129:144]",
"a[130:145]", "a[131:146]", "a[132:147]", "a[133:148]", "a[134:149]",
"a[135:150]", "a[136:151]", "a[137:152]", "a[138:153]", "a[139:154]",
"a[140:155]", "a[141:156]", "a[142:157]", "a[143:158]", "a[144:159]",
"a[145:160]", "a[146:161]", "a[147:162]", "a[148:163]", "a[149:164]",
"a[150:165]", "a[151:166]", "a[152:167]", "a[153:168]", "a[154:169]",
"a[155:170]", "a[156:171]", "a[157:172]", "a[158:173]", "a[159:174]",
"a[160:175]", "a[161:176]", "a[162:177]", "a[163:178]", "a[164:179]",
"a[165:180]", "a[166:181]", "a[167:182]", "a[168:183]", "a[169:184]",
"a[170:185]", "a[171:186]", "a[172:187]", "a[173:188]", "a[174:189]",
"a[175:190]", "a[176:191]", "a[177:192]", "a[178:193]", "a[179:194]",
"a[180:195]", "a[181:196]", "a[182:197]", "a[183:198]", "a[184:199]",
"a[185:200]", "a[186:201]", "a[187:202]", "a[188:203]", "a[189:204]",
"a[190:205]", "a[191:206]", "a[192:207]", "a[193:208]", "a[194:209]",
"a[195:210]", "a[196:211]", "a[197:212]", "a[198:213]", "a[199:214]",
"a[200:215]", "a[201:216]", "a[202:217]", "a[203:218]", "a[204:219]",
"a[205:220]", "a[206:221]", "a[207:222]", "a[208:223]", "a[209:224]",
"a[210:225]", "a[211:226]", "a[212:227]", "a[213:228]", "a[214:229]",
"a[215:230]", "a[216:231]", "a[217:232]", "a[218:233]", "a[219:234]",
"a[220:235]", "a[221:236]", "a[222:237]", "a[223:238]", "a[224:239]",
"a[225:240]", "a[226:241]", "a[227:242]", "a[228:243]", "a[229:244]",
"a[230:245]", "a[231:246]", "a[232:247]", "a[233:248]", "a[234:249]",
"a[235:250]", "a[236:251]", "a[237:252]", "a[238:253]", "a[239:254]",
"a[240:255]"
};
static const char *const AGPR1024RegNames[] = {
"a[0:31]", "a[1:32]", "a[2:33]", "a[3:34]", "a[4:35]",
"a[5:36]", "a[6:37]", "a[7:38]", "a[8:39]", "a[9:40]",
"a[10:41]", "a[11:42]", "a[12:43]", "a[13:44]", "a[14:45]",
"a[15:46]", "a[16:47]", "a[17:48]", "a[18:49]", "a[19:50]",
"a[20:51]", "a[21:52]", "a[22:53]", "a[23:54]", "a[24:55]",
"a[25:56]", "a[26:57]", "a[27:58]", "a[28:59]", "a[29:60]",
"a[30:61]", "a[31:62]", "a[32:63]", "a[33:64]", "a[34:65]",
"a[35:66]", "a[36:67]", "a[37:68]", "a[38:69]", "a[39:70]",
"a[40:71]", "a[41:72]", "a[42:73]", "a[43:74]", "a[44:75]",
"a[45:76]", "a[46:77]", "a[47:78]", "a[48:79]", "a[49:80]",
"a[50:81]", "a[51:82]", "a[52:83]", "a[53:84]", "a[54:85]",
"a[55:86]", "a[56:87]", "a[57:88]", "a[58:89]", "a[59:90]",
"a[60:91]", "a[61:92]", "a[62:93]", "a[63:94]", "a[64:95]",
"a[65:96]", "a[66:97]", "a[67:98]", "a[68:99]", "a[69:100]",
"a[70:101]", "a[71:102]", "a[72:103]", "a[73:104]", "a[74:105]",
"a[75:106]", "a[76:107]", "a[77:108]", "a[78:109]", "a[79:110]",
"a[80:111]", "a[81:112]", "a[82:113]", "a[83:114]", "a[84:115]",
"a[85:116]", "a[86:117]", "a[87:118]", "a[88:119]", "a[89:120]",
"a[90:121]", "a[91:122]", "a[92:123]", "a[93:124]", "a[94:125]",
"a[95:126]", "a[96:127]", "a[97:128]", "a[98:129]", "a[99:130]",
"a[100:131]", "a[101:132]", "a[102:133]", "a[103:134]", "a[104:135]",
"a[105:136]", "a[106:137]", "a[107:138]", "a[108:139]", "a[109:140]",
"a[110:141]", "a[111:142]", "a[112:143]", "a[113:144]", "a[114:145]",
"a[115:146]", "a[116:147]", "a[117:148]", "a[118:149]", "a[119:150]",
"a[120:151]", "a[121:152]", "a[122:153]", "a[123:154]", "a[124:155]",
"a[125:156]", "a[126:157]", "a[127:158]", "a[128:159]", "a[129:160]",
"a[130:161]", "a[131:162]", "a[132:163]", "a[133:164]", "a[134:165]",
"a[135:166]", "a[136:167]", "a[137:168]", "a[138:169]", "a[139:170]",
"a[140:171]", "a[141:172]", "a[142:173]", "a[143:174]", "a[144:175]",
"a[145:176]", "a[146:177]", "a[147:178]", "a[148:179]", "a[149:180]",
"a[150:181]", "a[151:182]", "a[152:183]", "a[153:184]", "a[154:185]",
"a[155:186]", "a[156:187]", "a[157:188]", "a[158:189]", "a[159:190]",
"a[160:191]", "a[161:192]", "a[162:193]", "a[163:194]", "a[164:195]",
"a[165:196]", "a[166:197]", "a[167:198]", "a[168:199]", "a[169:200]",
"a[170:201]", "a[171:202]", "a[172:203]", "a[173:204]", "a[174:205]",
"a[175:206]", "a[176:207]", "a[177:208]", "a[178:209]", "a[179:210]",
"a[180:211]", "a[181:212]", "a[182:213]", "a[183:214]", "a[184:215]",
"a[185:216]", "a[186:217]", "a[187:218]", "a[188:219]", "a[189:220]",
"a[190:221]", "a[191:222]", "a[192:223]", "a[193:224]", "a[194:225]",
"a[195:226]", "a[196:227]", "a[197:228]", "a[198:229]", "a[199:230]",
"a[200:231]", "a[201:232]", "a[202:233]", "a[203:234]", "a[204:235]",
"a[205:236]", "a[206:237]", "a[207:238]", "a[208:239]", "a[209:240]",
"a[210:241]", "a[211:242]", "a[212:243]", "a[213:244]", "a[214:245]",
"a[215:246]", "a[216:247]", "a[217:248]", "a[218:249]", "a[219:250]",
"a[220:251]", "a[221:252]", "a[222:253]", "a[223:254]", "a[224:255]"
};
#endif

lib/Target/AMDGPU/CMakeLists.txt

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesadd_llvm_target(AMDGPUCodeGen
AMDGPUMachineCFGStructurizer.cpp AMDGPUMachineCFGStructurizer.cpp
AMDGPUMachineFunction.cpp AMDGPUMachineFunction.cpp
AMDGPUMachineModuleInfo.cpp AMDGPUMachineModuleInfo.cpp
AMDGPUMacroFusion.cpp AMDGPUMacroFusion.cpp
AMDGPUMCInstLower.cpp AMDGPUMCInstLower.cpp
AMDGPUOpenCLEnqueuedBlockLowering.cpp AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPUPromoteAlloca.cpp AMDGPUPromoteAlloca.cpp
AMDGPUPropagateAttributes.cpp AMDGPUPropagateAttributes.cpp
AMDGPURegAsmNames.inc.cpp
AMDGPURegisterBankInfo.cpp AMDGPURegisterBankInfo.cpp
AMDGPURegisterInfo.cpp AMDGPURegisterInfo.cpp
AMDGPURewriteOutArguments.cpp AMDGPURewriteOutArguments.cpp
AMDGPUSubtarget.cpp AMDGPUSubtarget.cpp
AMDGPUTargetMachine.cpp AMDGPUTargetMachine.cpp
AMDGPUTargetObjectFile.cpp AMDGPUTargetObjectFile.cpp
AMDGPUTargetTransformInfo.cpp AMDGPUTargetTransformInfo.cpp
AMDGPUUnifyDivergentExitNodes.cpp AMDGPUUnifyDivergentExitNodes.cpp
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

//===-- AMDGPUInstPrinter.h - AMDGPU MC Inst -> ASM interface ---*- C++ -*-===// //===-- AMDGPUInstPrinter.h - AMDGPU MC Inst -> ASM interface ---*- C++ -*-===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
/// \file /// \file
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUINSTPRINTER_H #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUINSTPRINTER_H
#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUINSTPRINTER_H #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUINSTPRINTER_H
#include "AMDGPUMCTargetDesc.h"
#include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCInstPrinter.h"
namespace llvm { namespace llvm {
class AMDGPUInstPrinter : public MCInstPrinter { class AMDGPUInstPrinter : public MCInstPrinter {
public: public:
AMDGPUInstPrinter(const MCAsmInfo &MAI, AMDGPUInstPrinter(const MCAsmInfo &MAI,
const MCInstrInfo &MII, const MCRegisterInfo &MRI) const MCInstrInfo &MII, const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI) {} : MCInstPrinter(MAI, MII, MRI) {}
//Autogenerated by tblgen //Autogenerated by tblgen
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo,
unsigned AltIdx = AMDGPU::NoRegAltName);
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
const MCSubtargetInfo &STI) override; const MCSubtargetInfo &STI) override;
static void printRegOperand(unsigned RegNo, raw_ostream &O, static void printRegOperand(unsigned RegNo, raw_ostream &O,
const MCRegisterInfo &MRI); const MCRegisterInfo &MRI);
private: private:
void printU4ImmOperand(const MCInst *MI, unsigned OpNo, void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
▲ Show 20 Lines • Show All 230 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIRegisterInfo.cpp

Show All 10 Lines
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "SIRegisterInfo.h" #include "SIRegisterInfo.h"
#include "AMDGPURegisterBankInfo.h" #include "AMDGPURegisterBankInfo.h"
#include "AMDGPUSubtarget.h" #include "AMDGPUSubtarget.h"
#include "SIInstrInfo.h" #include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h" #include "SIMachineFunctionInfo.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
▲ Show 20 Lines • Show All 1,314 Lines • ▼ Show 20 Lines default: {
.addImm(Offset); .addImm(Offset);
FIOp.ChangeToRegister(TmpReg, false, false, true); FIOp.ChangeToRegister(TmpReg, false, false, true);
} }
} }
} }
} }
StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const { StringRef SIRegisterInfo::getRegAsmName(unsigned Reg) const {
#define AMDGPU_REG_ASM_NAMES
#include "AMDGPURegAsmNames.inc.cpp"
#define REG_RANGE(BeginReg, EndReg, RegTable) \
if (Reg >= BeginReg && Reg <= EndReg) { \
unsigned Index = Reg - BeginReg; \
assert(Index < array_lengthof(RegTable)); \
return RegTable[Index]; \
}
REG_RANGE(AMDGPU::VGPR0, AMDGPU::VGPR255, VGPR32RegNames);
REG_RANGE(AMDGPU::SGPR0, AMDGPU::SGPR105, SGPR32RegNames);
REG_RANGE(AMDGPU::AGPR0, AMDGPU::AGPR255, AGPR32RegNames);
REG_RANGE(AMDGPU::VGPR0_VGPR1, AMDGPU::VGPR254_VGPR255, VGPR64RegNames);
REG_RANGE(AMDGPU::SGPR0_SGPR1, AMDGPU::SGPR104_SGPR105, SGPR64RegNames);
REG_RANGE(AMDGPU::AGPR0_AGPR1, AMDGPU::AGPR254_AGPR255, AGPR64RegNames);
REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2, AMDGPU::VGPR253_VGPR254_VGPR255,
VGPR96RegNames);
REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3,
AMDGPU::VGPR252_VGPR253_VGPR254_VGPR255,
VGPR128RegNames);
REG_RANGE(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3,
AMDGPU::SGPR100_SGPR101_SGPR102_SGPR103,
SGPR128RegNames);
REG_RANGE(AMDGPU::AGPR0_AGPR1_AGPR2_AGPR3,
AMDGPU::AGPR252_AGPR253_AGPR254_AGPR255,
AGPR128RegNames);
REG_RANGE(AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7,
AMDGPU::VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255,
VGPR256RegNames);
REG_RANGE(
AMDGPU::VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7_VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15,
AMDGPU::VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247_VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255,
VGPR512RegNames);
REG_RANGE(
AMDGPU::AGPR0_AGPR1_AGPR2_AGPR3_AGPR4_AGPR5_AGPR6_AGPR7_AGPR8_AGPR9_AGPR10_AGPR11_AGPR12_AGPR13_AGPR14_AGPR15,
AMDGPU::AGPR240_AGPR241_AGPR242_AGPR243_AGPR244_AGPR245_AGPR246_AGPR247_AGPR248_AGPR249_AGPR250_AGPR251_AGPR252_AGPR253_AGPR254_AGPR255,
AGPR512RegNames);
REG_RANGE(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7,
AMDGPU::SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103,
SGPR256RegNames);
REG_RANGE(
AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15,
AMDGPU::SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95_SGPR96_SGPR97_SGPR98_SGPR99_SGPR100_SGPR101_SGPR102_SGPR103,
SGPR512RegNames
);
REG_RANGE(
AMDGPU::AGPR0_AGPR1_AGPR2_AGPR3_AGPR4_AGPR5_AGPR6_AGPR7_AGPR8_AGPR9_AGPR10_AGPR11_AGPR12_AGPR13_AGPR14_AGPR15_AGPR16_AGPR17_AGPR18_AGPR19_AGPR20_AGPR21_AGPR22_AGPR23_AGPR24_AGPR25_AGPR26_AGPR27_AGPR28_AGPR29_AGPR30_AGPR31,
AMDGPU::AGPR224_AGPR225_AGPR226_AGPR227_AGPR228_AGPR229_AGPR230_AGPR231_AGPR232_AGPR233_AGPR234_AGPR235_AGPR236_AGPR237_AGPR238_AGPR239_AGPR240_AGPR241_AGPR242_AGPR243_AGPR244_AGPR245_AGPR246_AGPR247_AGPR248_AGPR249_AGPR250_AGPR251_AGPR252_AGPR253_AGPR254_AGPR255,
AGPR1024RegNames);
#undef REG_RANGE
// FIXME: Rename flat_scr so we don't need to special case this. // FIXME: Rename flat_scr so we don't need to special case this.
switch (Reg) { switch (Reg) {
case AMDGPU::FLAT_SCR: case AMDGPU::FLAT_SCR:
return "flat_scratch"; return "flat_scratch";
case AMDGPU::FLAT_SCR_LO: case AMDGPU::FLAT_SCR_LO:
return "flat_scratch_lo"; return "flat_scratch_lo";
case AMDGPU::FLAT_SCR_HI: case AMDGPU::FLAT_SCR_HI:
return "flat_scratch_hi"; return "flat_scratch_hi";
default: default:
// For the special named registers the default is fine. break;
return TargetRegisterInfo::getRegAsmName(Reg); }
const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
unsigned Size = getRegSizeInBits(*RC);
unsigned AltName = AMDGPU::NoRegAltName;
switch (Size) {
case 32: AltName = AMDGPU::Reg32; break;
case 64: AltName = AMDGPU::Reg64; break;
case 96: AltName = AMDGPU::Reg96; break;
case 128: AltName = AMDGPU::Reg128; break;
case 160: AltName = AMDGPU::Reg160; break;
case 256: AltName = AMDGPU::Reg256; break;
case 512: AltName = AMDGPU::Reg512; break;
case 1024: AltName = AMDGPU::Reg1024; break;
} }
return AMDGPUInstPrinter::getRegisterName(Reg, AltName);
} }
// FIXME: This is very slow. It might be worth creating a map from physreg to // FIXME: This is very slow. It might be worth creating a map from physreg to
// register class. // register class.
const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
assert(!TargetRegisterInfo::isVirtualRegister(Reg)); assert(!TargetRegisterInfo::isVirtualRegister(Reg));
static const TargetRegisterClass *const BaseClasses[] = { static const TargetRegisterClass *const BaseClasses[] = {
▲ Show 20 Lines • Show All 648 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIRegisterInfo.td

Show All 31 Linesclass getSubRegs<int size> {
list<SubRegIndex> ret = !if(!eq(size, 2), ret2, list<SubRegIndex> ret = !if(!eq(size, 2), ret2,
!if(!eq(size, 3), ret3, !if(!eq(size, 3), ret3,
!if(!eq(size, 4), ret4, !if(!eq(size, 4), ret4,
!if(!eq(size, 5), ret5, !if(!eq(size, 5), ret5,
!if(!eq(size, 8), ret8, !if(!eq(size, 8), ret8,
!if(!eq(size, 16), ret16, ret32)))))); !if(!eq(size, 16), ret16, ret32))))));
} }
let Namespace = "AMDGPU" in {
defset list<RegAltNameIndex> AllRegAltNameIndices = {
def Reg32 : RegAltNameIndex;
def Reg64 : RegAltNameIndex;
def Reg96 : RegAltNameIndex;
def Reg128 : RegAltNameIndex;
def Reg160 : RegAltNameIndex;
def Reg256 : RegAltNameIndex;
def Reg512 : RegAltNameIndex;
def Reg1024 : RegAltNameIndex;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Declarations that describe the SI registers // Declarations that describe the SI registers
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SIReg <string n, bits<16> regIdx = 0> : Register<n>, class SIReg <string n, bits<16> regIdx = 0, string prefix = "",
int regNo = !cast<int>(regIdx)> :
Register<n, !if(!eq(prefix, ""),
[ n, n, n, n, n, n, n, n ],
[ prefix # regNo,
prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
arsenmUnsubmitted
Not Done
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So this generates too many names, and then the extra SGPR ones just don't work?

arsenm: So this generates too many names, and then the extra SGPR ones just don't work?
rampitecAuthorUnsubmitted
Done
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It generates a practical minimum of used names with exception of:

  1. It generates overflow names, like v[255:0]. We do not use overflow regs, but in fact we could.
  2. It generates dups for special registers, but there are not too much of them.

Generic names can be dropped in a separate patch in favor of Reg32, but that will be a separate huge tests update. I thought of that but do not want to mix everything into a single change. I am also not sure how mir will live with square brackets and colons.

rampitec: It generates a practical minimum of used names with exception of: 1. It generates overflow…
prefix # "[" # regNo # ":" # !and(!add(regNo, 2), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 3), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 4), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 7), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 15), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 31), 255) # "]",
])>,
DwarfRegNum<[!cast<int>(HWEncoding)]> { DwarfRegNum<[!cast<int>(HWEncoding)]> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let RegAltNameIndices = AllRegAltNameIndices;
// This is the not yet the complete register encoding. An additional // This is the not yet the complete register encoding. An additional
// bit is set for VGPRs. // bit is set for VGPRs.
let HWEncoding = regIdx; let HWEncoding = regIdx;
} }
class SIRegisterWithSubRegs<string n, list<Register> subregs> :
RegisterWithSubRegs<n, subregs> {
let RegAltNameIndices = AllRegAltNameIndices;
let AltNames = [ n, n, n, n, n, n, n, n ];
}
// Special Registers // Special Registers
def VCC_LO : SIReg<"vcc_lo", 106>; def VCC_LO : SIReg<"vcc_lo", 106>;
def VCC_HI : SIReg<"vcc_hi", 107>; def VCC_HI : SIReg<"vcc_hi", 107>;
// Pseudo-registers: Used as placeholders during isel and immediately // Pseudo-registers: Used as placeholders during isel and immediately
// replaced, never seeing the verifier. // replaced, never seeing the verifier.
def PRIVATE_RSRC_REG : SIReg<"", 0>; def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>;
def FP_REG : SIReg<"", 0>; def FP_REG : SIReg<"fp", 0>;
def SP_REG : SIReg<"", 0>; def SP_REG : SIReg<"sp", 0>;
def SCRATCH_WAVE_OFFSET_REG : SIReg<"", 0>; def SCRATCH_WAVE_OFFSET_REG : SIReg<"scratch_wave_offset", 0>;
// VCC for 64-bit instructions // VCC for 64-bit instructions
def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>, def VCC : SIRegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
DwarfRegAlias<VCC_LO> { DwarfRegAlias<VCC_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 106; let HWEncoding = 106;
} }
def EXEC_LO : SIReg<"exec_lo", 126>; def EXEC_LO : SIReg<"exec_lo", 126>;
def EXEC_HI : SIReg<"exec_hi", 127>; def EXEC_HI : SIReg<"exec_hi", 127>;
def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>, def EXEC : SIRegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
DwarfRegAlias<EXEC_LO> { DwarfRegAlias<EXEC_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 126; let HWEncoding = 126;
} }
// 32-bit real registers, for MC only. // 32-bit real registers, for MC only.
// May be used with both 32-bit and 64-bit operands. // May be used with both 32-bit and 64-bit operands.
def SRC_VCCZ : SIReg<"src_vccz", 251>; def SRC_VCCZ : SIReg<"src_vccz", 251>;
def SRC_EXECZ : SIReg<"src_execz", 252>; def SRC_EXECZ : SIReg<"src_execz", 252>;
def SRC_SCC : SIReg<"src_scc", 253>; def SRC_SCC : SIReg<"src_scc", 253>;
// 1-bit pseudo register, for codegen only. // 1-bit pseudo register, for codegen only.
// Should never be emitted. // Should never be emitted.
def SCC : SIReg<"">; def SCC : SIReg<"scc">;
def M0 : SIReg <"m0", 124>; def M0 : SIReg <"m0", 124>;
def SGPR_NULL : SIReg<"null", 125>; def SGPR_NULL : SIReg<"null", 125>;
def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>; def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>;
def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>; def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>;
def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>; def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>;
def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>; def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>;
def SRC_POPS_EXITING_WAVE_ID : SIReg<"src_pops_exiting_wave_id", 239>; def SRC_POPS_EXITING_WAVE_ID : SIReg<"src_pops_exiting_wave_id", 239>;
def LDS_DIRECT : SIReg <"lds_direct", 254>; def LDS_DIRECT : SIReg <"lds_direct", 254>;
def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>; def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>;
def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>; def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>;
def XNACK_MASK : RegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>, def XNACK_MASK : SIRegisterWithSubRegs<"xnack_mask", [XNACK_MASK_LO, XNACK_MASK_HI]>,
DwarfRegAlias<XNACK_MASK_LO> { DwarfRegAlias<XNACK_MASK_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 104; let HWEncoding = 104;
} }
// Trap handler registers // Trap handler registers
def TBA_LO : SIReg<"tba_lo", 108>; def TBA_LO : SIReg<"tba_lo", 108>;
def TBA_HI : SIReg<"tba_hi", 109>; def TBA_HI : SIReg<"tba_hi", 109>;
def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>, def TBA : SIRegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>,
DwarfRegAlias<TBA_LO> { DwarfRegAlias<TBA_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 108; let HWEncoding = 108;
} }
def TMA_LO : SIReg<"tma_lo", 110>; def TMA_LO : SIReg<"tma_lo", 110>;
def TMA_HI : SIReg<"tma_hi", 111>; def TMA_HI : SIReg<"tma_hi", 111>;
def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>, def TMA : SIRegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>,
DwarfRegAlias<TMA_LO> { DwarfRegAlias<TMA_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 110; let HWEncoding = 110;
} }
foreach Index = 0-15 in { foreach Index = 0-15 in {
def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>; def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>;
def TTMP#Index#_gfx9_gfx10 : SIReg<"ttmp"#Index, !add(108, Index)>; def TTMP#Index#_gfx9_gfx10 : SIReg<"ttmp"#Index, !add(108, Index)>;
def TTMP#Index : SIReg<"", 0>; def TTMP#Index : SIReg<"ttmp"#Index, 0>;
} }
multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> { multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
def _ci : SIReg<n, ci_e>; def _ci : SIReg<n, ci_e>;
def _vi : SIReg<n, vi_e>; def _vi : SIReg<n, vi_e>;
def "" : SIReg<"", 0>; def "" : SIReg<"", 0>;
} }
class FlatReg <Register lo, Register hi, bits<16> encoding> : class FlatReg <Register lo, Register hi, bits<16> encoding> :
RegisterWithSubRegs<"flat_scratch", [lo, hi]>, SIRegisterWithSubRegs<"flat_scratch", [lo, hi]>,
DwarfRegAlias<lo> { DwarfRegAlias<lo> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = encoding; let HWEncoding = encoding;
} }
defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes. defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.
defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes. defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>; def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>; def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>; def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
// SGPR registers // SGPR registers
foreach Index = 0-105 in { foreach Index = 0-105 in {
def SGPR#Index : SIReg <"SGPR"#Index, Index>; def SGPR#Index : SIReg <"SGPR"#Index, Index, "S">;
} }
// VGPR registers // VGPR registers
foreach Index = 0-255 in { foreach Index = 0-255 in {
def VGPR#Index : SIReg <"VGPR"#Index, Index> { def VGPR#Index : SIReg <"VGPR"#Index, Index, "V"> {
let HWEncoding{8} = 1; let HWEncoding{8} = 1;
} }
} }
// AccVGPR registers // AccVGPR registers
foreach Index = 0-255 in { foreach Index = 0-255 in {
def AGPR#Index : SIReg <"AGPR"#Index, Index> { def AGPR#Index : SIReg <"AGPR"#Index, Index, "A"> {
let HWEncoding{8} = 1; let HWEncoding{8} = 1;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Groupings using register classes and tuples // Groupings using register classes and tuples
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> { def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
let CopyCost = -1; let CopyCost = -1;
let isAllocatable = 0; let isAllocatable = 0;
} }
def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> { def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
let CopyCost = 1; let CopyCost = 1;
let isAllocatable = 0; let isAllocatable = 0;
} }
// TODO: Do we need to set DwarfRegAlias on register tuples? // TODO: Do we need to set DwarfRegAlias on register tuples?
// SGPR 32-bit registers // SGPR 32-bit registers
def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add (sequence "SGPR%u", 0, 105))> { (add (sequence "SGPR%u", 0, 105)), Reg32> {
// Give all SGPR classes higher priority than VGPR classes, because // Give all SGPR classes higher priority than VGPR classes, because
// we want to spill SGPRs to VGPRs. // we want to spill SGPRs to VGPRs.
let AllocationPriority = 9; let AllocationPriority = 9;
} }
// SGPR 64-bit registers // SGPR 64-bit registers
def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret, def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret,
[(add (decimate SGPR_32, 2)), [(add (decimate SGPR_32, 2)),
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Linesdef TTMP_512Regs : RegisterTuples<getSubRegs<16>.ret,
(add (decimate (shl TTMP_32, 14), 4)), (add (decimate (shl TTMP_32, 14), 4)),
(add (decimate (shl TTMP_32, 15), 4))]>; (add (decimate (shl TTMP_32, 15), 4))]>;
class TmpRegTuplesBase<int index, int size, class TmpRegTuplesBase<int index, int size,
list<Register> subRegs, list<Register> subRegs,
list<SubRegIndex> indices = getSubRegs<size>.ret, list<SubRegIndex> indices = getSubRegs<size>.ret,
int index1 = !add(index, !add(size, -1)), int index1 = !add(index, !add(size, -1)),
string name = "ttmp["#index#":"#index1#"]"> : string name = "ttmp["#index#":"#index1#"]"> :
RegisterWithSubRegs<name, subRegs> { SIRegisterWithSubRegs<name, subRegs> {
let HWEncoding = subRegs[0].HWEncoding; let HWEncoding = subRegs[0].HWEncoding;
let SubRegIndices = indices; let SubRegIndices = indices;
} }
class TmpRegTuples<string tgt, class TmpRegTuples<string tgt,
int size, int size,
int index0, int index0,
int index1 = !add(index0, 1), int index1 = !add(index0, 1),
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines TmpRegTuplesBase<0, 16,
[TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10, [TTMP0_gfx9_gfx10, TTMP1_gfx9_gfx10, TTMP2_gfx9_gfx10, TTMP3_gfx9_gfx10,
TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10, TTMP4_gfx9_gfx10, TTMP5_gfx9_gfx10, TTMP6_gfx9_gfx10, TTMP7_gfx9_gfx10,
TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10, TTMP8_gfx9_gfx10, TTMP9_gfx9_gfx10, TTMP10_gfx9_gfx10, TTMP11_gfx9_gfx10,
TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>; TTMP12_gfx9_gfx10, TTMP13_gfx9_gfx10, TTMP14_gfx9_gfx10, TTMP15_gfx9_gfx10]>;
// VGPR 32-bit registers // VGPR 32-bit registers
// i16/f16 only on VI+ // i16/f16 only on VI+
def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add (sequence "VGPR%u", 0, 255))> { (add (sequence "VGPR%u", 0, 255)), Reg32> {
let AllocationPriority = 1; let AllocationPriority = 1;
let Size = 32; let Size = 32;
} }
// VGPR 64-bit registers // VGPR 64-bit registers
def VGPR_64 : RegisterTuples<getSubRegs<2>.ret, def VGPR_64 : RegisterTuples<getSubRegs<2>.ret,
[(add (trunc VGPR_32, 255)), [(add (trunc VGPR_32, 255)),
(add (shl VGPR_32, 1))]>; (add (shl VGPR_32, 1))]>;
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Linesdef VGPR_1024 : RegisterTuples<getSubRegs<32>.ret,
(add (shl VGPR_32, 27)), (add (shl VGPR_32, 27)),
(add (shl VGPR_32, 28)), (add (shl VGPR_32, 28)),
(add (shl VGPR_32, 29)), (add (shl VGPR_32, 29)),
(add (shl VGPR_32, 30)), (add (shl VGPR_32, 30)),
(add (shl VGPR_32, 31))]>; (add (shl VGPR_32, 31))]>;
// AccVGPR 32-bit registers // AccVGPR 32-bit registers
def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add (sequence "AGPR%u", 0, 255))> { (add (sequence "AGPR%u", 0, 255)), Reg32> {
let AllocationPriority = 1; let AllocationPriority = 1;
let Size = 32; let Size = 32;
} }
// AGPR 64-bit registers // AGPR 64-bit registers
def AGPR_64 : RegisterTuples<getSubRegs<2>.ret, def AGPR_64 : RegisterTuples<getSubRegs<2>.ret,
[(add (trunc AGPR_32, 255)), [(add (trunc AGPR_32, 255)),
(add (shl AGPR_32, 1))]>; (add (shl AGPR_32, 1))]>;
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Linesdef AGPR_1024 : RegisterTuples<getSubRegs<32>.ret,
(add (shl AGPR_32, 30)), (add (shl AGPR_32, 30)),
(add (shl AGPR_32, 31))]>; (add (shl AGPR_32, 31))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register classes used as source and destination // Register classes used as source and destination
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> { (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG), Reg32> {
let isAllocatable = 0; let isAllocatable = 0;
let CopyCost = -1; let CopyCost = -1;
} }
def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32,
(add PRIVATE_RSRC_REG)> { (add PRIVATE_RSRC_REG), Reg32> {
arsenmUnsubmitted
Not Done
ReplyInline Actions

This probably shouldn't have a set name, but should be Reg128

arsenm: This probably shouldn't have a set name, but should be Reg128
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

Thanks, Reg128 indeed.

rampitec: Thanks, Reg128 indeed.
let isAllocatable = 0; let isAllocatable = 0;
let CopyCost = -1; let CopyCost = -1;
} }
def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add LDS_DIRECT)> { (add LDS_DIRECT), Reg32> {
let isAllocatable = 0; let isAllocatable = 0;
let CopyCost = -1; let CopyCost = -1;
} }
// Subset of SReg_32 without M0 for SMRD instructions and alike. // Subset of SReg_32 without M0 for SMRD instructions and alike.
// See comments in SIInstructions.td for more info. // See comments in SIInstructions.td for more info.
def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
(add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI, (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT, SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID, SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID,
SRC_VCCZ, SRC_EXECZ, SRC_SCC)> { SRC_VCCZ, SRC_EXECZ, SRC_SCC), Reg32> {
let AllocationPriority = 10; let AllocationPriority = 10;
} }
def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
(add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> { (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS), Reg32> {
let AllocationPriority = 10; let AllocationPriority = 10;
} }
def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
(add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> { (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI), Reg32> {
let AllocationPriority = 10; let AllocationPriority = 10;
} }
// Register class for all scalar registers (SGPRs + Special Registers) // Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
(add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> { (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI), Reg32> {
let AllocationPriority = 10; let AllocationPriority = 10;
} }
def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
(add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS)> { (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS),
Reg32> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, (add SGPR_64Regs)> { def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32,
(add SGPR_64Regs), Reg64> {
let CopyCost = 1; let CopyCost = 1;
let AllocationPriority = 11; let AllocationPriority = 11;
} }
// CCR (call clobbered registers) SGPR 64-bit registers // CCR (call clobbered registers) SGPR 64-bit registers
def CCR_SGPR_64 : RegisterClass<"AMDGPU", SGPR_64.RegTypes, 32, (add (trunc SGPR_64, 16))> { def CCR_SGPR_64 : RegisterClass<"AMDGPU", SGPR_64.RegTypes, 32,
(add (trunc SGPR_64, 16)), Reg64> {
let CopyCost = SGPR_64.CopyCost; let CopyCost = SGPR_64.CopyCost;
let AllocationPriority = SGPR_64.AllocationPriority; let AllocationPriority = SGPR_64.AllocationPriority;
} }
def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32, (add TTMP_64Regs)> { def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, v4i16, v4f16], 32,
(add TTMP_64Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
(add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> { (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA), Reg64> {
let CopyCost = 1; let CopyCost = 1;
let AllocationPriority = 13; let AllocationPriority = 13;
} }
def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32, def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, i1, v4i16, v4f16], 32,
(add SReg_64_XEXEC, EXEC)> { (add SReg_64_XEXEC, EXEC), Reg64> {
let CopyCost = 1; let CopyCost = 1;
let AllocationPriority = 13; let AllocationPriority = 13;
} }
def SReg_1_XEXEC : RegisterClass<"AMDGPU", [i1], 32, def SReg_1_XEXEC : RegisterClass<"AMDGPU", [i1], 32,
(add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> { (add SReg_64_XEXEC, SReg_32_XM0_XEXEC)> {
let CopyCost = 1; let CopyCost = 1;
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_1 : RegisterClass<"AMDGPU", [i1], 32, def SReg_1 : RegisterClass<"AMDGPU", [i1], 32,
(add SReg_1_XEXEC, EXEC, EXEC_LO)> { (add SReg_1_XEXEC, EXEC, EXEC_LO)> {
let CopyCost = 1; let CopyCost = 1;
let isAllocatable = 0; let isAllocatable = 0;
} }
// Requires 2 s_mov_b64 to copy // Requires 2 s_mov_b64 to copy
let CopyCost = 2 in { let CopyCost = 2 in {
// There are no 3-component scalar instructions, but this is needed // There are no 3-component scalar instructions, but this is needed
// for symmetry with VGPRs. // for symmetry with VGPRs.
def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, def SGPR_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
(add SGPR_96Regs)> { (add SGPR_96Regs), Reg96> {
let AllocationPriority = 14; let AllocationPriority = 14;
} }
def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, def SReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32,
(add SGPR_96)> { (add SGPR_96), Reg96> {
let AllocationPriority = 14; let AllocationPriority = 14;
} }
def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, (add SGPR_128Regs)> { def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32,
(add SGPR_128Regs), Reg128> {
let AllocationPriority = 15; let AllocationPriority = 15;
} }
def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32, (add TTMP_128Regs)> { def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32,
(add TTMP_128Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
(add SGPR_128, TTMP_128)> { (add SGPR_128, TTMP_128), Reg128> {
let AllocationPriority = 15; let AllocationPriority = 15;
} }
} // End CopyCost = 2 } // End CopyCost = 2
// There are no 5-component scalar instructions, but this is needed // There are no 5-component scalar instructions, but this is needed
// for symmetry with VGPRs. // for symmetry with VGPRs.
def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, def SGPR_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
(add SGPR_160Regs)> { (add SGPR_160Regs), Reg160> {
let AllocationPriority = 16; let AllocationPriority = 16;
} }
def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
(add SGPR_160)> { (add SGPR_160), Reg160> {
let AllocationPriority = 16; let AllocationPriority = 16;
} }
def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> { def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs),
Reg256> {
let AllocationPriority = 17; let AllocationPriority = 17;
} }
def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> { def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
(add SGPR_256, TTMP_256)> { (add SGPR_256, TTMP_256), Reg256> {
// Requires 4 s_mov_b64 to copy // Requires 4 s_mov_b64 to copy
let CopyCost = 4; let CopyCost = 4;
let AllocationPriority = 17; let AllocationPriority = 17;
} }
def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add SGPR_512Regs)> { def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add SGPR_512Regs), Reg512> {
let AllocationPriority = 18; let AllocationPriority = 18;
} }
def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add TTMP_512Regs)> { def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add TTMP_512Regs)> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add SGPR_512, TTMP_512)> { (add SGPR_512, TTMP_512), Reg512> {
// Requires 8 s_mov_b64 to copy // Requires 8 s_mov_b64 to copy
let CopyCost = 8; let CopyCost = 8;
let AllocationPriority = 18; let AllocationPriority = 18;
} }
def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add VGPR_32, LDS_DIRECT_CLASS)> { (add VGPR_32, LDS_DIRECT_CLASS), Reg32> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, (add SGPR_1024Regs)> { def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
(add SGPR_1024Regs), Reg1024> {
let AllocationPriority = 19; let AllocationPriority = 19;
} }
def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
(add SGPR_1024)> { (add SGPR_1024), Reg1024> {
let CopyCost = 16; let CopyCost = 16;
let AllocationPriority = 19; let AllocationPriority = 19;
} }
// Register class for all vector registers (VGPRs + Interploation Registers) // Register class for all vector registers (VGPRs + Interploation Registers)
def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, (add VGPR_64)> { def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32,
(add VGPR_64), Reg64> {
let Size = 64; let Size = 64;
// Requires 2 v_mov_b32 to copy // Requires 2 v_mov_b32 to copy
let CopyCost = 2; let CopyCost = 2;
let AllocationPriority = 2; let AllocationPriority = 2;
} }
def VReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, (add VGPR_96)> { def VReg_96 : RegisterClass<"AMDGPU", [v3i32, v3f32], 32, (add VGPR_96), Reg96> {
let Size = 96; let Size = 96;
// Requires 3 v_mov_b32 to copy // Requires 3 v_mov_b32 to copy
let CopyCost = 3; let CopyCost = 3;
let AllocationPriority = 3; let AllocationPriority = 3;
} }
def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add VGPR_128)> { def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
(add VGPR_128), Reg128> {
let Size = 128; let Size = 128;
// Requires 4 v_mov_b32 to copy // Requires 4 v_mov_b32 to copy
let CopyCost = 4; let CopyCost = 4;
let AllocationPriority = 4; let AllocationPriority = 4;
} }
def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32, (add VGPR_160)> { def VReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
(add VGPR_160), Reg160> {
let Size = 160; let Size = 160;
// Requires 5 v_mov_b32 to copy // Requires 5 v_mov_b32 to copy
let CopyCost = 5; let CopyCost = 5;
let AllocationPriority = 5; let AllocationPriority = 5;
} }
def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add VGPR_256)> { def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
(add VGPR_256), Reg256> {
let Size = 256; let Size = 256;
let CopyCost = 8; let CopyCost = 8;
let AllocationPriority = 6; let AllocationPriority = 6;
} }
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> { def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add VGPR_512), Reg512> {
let Size = 512; let Size = 512;
let CopyCost = 16; let CopyCost = 16;
let AllocationPriority = 7; let AllocationPriority = 7;
} }
def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, (add VGPR_1024)> { def VReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
(add VGPR_1024), Reg1024> {
let Size = 1024; let Size = 1024;
let CopyCost = 32; let CopyCost = 32;
let AllocationPriority = 8; let AllocationPriority = 8;
} }
def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, (add AGPR_64)> { def AReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32,
(add AGPR_64), Reg64> {
let Size = 64; let Size = 64;
let CopyCost = 5; let CopyCost = 5;
let AllocationPriority = 2; let AllocationPriority = 2;
} }
def AReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add AGPR_128)> { def AReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
(add AGPR_128), Reg128> {
let Size = 128; let Size = 128;
// Requires 4 v_accvgpr_write and 4 v_accvgpr_read to copy + burn 1 vgpr // Requires 4 v_accvgpr_write and 4 v_accvgpr_read to copy + burn 1 vgpr
let CopyCost = 9; let CopyCost = 9;
let AllocationPriority = 4; let AllocationPriority = 4;
} }
def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add AGPR_512)> { def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
(add AGPR_512), Reg512> {
let Size = 512; let Size = 512;
let CopyCost = 33; let CopyCost = 33;
let AllocationPriority = 7; let AllocationPriority = 7;
} }
// TODO: add v32f32 value type def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
def AReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32, (add AGPR_1024)> { (add AGPR_1024), Reg1024> {
let Size = 1024; let Size = 1024;
let CopyCost = 65; let CopyCost = 65;
let AllocationPriority = 8; let AllocationPriority = 8;
} }
def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> { def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32), Reg32> {
let Size = 32; let Size = 32;
} }
def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> { (add VGPR_32, SReg_32, LDS_DIRECT_CLASS), Reg32> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64),
Reg64> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add AGPR_32, VGPR_32)> { (add AGPR_32, VGPR_32), Reg32> {
let isAllocatable = 0; let isAllocatable = 0;
} }
def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32, (add AReg_64, VReg_64)> { def AV_64 : RegisterClass<"AMDGPU", [i64, f64, v4f16], 32,
(add AReg_64, VReg_64), Reg64> {
let isAllocatable = 0; let isAllocatable = 0;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register operands // Register operands
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class RegImmMatcher<string name> : AsmOperandClass { class RegImmMatcher<string name> : AsmOperandClass {
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