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AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC
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Authored by arsenm on Jul 15 2019, 5:53 AM.

Details

Reviewers
tstellar
nhaehnle
Summary

This was emitting a copy from a 32-bit register to a 64-bit.

Diff Detail

Event Timeline

arsenm created this revision.Jul 15 2019, 5:53 AM
tstellar accepted this revision.Jul 15 2019, 7:39 AM

LGTM.

This revision is now accepted and ready to land.Jul 15 2019, 7:39 AM
arsenm closed this revision.Jul 15 2019, 12:43 PM

r366117