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AMDGPU/GlobalISel: Allow scalar s1 and/or/xor
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Authored by arsenm on Jul 10 2019, 10:05 AM.

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Reviewers
tstellar
nhaehnle
Summary

If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.

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Event Timeline

arsenm created this revision.Jul 10 2019, 10:05 AM
This revision is now accepted and ready to land.Jul 15 2019, 10:32 AM
arsenm closed this revision.Jul 15 2019, 1:20 PM

r366125