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Differential D64336

AMDGPU: Use standalone MUBUF load patterns
ClosedPublic

Authored by arsenm on Jul 8 2019, 7:24 AM.

Details

Reviewers
rampitec
nhaehnle
Summary

We already do this for the flat and DS instructions, although it is
certainly uglier and more verbose.




This will allow using separate pattern definitions for extload and

zextload. Currently we get away with using a single PatFrag with

custom predicate code to check if the extension type is a zextload or

anyextload. The generic mechanism the global isel emitter understands

treats these as mutually exclusive. I was considering making the

pattern emitter accept zextload or sextload extensions for anyextload

patterns, but in global isel, the different extending loads have

distinct opcodes, and there is currently no mechanism for an opcode

matcher to try multiple (and there probably is very little need for

one beyond this case).
Diff Detail
Event Timeline
arsenm created this revision.Jul 8 2019, 7:24 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others.  ·  View Herald TranscriptJul 8 2019, 7:24 AM
rampitec accepted this revision.Jul 8 2019, 10:52 AM
LGTM
This revision is now accepted and ready to land.Jul 8 2019, 10:52 AM
arsenm closed this revision.Jul 15 2019, 2:41 PM
r366132
Revision Contents
PathSize
lib/
Target/
AMDGPU/
57 lines
Diff 208403
lib/Target/AMDGPU/BUFInstructions.td
Show First 20 Lines • Show All 464 Lines • ▼ Show 20 Linesclass MUBUF_Load_Pseudo <string opName,

  let mayStore = 0;
  let mayStore = 0;

  let maybeAtomic = 1;
  let maybeAtomic = 1;

  let Uses = !if(isLds, [EXEC, M0], [EXEC]);
  let Uses = !if(isLds, [EXEC, M0], [EXEC]);

  let has_tfe = !if(isLds, 0, 1);
  let has_tfe = !if(isLds, 0, 1);

  let lds = isLds;
  let lds = isLds;

  let dwords = getMUBUFDwords<vdataClass>.ret;
  let dwords = getMUBUFDwords<vdataClass>.ret;

}
}




class MUBUF_Offset_Load_Pat <Instruction inst, ValueType load_vt = i32, SDPatternOperator ld = null_frag> : Pat <

  (load_vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))),

  (load_vt (inst v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))

>;



class MUBUF_Addr64_Load_Pat <Instruction inst,

                            ValueType load_vt = i32,

                            SDPatternOperator ld = null_frag> : Pat <

  (load_vt (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))),

  (load_vt (inst i64:$vaddr, v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc))

>;



multiclass MUBUF_Pseudo_Load_Pats<string BaseInst, ValueType load_vt = i32, SDPatternOperator ld = null_frag> {

  def : MUBUF_Offset_Load_Pat<!cast<Instruction>(BaseInst#"_OFFSET"), load_vt, ld>;

  def : MUBUF_Addr64_Load_Pat<!cast<Instruction>(BaseInst#"_ADDR64"), load_vt, ld>;

}





// FIXME: tfe can't be an operand because it requires a separate
// FIXME: tfe can't be an operand because it requires a separate

// opcode because it needs an N+1 register class dest register.
// opcode because it needs an N+1 register class dest register.

multiclass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
multiclass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,

                              ValueType load_vt = i32,
                              ValueType load_vt = i32,

                              SDPatternOperator ld = null_frag,
                              SDPatternOperator ld = null_frag,

                              bit TiedDest = 0,
                              bit TiedDest = 0,

                              bit isLds = 0> {
                              bit isLds = 0> {




  def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
  def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>,

    TiedDest, isLds,

    !if(isLds,

        [],

        [(set load_vt:$vdata,

         (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)))])>,

    MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;
    MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;




  def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
  def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, TiedDest, isLds>,

    TiedDest, isLds,

    !if(isLds,

        [],

        [(set load_vt:$vdata,

         (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc)))])>,

    MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;
    MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;




  def _OFFEN  : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
  def _OFFEN  : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;

  def _IDXEN  : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
  def _IDXEN  : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;

  def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;
  def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, TiedDest, isLds>;




  let DisableWQM = 1 in {
  let DisableWQM = 1 in {

    def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>;
    def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, TiedDest, isLds>;

▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines  defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Pseudo_Stores <

    "buffer_store_format_d16_xyz", VReg_64
    "buffer_store_format_d16_xyz", VReg_64

  >;
  >;

  defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Pseudo_Stores <
  defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Pseudo_Stores <

    "buffer_store_format_d16_xyzw", VReg_64
    "buffer_store_format_d16_xyzw", VReg_64

  >;
  >;

} // End HasPackedD16VMem.
} // End HasPackedD16VMem.




defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads_Lds <
defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads_Lds <

  "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global
  "buffer_load_ubyte", VGPR_32, i32

>;
>;

defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads_Lds <
defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads_Lds <

  "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global
  "buffer_load_sbyte", VGPR_32, i32

>;
>;

defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads_Lds <
defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads_Lds <

  "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global
  "buffer_load_ushort", VGPR_32, i32

>;
>;

defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads_Lds <
defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads_Lds <

  "buffer_load_sshort", VGPR_32, i32, sextloadi16_global
  "buffer_load_sshort", VGPR_32, i32

>;
>;

defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads_Lds <
defm BUFFER_LOAD_DWORD : MUBUF_Pseudo_Loads_Lds <

  "buffer_load_dword", VGPR_32, i32, load_global
  "buffer_load_dword", VGPR_32, i32

>;
>;

defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads <
defm BUFFER_LOAD_DWORDX2 : MUBUF_Pseudo_Loads <

  "buffer_load_dwordx2", VReg_64, v2i32, load_global
  "buffer_load_dwordx2", VReg_64, v2i32

>;
>;

defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads <
defm BUFFER_LOAD_DWORDX3 : MUBUF_Pseudo_Loads <

  "buffer_load_dwordx3", VReg_96, v3i32, load_global
  "buffer_load_dwordx3", VReg_96, v3i32

>;
>;

defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <
defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <

  "buffer_load_dwordx4", VReg_128, v4i32, load_global
  "buffer_load_dwordx4", VReg_128, v4i32

>;
>;




defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, az_extloadi8_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SBYTE", i32, sextloadi8_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, az_extloadi16_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SSHORT", i32, sextloadi16_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORD", i32, load_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX2", v2i32, load_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX3", v3i32, load_global>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX4", v4i32, load_global>;



// This is not described in AMD documentation,
// This is not described in AMD documentation,

// but 'lds' versions of these opcodes are available
// but 'lds' versions of these opcodes are available

// in at least GFX8+ chips. See Bug 37653.
// in at least GFX8+ chips. See Bug 37653.

let SubtargetPredicate = isGFX8GFX9 in {
let SubtargetPredicate = isGFX8GFX9 in {

defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads <
defm BUFFER_LOAD_DWORDX2_LDS : MUBUF_Pseudo_Loads <

  "buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1
  "buffer_load_dwordx2", VReg_64, v2i32, null_frag, 0, 1

>;
>;

defm BUFFER_LOAD_DWORDX3_LDS : MUBUF_Pseudo_Loads <
defm BUFFER_LOAD_DWORDX3_LDS : MUBUF_Pseudo_Loads <

▲ Show 20 Lines • Show All 1,432 Lines • Show Last 20 Lines