[LLD] [COFF] Share the tail in delayimport symbol thunks

[mstorsjo]

Summary

E.g. for x86_64, previously each symbol's thunk was 87 bytes. Now there's a 12 byte thunk per symbol, plus a shared 83 byte tail function.

This is similar to what both MS link.exe and GNU tools do for delay imports.

[ruiu]

Nice!

COFF/DLL.cpp

195

Intel recommends jump targets being aligned to 16 bytes. Does this jump target aligned to the boundaries? Last time I tried, I observed a non-negligible difference between unaligned and aligned jump targets.

[mstorsjo]

COFF/DLL.cpp

195

I guess that can be done by just marking the tail chunk as 16 byte aligned? Aligning the thunks themselves feels wasteful though.

[rnk]

COFF/DLL.cpp

195

As far as performance is concerned, each delay load thunk runs once, so I would leave them unaligned to optimize for size.

It might end up mattering for CFI, actually. There's some assumption there that indirect branch targets (which these thunks are) are aligned. I forget the details, though.

I'm also wondering if we shouldn't mark the delay load thunks as hotpatchable so they are affected by /functionpadmin:. It seems separable though.

[ruiu]

COFF/DLL.cpp

195

Ah, good point. If they are executed only once, there's no point to align them to trade speed with binary size.

[mstorsjo]

Any other concerns with the patch, or is it ok as is?

COFF/DLL.cpp

195

Re CFI, we don't generate any for the thunk right now either. And making them respect /functionpadmin: also seems orthogonal to this patch.

[rnk]

lgtm, and I think Rui approves as well.

[ruiu]

Yes, as long as Reid is fine, I'm fine with this patch.

COFF/DLL.h

public:
   std::vector<Chunk *> getChunks();
   std::vector<Chunk *> getDataChunks();
   ArrayRef<Chunk *> getCodeChunks() { return Thunks; }
 
   uint64_t getDirRVA() { return Dirs[0]->getRVA(); }
   uint64_t getDirSize();
 
 private:
-  Chunk *newThunkChunk(DefinedImportData *S, Chunk *Dir);
+  Chunk *newThunkChunk(DefinedImportData *S, Chunk *TailMerge);
+  Chunk *newTailMergeChunk(Chunk *Dir);
 
   Defined *Helper;
   std::vector<DefinedImportData *> Imports;
   std::vector<Chunk *> Dirs;
   std::vector<Chunk *> ModuleHandles;
   std::vector<Chunk *> Addresses;
   std::vector<Chunk *> Names;
   std::vector<Chunk *> HintNames;

COFF/DLL.cpp

public:
   Chunk *NameTab;
 };
 
 // Initial contents for delay-loaded functions.
 // This code calls __delayLoadHelper2 function to resolve a symbol
 // which then overwrites its jump table slot with the result
 // for subsequent function calls.
 static const uint8_t ThunkX64[] = {
+    0x48, 0x8D, 0x05, 0, 0, 0, 0,       // lea     rax, [__imp_<FUNCNAME>]
+    0xE9, 0, 0, 0, 0,                   // jmp     __tailMerge_<lib>
+};
+
+static const uint8_t TailMergeX64[] = {
     0x51,                               // push    rcx
     0x52,                               // push    rdx
     0x41, 0x50,                         // push    r8
     0x41, 0x51,                         // push    r9
     0x48, 0x83, 0xEC, 0x48,             // sub     rsp, 48h
     0x66, 0x0F, 0x7F, 0x04, 0x24,       // movdqa  xmmword ptr [rsp], xmm0
     0x66, 0x0F, 0x7F, 0x4C, 0x24, 0x10, // movdqa  xmmword ptr [rsp+10h], xmm1
     0x66, 0x0F, 0x7F, 0x54, 0x24, 0x20, // movdqa  xmmword ptr [rsp+20h], xmm2
     0x66, 0x0F, 0x7F, 0x5C, 0x24, 0x30, // movdqa  xmmword ptr [rsp+30h], xmm3
-    0x48, 0x8D, 0x15, 0, 0, 0, 0,       // lea     rdx, [__imp_<FUNCNAME>]
+    0x48, 0x8B, 0xD0,                   // mov     rdx, rax
     0x48, 0x8D, 0x0D, 0, 0, 0, 0,       // lea     rcx, [___DELAY_IMPORT_...]
     0xE8, 0, 0, 0, 0,                   // call    __delayLoadHelper2
     0x66, 0x0F, 0x6F, 0x04, 0x24,       // movdqa  xmm0, xmmword ptr [rsp]
     0x66, 0x0F, 0x6F, 0x4C, 0x24, 0x10, // movdqa  xmm1, xmmword ptr [rsp+10h]
     0x66, 0x0F, 0x6F, 0x54, 0x24, 0x20, // movdqa  xmm2, xmmword ptr [rsp+20h]
     0x66, 0x0F, 0x6F, 0x5C, 0x24, 0x30, // movdqa  xmm3, xmmword ptr [rsp+30h]
     0x48, 0x83, 0xC4, 0x48,             // add     rsp, 48h
     0x41, 0x59,                         // pop     r9
     0x41, 0x58,                         // pop     r8
     0x5A,                               // pop     rdx
     0x59,                               // pop     rcx
     0xFF, 0xE0,                         // jmp     rax
 };
 
 static const uint8_t ThunkX86[] = {
+    0xB8, 0, 0, 0, 0,  // mov   eax, offset ___imp__<FUNCNAME>
+    0xE9, 0, 0, 0, 0,  // jmp   __tailMerge_<lib>
+};
+
+static const uint8_t TailMergeX86[] = {
     0x51,              // push  ecx
     0x52,              // push  edx
-    0x68, 0, 0, 0, 0,  // push  offset ___imp__<FUNCNAME>
+    0x50,              // push  eax
     0x68, 0, 0, 0, 0,  // push  offset ___DELAY_IMPORT_DESCRIPTOR_<DLLNAME>_dll
     0xE8, 0, 0, 0, 0,  // call  ___delayLoadHelper2@8
     0x5A,              // pop   edx
     0x59,              // pop   ecx
     0xFF, 0xE0,        // jmp   eax
 };
 
 static const uint8_t ThunkARM[] = {
     0x40, 0xf2, 0x00, 0x0c, // mov.w   ip, #0 __imp_<FUNCNAME>
     0xc0, 0xf2, 0x00, 0x0c, // mov.t   ip, #0 __imp_<FUNCNAME>
+    0x00, 0xf0, 0x00, 0xb8, // b.w     __tailMerge_<lib>
+};
+
+static const uint8_t TailMergeARM[] = {
     0x2d, 0xe9, 0x0f, 0x48, // push.w  {r0, r1, r2, r3, r11, lr}
     0x0d, 0xf2, 0x10, 0x0b, // addw    r11, sp, #16
     0x2d, 0xed, 0x10, 0x0b, // vpush   {d0, d1, d2, d3, d4, d5, d6, d7}
     0x61, 0x46,             // mov     r1, ip
     0x40, 0xf2, 0x00, 0x00, // mov.w   r0, #0 DELAY_IMPORT_DESCRIPTOR
     0xc0, 0xf2, 0x00, 0x00, // mov.t   r0, #0 DELAY_IMPORT_DESCRIPTOR
     0x00, 0xf0, 0x00, 0xd0, // bl      #0 __delayLoadHelper2
     0x84, 0x46,             // mov     ip, r0
     0xbd, 0xec, 0x10, 0x0b, // vpop    {d0, d1, d2, d3, d4, d5, d6, d7}
     0xbd, 0xe8, 0x0f, 0x48, // pop.w   {r0, r1, r2, r3, r11, lr}
     0x60, 0x47,             // bx      ip
 };
 
 static const uint8_t ThunkARM64[] = {
     0x11, 0x00, 0x00, 0x90, // adrp    x17, #0      __imp_<FUNCNAME>
     0x31, 0x02, 0x00, 0x91, // add     x17, x17, #0 :lo12:__imp_<FUNCNAME>
+    0x00, 0x00, 0x00, 0x14, // b       __tailMerge_<lib>
+};
+
+static const uint8_t TailMergeARM64[] = {
     0xfd, 0x7b, 0xb3, 0xa9, // stp     x29, x30, [sp, #-208]!
     0xfd, 0x03, 0x00, 0x91, // mov     x29, sp
     0xe0, 0x07, 0x01, 0xa9, // stp     x0, x1, [sp, #16]
     0xe2, 0x0f, 0x02, 0xa9, // stp     x2, x3, [sp, #32]
     0xe4, 0x17, 0x03, 0xa9, // stp     x4, x5, [sp, #48]
     0xe6, 0x1f, 0x04, 0xa9, // stp     x6, x7, [sp, #64]
     0xe0, 0x87, 0x02, 0xad, // stp     q0, q1, [sp, #80]
     0xe2, 0x8f, 0x03, 0xad, // stp     q2, q3, [sp, #112]
static const uint8_t TailMergeARM64[] = {
     0xe0, 0x07, 0x41, 0xa9, // ldp     x0, x1, [sp, #16]
     0xfd, 0x7b, 0xcd, 0xa8, // ldp     x29, x30, [sp], #208
     0x00, 0x02, 0x1f, 0xd6, // br      x16
 };
 
 // A chunk for the delay import thunk.
 class ThunkChunkX64 : public NonSectionChunk {
 public:
-  ThunkChunkX64(Defined *I, Chunk *D, Defined *H)
-      : Imp(I), Desc(D), Helper(H) {}
+  ThunkChunkX64(Defined *I, Chunk *TM) : Imp(I), TailMerge(TM) {}
 
   size_t getSize() const override { return sizeof(ThunkX64); }
 
   void writeTo(uint8_t *Buf) const override {
     memcpy(Buf, ThunkX64, sizeof(ThunkX64));
-    write32le(Buf + 36, Imp->getRVA() - RVA - 40);
-    write32le(Buf + 43, Desc->getRVA() - RVA - 47);
-    write32le(Buf + 48, Helper->getRVA() - RVA - 52);
+    write32le(Buf + 3, Imp->getRVA() - RVA - 7);
+    write32le(Buf + 8, TailMerge->getRVA() - RVA - 12);
   }
 
   Defined *Imp = nullptr;
+  Chunk *TailMerge = nullptr;
+};
+
+class TailMergeChunkX64 : public NonSectionChunk {
+public:
+  TailMergeChunkX64(Chunk *D, Defined *H) : Desc(D), Helper(H) {}
+
+  size_t getSize() const override { return sizeof(TailMergeX64); }
+
+  void writeTo(uint8_t *Buf) const override {
+    memcpy(Buf, TailMergeX64, sizeof(TailMergeX64));
+    write32le(Buf + 39, Desc->getRVA() - RVA - 43);
+    write32le(Buf + 44, Helper->getRVA() - RVA - 48);
+  }
+
   Chunk *Desc = nullptr;
   Defined *Helper = nullptr;
 };
 
 class ThunkChunkX86 : public NonSectionChunk {
 public:
-  ThunkChunkX86(Defined *I, Chunk *D, Defined *H)
-      : Imp(I), Desc(D), Helper(H) {}
+  ThunkChunkX86(Defined *I, Chunk *TM) : Imp(I), TailMerge(TM) {}
 
   size_t getSize() const override { return sizeof(ThunkX86); }
 
   void writeTo(uint8_t *Buf) const override {
     memcpy(Buf, ThunkX86, sizeof(ThunkX86));
-    write32le(Buf + 3, Imp->getRVA() + Config->ImageBase);
-    write32le(Buf + 8, Desc->getRVA() + Config->ImageBase);
-    write32le(Buf + 13, Helper->getRVA() - RVA - 17);
+    write32le(Buf + 1, Imp->getRVA() + Config->ImageBase);
+    write32le(Buf + 6, TailMerge->getRVA() - RVA - 10);
   }
 
   void getBaserels(std::vector<Baserel> *Res) override {
-    Res->emplace_back(RVA + 3);
-    Res->emplace_back(RVA + 8);
+    Res->emplace_back(RVA + 1);
   }
 
   Defined *Imp = nullptr;
+  Chunk *TailMerge = nullptr;
+};
+
+class TailMergeChunkX86 : public NonSectionChunk {
+public:
+  TailMergeChunkX86(Chunk *D, Defined *H) : Desc(D), Helper(H) {}
+
+  size_t getSize() const override { return sizeof(TailMergeX86); }
+
+  void writeTo(uint8_t *Buf) const override {
+    memcpy(Buf, TailMergeX86, sizeof(TailMergeX86));
+    write32le(Buf + 4, Desc->getRVA() + Config->ImageBase);
+    write32le(Buf + 9, Helper->getRVA() - RVA - 13);
+  }
+
+  void getBaserels(std::vector<Baserel> *Res) override {
+    Res->emplace_back(RVA + 4);
+  }
+
   Chunk *Desc = nullptr;
   Defined *Helper = nullptr;
 };
 
 class ThunkChunkARM : public NonSectionChunk {
 public:
-  ThunkChunkARM(Defined *I, Chunk *D, Defined *H)
-      : Imp(I), Desc(D), Helper(H) {}
+  ThunkChunkARM(Defined *I, Chunk *TM) : Imp(I), TailMerge(TM) {}
 
   size_t getSize() const override { return sizeof(ThunkARM); }
 
   void writeTo(uint8_t *Buf) const override {
     memcpy(Buf, ThunkARM, sizeof(ThunkARM));
     applyMOV32T(Buf + 0, Imp->getRVA() + Config->ImageBase);
-    applyMOV32T(Buf + 22, Desc->getRVA() + Config->ImageBase);
-    applyBranch24T(Buf + 30, Helper->getRVA() - RVA - 34);
+    applyBranch24T(Buf + 8, TailMerge->getRVA() - RVA - 12);
   }
 
   void getBaserels(std::vector<Baserel> *Res) override {
     Res->emplace_back(RVA + 0, IMAGE_REL_BASED_ARM_MOV32T);
-    Res->emplace_back(RVA + 22, IMAGE_REL_BASED_ARM_MOV32T);
   }
 
   Defined *Imp = nullptr;
+  Chunk *TailMerge = nullptr;
+};
+
+class TailMergeChunkARM : public NonSectionChunk {
+public:
+  TailMergeChunkARM(Chunk *D, Defined *H) : Desc(D), Helper(H) {}
+
+  size_t getSize() const override { return sizeof(TailMergeARM); }
+
+  void writeTo(uint8_t *Buf) const override {
+    memcpy(Buf, TailMergeARM, sizeof(TailMergeARM));
+    applyMOV32T(Buf + 14, Desc->getRVA() + Config->ImageBase);
+    applyBranch24T(Buf + 22, Helper->getRVA() - RVA - 26);
+  }
+
+  void getBaserels(std::vector<Baserel> *Res) override {
+    Res->emplace_back(RVA + 14, IMAGE_REL_BASED_ARM_MOV32T);
+  }
+
   Chunk *Desc = nullptr;
   Defined *Helper = nullptr;
 };
 
 class ThunkChunkARM64 : public NonSectionChunk {
 public:
-  ThunkChunkARM64(Defined *I, Chunk *D, Defined *H)
-      : Imp(I), Desc(D), Helper(H) {}
+  ThunkChunkARM64(Defined *I, Chunk *TM) : Imp(I), TailMerge(TM) {}
 
   size_t getSize() const override { return sizeof(ThunkARM64); }
 
   void writeTo(uint8_t *Buf) const override {
     memcpy(Buf, ThunkARM64, sizeof(ThunkARM64));
     applyArm64Addr(Buf + 0, Imp->getRVA(), RVA + 0, 12);
     applyArm64Imm(Buf + 4, Imp->getRVA() & 0xfff, 0);
-    applyArm64Addr(Buf + 52, Desc->getRVA(), RVA + 52, 12);
-    applyArm64Imm(Buf + 56, Desc->getRVA() & 0xfff, 0);
-    applyArm64Branch26(Buf + 60, Helper->getRVA() - RVA - 60);
+    applyArm64Branch26(Buf + 8, TailMerge->getRVA() - RVA - 8);
   }
 
   Defined *Imp = nullptr;
+  Chunk *TailMerge = nullptr;
+};
+
+class TailMergeChunkARM64 : public NonSectionChunk {
+public:
+  TailMergeChunkARM64(Chunk *D, Defined *H) : Desc(D), Helper(H) {}
+
+  size_t getSize() const override { return sizeof(TailMergeARM64); }
+
+  void writeTo(uint8_t *Buf) const override {
+    memcpy(Buf, TailMergeARM64, sizeof(TailMergeARM64));
+    applyArm64Addr(Buf + 44, Desc->getRVA(), RVA + 44, 12);
+    applyArm64Imm(Buf + 48, Desc->getRVA() & 0xfff, 0);
+    applyArm64Branch26(Buf + 52, Helper->getRVA() - RVA - 52);
+  }
+
   Chunk *Desc = nullptr;
   Defined *Helper = nullptr;
 };
 
 // A chunk for the import descriptor table.
 class DelayAddressChunk : public NonSectionChunk {
 public:
   explicit DelayAddressChunk(Chunk *C) : Thunk(C) {
void DelayLoadContents::create(Defined *H) {
 
   // Create .didat contents for each DLL.
   for (std::vector<DefinedImportData *> &Syms : V) {
     // Create the delay import table header.
     DLLNames.push_back(make<StringChunk>(Syms[0]->getDLLName()));
     auto *Dir = make<DelayDirectoryChunk>(DLLNames.back());
 
     size_t Base = Addresses.size();
+    Chunk *TM = newTailMergeChunk(Dir);
     for (DefinedImportData *S : Syms) {
-      Chunk *T = newThunkChunk(S, Dir);
+      Chunk *T = newThunkChunk(S, TM);
       auto *A = make<DelayAddressChunk>(T);
       Addresses.push_back(A);
       Thunks.push_back(T);
       StringRef ExtName = S->getExternalName();
       if (ExtName.empty()) {
         Names.push_back(make<OrdinalOnlyChunk>(S->getOrdinal()));
       } else {
         auto *C = make<HintNameChunk>(ExtName, 0);
         Names.push_back(make<LookupChunk>(C));
         HintNames.push_back(C);
       }
     }
+    Thunks.push_back(TM);
     // Terminate with null values.
     Addresses.push_back(make<NullChunk>(8));
     Names.push_back(make<NullChunk>(8));
 
     for (int I = 0, E = Syms.size(); I < E; ++I)
       Syms[I]->setLocation(Addresses[Base + I]);
     auto *MH = make<NullChunk>(8);
     MH->setAlignment(8);
     ModuleHandles.push_back(MH);
 
     // Fill the delay import table header fields.
     Dir->ModuleHandle = MH;
     Dir->AddressTab = Addresses[Base];
     Dir->NameTab = Names[Base];
     Dirs.push_back(Dir);
   }
   // Add null terminator.
   Dirs.push_back(make<NullChunk>(sizeof(delay_import_directory_table_entry)));
 }
 
-Chunk *DelayLoadContents::newThunkChunk(DefinedImportData *S, Chunk *Dir) {
+Chunk *DelayLoadContents::newTailMergeChunk(Chunk *Dir) {
+  switch (Config->Machine) {
+  case AMD64:
+    return make<TailMergeChunkX64>(Dir, Helper);
+  case I386:
+    return make<TailMergeChunkX86>(Dir, Helper);
+  case ARMNT:
+    return make<TailMergeChunkARM>(Dir, Helper);
+  case ARM64:
+    return make<TailMergeChunkARM64>(Dir, Helper);
+  default:
+    llvm_unreachable("unsupported machine type");
+  }
+}
+
+Chunk *DelayLoadContents::newThunkChunk(DefinedImportData *S,
+                                        Chunk *TailMerge) {
   switch (Config->Machine) {
   case AMD64:
-    return make<ThunkChunkX64>(S, Dir, Helper);
+    return make<ThunkChunkX64>(S, TailMerge);
   case I386:
-    return make<ThunkChunkX86>(S, Dir, Helper);
+    return make<ThunkChunkX86>(S, TailMerge);
   case ARMNT:
-    return make<ThunkChunkARM>(S, Dir, Helper);
+    return make<ThunkChunkARM>(S, TailMerge);
   case ARM64:
-    return make<ThunkChunkARM64>(S, Dir, Helper);
+    return make<ThunkChunkARM64>(S, TailMerge);
   default:
     llvm_unreachable("unsupported machine type");
   }
 }
 
 EdataContents::EdataContents() {
   uint16_t MaxOrdinal = 0;
   for (Export &E : Config->Exports)

test/COFF/arm64-delayimport.yaml

 # REQUIRES: aarch64
 
 # RUN: yaml2obj < %s > %t.obj
 # RUN: lld-link /entry:main /subsystem:console /out:%t.exe %t.obj %p/Inputs/library-arm64.lib /alternatename:__delayLoadHelper2=main /delayload:library.dll
 # RUN: llvm-objdump -d %t.exe | FileCheck %s -check-prefix DISASM
 # RUN: llvm-readobj --coff-imports %t.exe | FileCheck %s -check-prefix IMPORTS
 
 # DISASM:  140001014:      11 00 00 d0     adrp    x17, #8192
 # DISASM:  140001018:      31 22 00 91     add     x17, x17, #8
-# DISASM:  14000101c:      fd 7b b3 a9     stp     x29, x30, [sp, #-208]!
-# DISASM:  140001020:      fd 03 00 91     mov     x29, sp
-# DISASM:  140001024:      e0 07 01 a9     stp     x0, x1, [sp, #16]
-# DISASM:  140001028:      e2 0f 02 a9     stp     x2, x3, [sp, #32]
-# DISASM:  14000102c:      e4 17 03 a9     stp     x4, x5, [sp, #48]
-# DISASM:  140001030:      e6 1f 04 a9     stp     x6, x7, [sp, #64]
-# DISASM:  140001034:      e0 87 02 ad     stp     q0, q1, [sp, #80]
-# DISASM:  140001038:      e2 8f 03 ad     stp     q2, q3, [sp, #112]
-# DISASM:  14000103c:      e4 97 04 ad     stp     q4, q5, [sp, #144]
-# DISASM:  140001040:      e6 9f 05 ad     stp     q6, q7, [sp, #176]
-# DISASM:  140001044:      e1 03 11 aa     mov     x1, x17
-# DISASM:  140001048:      00 00 00 b0     adrp    x0, #4096
-# DISASM:  14000104c:      00 00 00 91     add     x0, x0, #0
-# DISASM:  140001050:      ec ff ff 97     bl      #-80 <.text>
-# DISASM:  140001054:      f0 03 00 aa     mov     x16, x0
-# DISASM:  140001058:      e6 9f 45 ad     ldp     q6, q7, [sp, #176]
-# DISASM:  14000105c:      e4 97 44 ad     ldp     q4, q5, [sp, #144]
-# DISASM:  140001060:      e2 8f 43 ad     ldp     q2, q3, [sp, #112]
-# DISASM:  140001064:      e0 87 42 ad     ldp     q0, q1, [sp, #80]
-# DISASM:  140001068:      e6 1f 44 a9     ldp     x6, x7, [sp, #64]
-# DISASM:  14000106c:      e4 17 43 a9     ldp     x4, x5, [sp, #48]
-# DISASM:  140001070:      e2 0f 42 a9     ldp     x2, x3, [sp, #32]
-# DISASM:  140001074:      e0 07 41 a9     ldp     x0, x1, [sp, #16]
-# DISASM:  140001078:      fd 7b cd a8     ldp     x29, x30, [sp], #208
-# DISASM:  14000107c:      00 02 1f d6     br      x16
+# DISASM:  14000101c:      01 00 00 14     b       #4 <.text+0x20>
+# DISASM:  140001020:      fd 7b b3 a9     stp     x29, x30, [sp, #-208]!
+# DISASM:  140001024:      fd 03 00 91     mov     x29, sp
+# DISASM:  140001028:      e0 07 01 a9     stp     x0, x1, [sp, #16]
+# DISASM:  14000102c:      e2 0f 02 a9     stp     x2, x3, [sp, #32]
+# DISASM:  140001030:      e4 17 03 a9     stp     x4, x5, [sp, #48]
+# DISASM:  140001034:      e6 1f 04 a9     stp     x6, x7, [sp, #64]
+# DISASM:  140001038:      e0 87 02 ad     stp     q0, q1, [sp, #80]
+# DISASM:  14000103c:      e2 8f 03 ad     stp     q2, q3, [sp, #112]
+# DISASM:  140001040:      e4 97 04 ad     stp     q4, q5, [sp, #144]
+# DISASM:  140001044:      e6 9f 05 ad     stp     q6, q7, [sp, #176]
+# DISASM:  140001048:      e1 03 11 aa     mov     x1, x17
+# DISASM:  14000104c:      00 00 00 b0     adrp    x0, #4096
+# DISASM:  140001050:      00 00 00 91     add     x0, x0, #0
+# DISASM:  140001054:      eb ff ff 97     bl      #-84 <.text>
+# DISASM:  140001058:      f0 03 00 aa     mov     x16, x0
+# DISASM:  14000105c:      e6 9f 45 ad     ldp     q6, q7, [sp, #176]
+# DISASM:  140001060:      e4 97 44 ad     ldp     q4, q5, [sp, #144]
+# DISASM:  140001064:      e2 8f 43 ad     ldp     q2, q3, [sp, #112]
+# DISASM:  140001068:      e0 87 42 ad     ldp     q0, q1, [sp, #80]
+# DISASM:  14000106c:      e6 1f 44 a9     ldp     x6, x7, [sp, #64]
+# DISASM:  140001070:      e4 17 43 a9     ldp     x4, x5, [sp, #48]
+# DISASM:  140001074:      e2 0f 42 a9     ldp     x2, x3, [sp, #32]
+# DISASM:  140001078:      e0 07 41 a9     ldp     x0, x1, [sp, #16]
+# DISASM:  14000107c:      fd 7b cd a8     ldp     x29, x30, [sp], #208
+# DISASM:  140001080:      00 02 1f d6     br      x16
 
 # IMPORTS: Format: COFF-ARM64
 # IMPORTS: Arch: aarch64
 # IMPORTS: AddressSize: 64bit
 # IMPORTS: DelayImport {
 # IMPORTS:   Name: library.dll
 # IMPORTS:   Attributes: 0x1
 # IMPORTS:   ModuleHandle: 0x3000

test/COFF/delayimports-armnt.yaml

 # BASEREL-NEXT:     Address: 0x1000
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT:     Type: ARM_MOV32(T)
 # BASEREL-NEXT:     Address: 0x100C
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT:     Type: ARM_MOV32(T)
-# BASEREL-NEXT:     Address: 0x1022
+# BASEREL-NEXT:     Address: 0x1026
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT:     Type: ABSOLUTE
 # BASEREL-NEXT:     Address: 0x1000
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT:     Type: HIGHLOW
 # BASEREL-NEXT:     Address: 0x3008
 # BASEREL-NEXT:   }
 # BASEREL-NEXT:   Entry {
 # BASEREL-NEXT:     Type: ABSOLUTE
 # BASEREL-NEXT:     Address: 0x3000
 # BASEREL-NEXT:   }
 # BASEREL-NEXT: ]
 #
 # DISASM:      40100c:       43 f2 08 0c     movw r12, #12296
 # DISASM-NEXT:               c0 f2 40 0c     movt    r12, #64
+# DISASM-NEXT:               00 f0 00 b8     b.w     #0
 # DISASM-NEXT:               2d e9 0f 48     push.w  {r0, r1, r2, r3, r11, lr}
 # DISASM-NEXT:               0d f2 10 0b     addw    r11, sp, #16
 # DISASM-NEXT:               2d ed 10 0b     vpush   {d0, d1, d2, d3, d4, d5, d6, d7}
 # DISASM-NEXT:               61 46           mov     r1, r12
 # DISASM-NEXT:               42 f2 00 00     movw r0, #8192
 # DISASM-NEXT:               c0 f2 40 00     movt    r0, #64
-# DISASM-NEXT:               ff f7 e9 ff     bl      #-46
+# DISASM-NEXT:               ff f7 e7 ff     bl      #-50
 # DISASM-NEXT:               84 46           mov     r12, r0
 # DISASM-NEXT:               bd ec 10 0b     vpop    {d0, d1, d2, d3, d4, d5, d6, d7}
 # DISASM-NEXT:               bd e8 0f 48     pop.w   {r0, r1, r2, r3, r11, lr}
 # DISASM-NEXT:               60 47           bx      r12
 
 --- !COFF
 header:
   Machine:         IMAGE_FILE_MACHINE_ARMNT

test/COFF/delayimports.test

 IMPORT-NEXT:   BoundDelayImportTable: 0x0
 IMPORT-NEXT:   UnloadDelayImportTable: 0x0
 IMPORT-NEXT:   Import {
 IMPORT-NEXT:     Symbol: ExitProcess (0)
 IMPORT-NEXT:     Address: 0x140001066
 IMPORT-NEXT:   }
 IMPORT-NEXT:   Import {
 IMPORT-NEXT:     Symbol:  (50)
-IMPORT-NEXT:     Address: 0x1400010BD
+IMPORT-NEXT:     Address: 0x140001072
 IMPORT-NEXT:   }
 IMPORT-NEXT:   Import {
 IMPORT-NEXT:     Symbol: MessageBoxA (0)
-IMPORT-NEXT:     Address: 0x140001114
+IMPORT-NEXT:     Address: 0x14000107E
 IMPORT-NEXT:   }
 IMPORT-NEXT: }
 
 BASEREL:      BaseReloc [
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: DIR64
 BASEREL-NEXT:     Address: 0x3020
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: DIR64
 BASEREL-NEXT:     Address: 0x3028
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: DIR64
 BASEREL-NEXT:     Address: 0x3030
 BASEREL-NEXT:   }

test/COFF/delayimports32.test

 IMPORT-NEXT:   BoundDelayImportTable: 0x0
 IMPORT-NEXT:   UnloadDelayImportTable: 0x0
 IMPORT-NEXT:   Import {
 IMPORT-NEXT:     Symbol: ExitProcess (0)
 IMPORT-NEXT:     Address: 0x401029
 IMPORT-NEXT:   }
 IMPORT-NEXT:   Import {
 IMPORT-NEXT:     Symbol: MessageBoxA (0)
-IMPORT-NEXT:     Address: 0x40103E
+IMPORT-NEXT:     Address: 0x401033
 IMPORT-NEXT:   }
 IMPORT-NEXT: }
 
 BASEREL:      BaseReloc [
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x1005
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x100C
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x101F
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x1025
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
-BASEREL-NEXT:     Address: 0x102C
+BASEREL-NEXT:     Address: 0x102A
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
-BASEREL-NEXT:     Address: 0x1031
+BASEREL-NEXT:     Address: 0x1034
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x1041
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
-BASEREL-NEXT:     Type: HIGHLOW
-BASEREL-NEXT:     Address: 0x1046
+BASEREL-NEXT:     Type: ABSOLUTE
+BASEREL-NEXT:     Address: 0x1000
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x3020
 BASEREL-NEXT:   }
 BASEREL-NEXT:   Entry {
 BASEREL-NEXT:     Type: HIGHLOW
 BASEREL-NEXT:     Address: 0x3024
 BASEREL-NEXT:   }
 BASEREL-NEXT: ]
 
-DISASM:      102b:      68 20 30 40 00  pushl   $4206624
-DISASM-NEXT: 1030:      68 00 20 40 00  pushl   $4202496
-DISASM-NEXT: 1035:      e8 c6 ff ff ff  calll   -58 <.text>
-DISASM-NEXT: 103a:      5a      popl    %edx
-DISASM-NEXT: 103b:      59      popl    %ecx
-DISASM-NEXT: 103c:      ff e0   jmpl    *%eax
-DISASM-NEXT: 103e:      51      pushl   %ecx
-DISASM-NEXT: 103f:      52      pushl   %edx
-DISASM-NEXT: 1040:      68 24 30 40 00  pushl   $4206628
-DISASM-NEXT: 1045:      68 00 20 40 00  pushl   $4202496
-DISASM-NEXT: 104a:      e8 b1 ff ff ff  calll   -79 <.text>
-DISASM-NEXT: 104f:      5a      popl    %edx
-DISASM-NEXT: 1050:      59      popl    %ecx
-DISASM-NEXT: 1051:      ff e0   jmpl    *%eax
+DISASM:      1029:      b8 20 30 40 00  movl    $4206624, %eax
+DISASM-NEXT: 102e:      e9 0a 00 00 00  jmp     10 <.text+0x3d>
+DISASM-NEXT: 1033:      b8 24 30 40 00  movl    $4206628, %eax
+DISASM-NEXT: 1038:      e9 00 00 00 00  jmp     0 <.text+0x3d>
+DISASM-NEXT: 103d:      51      pushl   %ecx
+DISASM-NEXT: 103e:      52      pushl   %edx
+DISASM-NEXT: 103f:      50      pushl   %eax
+DISASM-NEXT: 1040:      68 00 20 40 00  pushl   $4202496
+DISASM-NEXT: 1045:      e8 b6 ff ff ff  calll   -74 <.text>
+DISASM-NEXT: 104a:      5a      popl    %edx
+DISASM-NEXT: 104b:      59      popl    %ecx
+DISASM-NEXT: 104c:      ff e0   jmpl    *%eax

test/COFF/delayimporttables.yaml

 # CHECK-NEXT:   BoundDelayImportTable: 0x0
 # CHECK-NEXT:   UnloadDelayImportTable: 0x0
 # CHECK-NEXT:   Import {
 # CHECK-NEXT:     Symbol: one (0)
 # CHECK-NEXT:     Address: 0x14000104D
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Import {
 # CHECK-NEXT:     Symbol: two (0)
-# CHECK-NEXT:     Address: 0x1400010A4
+# CHECK-NEXT:     Address: 0x140001059
 # CHECK-NEXT:   }
 # CHECK-NEXT: }
 # CHECK-NEXT: DelayImport {
 # CHECK-NEXT:   Name: delayimporttables-dll2.dll
 # CHECK-NEXT:   Attributes: 0x1
 # CHECK-NEXT:   ModuleHandle: 0x3008
 # CHECK-NEXT:   ImportAddressTable: 0x3028
 # CHECK-NEXT:   ImportNameTable: 0x2078
 # CHECK-NEXT:   BoundDelayImportTable: 0x0
 # CHECK-NEXT:   UnloadDelayImportTable: 0x0
 # CHECK-NEXT:   Import {
 # CHECK-NEXT:     Symbol: left (0)
-# CHECK-NEXT:     Address: 0x1400010FB
+# CHECK-NEXT:     Address: 0x1400010B8
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Import {
 # CHECK-NEXT:     Symbol: right (0)
-# CHECK-NEXT:     Address: 0x140001152
+# CHECK-NEXT:     Address: 0x1400010C4
 # CHECK-NEXT:   }
 # CHECK-NEXT: }
 
 --- !COFF
 header:
   Machine:         IMAGE_FILE_MACHINE_AMD64
   Characteristics: [  ]
 sections: