[WebAssembly] Enable IndirectBrExpandPass

[dschuff]

Summary

Wasm doesn't have a direct way to lower indirectbr, so hook up the
IndirectBrExpandPass to lower indirectbr into a switch.

Fixes PR42498

[aheejin]

This is great!

llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h

public:
   const WebAssemblyInstrInfo *getInstrInfo() const override {
     return &InstrInfo;
   }
   const WebAssemblyRegisterInfo *getRegisterInfo() const override {
     return &getInstrInfo()->getRegisterInfo();
   }
   const Triple &getTargetTriple() const { return TargetTriple; }
   bool enableAtomicExpand() const override;
+  bool enableIndirectBrExpand() const override { return true; }
   bool enableMachineScheduler() const override;
   bool useAA() const override;
 
   // Predicates used by WebAssemblyInstrInfo.td.
   bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
   bool hasSIMD128() const { return SIMDLevel >= SIMD128; }
   bool hasUnimplementedSIMD128() const {
     return SIMDLevel >= UnimplementedSIMD128;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

if (!EnableEmException &&
     addPass(createUnreachableBlockEliminationPass());
   }
 
   // Handle exceptions and setjmp/longjmp if enabled.
   if (EnableEmException || EnableEmSjLj)
     addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
                                                    EnableEmSjLj));
 
+  // Expand indirectbr instructions to switches.
+  addPass(createIndirectBrExpandPass());
+
   TargetPassConfig::addIRPasses();
 }
 
 bool WebAssemblyPassConfig::addInstSelector() {
   (void)TargetPassConfig::addInstSelector();
   addPass(
       createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
   // Run the argument-move pass immediately after the ScheduleDAG scheduler

llvm/trunk/lib/Target/WebAssembly/known_gcc_test_failures.txt

 # Tests which are known to fail from the GCC torture test suite.
 
 # Syntax: Each line has a single test to be marked as a 'known failure' (or
 # 'exclusion'. Known failures are expected to fail, and will cause an error if
 # they pass. (Known failures that do not run at all will not cause an
 # error). The format is
 # <name> <attributes> # comment
 
 # Computed gotos are not supported (Cannot select BlockAddress/BRIND)
-20071220-1.c
[phone].c O2
 20071220-2.c
-20040302-1.c
-20041214-1.c O0
-20071210-1.c
-920501-4.c
-920501-5.c
-comp-goto-1.c
-980526-1.c
 990208-1.c
 label13.C O0
 label13a.C O0
 label3.C
-pr42462.C O0
 
 # WebAssembly hasn't implemented (will never?) __builtin_return_address
 20010122-1.c
 20030323-1.c
 20030811-1.c
 pr17377.c
 
 # Error: invalid output constraint '=t' in asm.

llvm/trunk/test/CodeGen/WebAssembly/indirectbr.ll

+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
+
+; This tests that indirectbr instructions are lowered to switches. Currently we
+; just re-use the IndirectBrExpand Pass; it has its own IR-level test.
+; So this test just ensures that the pass gets run and we can lower indirectbr
+
+target triple = "wasm32"
+
[e-mail] = constant [4 x i8*] [i8* blockaddress(@test1, %bb0),
+                                     i8* blockaddress(@test1, %bb1),
+                                     i8* blockaddress(@test1, %bb2),
+                                     i8* blockaddress(@test1, %bb3)]
+
+; Just check the barest skeleton of the structure
+; CHECK-LABEL: test1:
+; CHECK: i32.load
+; CHECK: i32.load $[[DEST:.+]]=
+; CHECK: loop
+; CHECK: block
+; CHECK: block
+; CHECK: end_block
+; CHECK: block
+; CHECK: block
+; CHECK: br_table $[[DEST]]
+; CHECK: end_block
+; CHECK: end_block
+; CHECK: i32.load $[[DEST]]=
+; CHECK: end_loop
+
+; CHECK: test1.targets:
+; CHECK-NEXT: .int32
+; CHECK-NEXT: .int32
+; CHECK-NEXT: .int32
+; CHECK-NEXT: .int32
+
+define void @test1(i32* readonly %p, i32* %sink) #0 {
+
+entry:
+  %i0 = load i32, i32* %p
+  %target.i0 = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i0
+  %target0 = load i8*, i8** %target.i0
+  ; Only a subset of blocks are viable successors here.
+  indirectbr i8* %target0, [label %bb0, label %bb1]
+
+
+bb0:
+  store volatile i32 0, i32* %sink
+  br label %latch
+
+bb1:
+  store volatile i32 1, i32* %sink
+  br label %latch
+
+bb2:
+  store volatile i32 2, i32* %sink
+  br label %latch
+
+bb3:
+  store volatile i32 3, i32* %sink
+  br label %latch
+
+latch:
+  %i.next = load i32, i32* %p
+  %target.i.next = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i.next
+  %target.next = load i8*, i8** %target.i.next
+  ; A different subset of blocks are viable successors here.
+  indirectbr i8* %target.next, [label %bb1, label %bb2]
+}